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2023-09-16mb/google/brya0: Configure _DSC for camera devicesBora Guvendik
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. TEST=Boot to OS, check camera LEDs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib9375d602171aa5018b1add1deac3021724dc207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-16soc/intel/alderlake: Remove ACPI_ADL_IPU_ES_SUPPORTJamie Ryu
DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC is added to mipi camera driver to extend the same support for all SoCs, so removing this config from Alderlake SoC code. BUG=None TEST=Build rex and brya to check if the build passes without an error. Change-Id: I5bc23fce89f0ae22b64b90cb12621320cac30d85 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-09-15mb/google/brya/var/craask: Disable C1 PMC mux conn for HDMIRen Kuo
Add fw_config - DB_1A_HDMI for craaskana, and disable C1 PMC mux conn for HDMI. BUG=b:296791122 TEST=build and check HDMI function works on craaskana Change-Id: Ibaa0cd917a23b7f670ecd648765d1eb566edfe61 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77890 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-09-15soc/intel/xeon_sp: Add missing HDA devicePatrick Rudolph
Change-Id: Icc7974931a9b3f5b5c7a2ed4df2c668dac0cd684 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-09-15xeon_sp/spr: Fix duplicated definesPatrick Rudolph
Change-Id: Ib365a17652b8531e865fa16eae837c68cbedbca8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-09-15vc/intel/raptorlake: Add the FSP v4301.01 headersSean Rhodes
Move the existing FSP 4221.00 headers for Raptor Lake to a subdirectory called 4221.00_google, and select this if the vendor is Google. Add the standard FSP 4301.01 headers to a separate directory, from Intel download #686654, and select this for all other vendors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15drivers/pc80/tpm: Silence warnings when CONFIG_TPM is unsetArthur Heymans
Add some noop device_operations for devices below chip drivers/pc80/tpm in the case CONFIG_TPM is unset. This avoids the warning "... missing read_resources" when probing all devices for resources. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ibc37642a8b5f37b95c648141e03025a04ffa36bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/77386 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15mb/google/rex/var/karis: Disable stylus/FP module based on fw_configTyler Wang
There are going to be skus without stylus and fingerprint module. Disable stylus and fingerprint module based on fw_config. BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I047aae06c4a915d0392edc836757b882a261c178 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77647 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15mb/google/rex/var/karis: Update fw_config settingsTyler Wang
Update fw_config settings for karis: | | | 0 --> STYLUS_ABSENT | | Bit 2 | STYLUS | 1 --> STYLUS_PRESENT | | | | | | Bit 3-5 | AUDIO | 0 --> ALC5650_NO_AMP_I2S | | | | | | Bit 8-9 | MIPI_CAM | 0 --> UF_CAM_HI556 | | | | | | | | 0 --> FP_ABSENT | | Bit 10-11 | FP_MCU | 1 --> FP_MCU_NUVOTON | | | | | | | | 0 --> WIFI_CNVI | | Bit 13 | WIFI_TYPE | 1 --> WIFI_PCIE | BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I1df30ad32d212a36b8a5bd7324f3eb8045b2795c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-15mb/google/dedede/var/dibbi: Swap USB3 ports for A2 and A3Reka Norman
BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port5 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4 Change-Id: I5fe8066e361da62b747464b2ec09bcc6e7dda0fe Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77867 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15soc/intel/jasperlake: Add ACPI names for missing USB3 portsReka Norman
BUG=b:264960828 TEST=On dibbi, ACPI tables contain entries for USB 3.4 and 3.5 Change-Id: If3266d356a2deaf42aa0943f85593416d80637ad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15mb/google/rex: add support for UWBEran Mitrani
UWB on Rex will have 2 options to connect to the SoC: 1. Through GSPI1 (muxed with FP) 2. bit-bang over GPP This CL adds GSPI1 option. BB may be added later. BUG=b:263413448, b:263499898 TEST=UWB ranging works on Rex with this CL Change-Id: I93b3bcef84d775866df43d00c934f013e9f85c47 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76665 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15mb/google/brya/var/pujjo: modify wifi sar table for pujjo1eLeo Chou
1. WIFI_SAR_ID_4: AX211 2. WIFI_SAR_ID_5: AX203 (without WiFi-6E) BUG=b:293360900 TEST=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6c4705d25d927aaefbc8814ea1df3b4c36b30968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77790 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15mb/google/brask/var/kuldax: Add fw_config probe for USB HubDavid Wu
Kuldax-refresh use USB Hub, add fw_config probe for USB Hub. BUG=b:275335023 BRANCH=brya TEST=Built and check firmware log. Change-Id: Ib983ca527a891718f317336597faad66d076247f Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15intelblocks/{pmc,p2sb}: Add missing RPL-S PCH IDs for PMC and P2SBMichał Żygowski
The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based on doc 619362 rev 2.2. Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold bootDinesh Gehlot
This patch addresses the increased boot time issue that occurs when ISH store is enabled, such as in the "rex4es_ec_ish" variant. During a cold reboot, the CBMEM memory resets and loses the stored firmware versions. This causes the firmware versions to be fetched again from the CSE, which increases the boot time by about 200 ms. This patch stores a backup of the firmware version in CMOS and updates the CBMEM memory during a cold reboot. BUG=b:280722061 Test=Verified the changes on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75755 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15soc/intel/cmd/blk/cse: Implement APIs to access CMOS CSE FPT versionsDinesh Gehlot
This patch implements APIs to access the CSE FW partition versions in CMOS. The get API allows users to retrieve the current version from CMOS memory. The set API allows users to set the version in CMOS memory. BUG=b:280722061 TEST=APIs verified on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2023-09-15soc/intel/meteorlake: Remove the check for INFRSean Rhodes
Remove the check to follow the new flow that commit 9c348a7b7ea3 ("soc/intel/alderlake: Fix processor hang while plug unplug of TBT device") introduced. Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie822b8e1fd7592a31275db8455519c4cc6ac02ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/77456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-15soc/intel/meteorlake: Remove space after a castElyes Haouas
Change-Id: Ibf28fbdf791e7aa2faa41f3059150bf5ff5d21d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77735 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14qualcomm/common: Remove carriage returns from QcLib logJulius Werner
The memory log we get returned by QcLib contains Windows line endings ("\r\n"), while we prefer to have POSIX line endings in the CBMEM console (just "\n"). Filter the '\r' character out when copying that log into the CBMEM console to convert. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0652300c2393fbc0b3c9875bb0ca1aa921e59098 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77722 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14x86: Add .data section support for pre-memory stagesJeremy Compostella
x86 pre-memory stages do not support the `.data` section and as a result developers are required to include runtime initialization code instead of relying on C global variable definition. To illustrate the impact of this lack of `.data` section support, here are two limitations I personally ran into: 1. The inclusion of libgfxinit in romstage for Raptor Lake has required some changes in libgfxinit to ensure data is initialized at runtime. In addition, we had to manually map some `.data` symbols in the `_bss` region. 2. CBFS cache is currently not supported in pre-memory stages and enabling it would require to add an initialization function and find a generic spot to call it. Other platforms do not have that limitation. Hence, resolving it would help to align code and reduce compilation based restriction (cf. the use of `ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot code). We identified three cases to consider: 1. eXecute-In-Place pre-memory stages - code is in SPINOR - data is also stored in SPINOR but must be linked in Cache-As-RAM and copied there at runtime 2. `bootblock` stage is a bit different as it uses Cache-As-Ram but the memory mapping and its entry code different 3. pre-memory stages loaded in and executed from Cache-As-RAM (cf. `CONFIG_NO_XIP_EARLY_STAGES`). eXecute-In-Place pre-memory stages (#1) require the creation of a new ELF segment as the code segment Virtual Memory Address and Load Memory Address are identical but the data needs to be linked in cache-As-RAM (VMA) but to be stored right after the code (LMA). Here is the output `readelf --segments` on a `romstage.debug` ELF binary. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x02000000 0x02000000 0x21960 0x21960 R E 0x20 LOAD 0x0219e0 0xfefb1640 0x02021960 0x00018 0x00018 RW 0x4 Section to Segment mapping: Segment Sections... 00 .text 01 .data Segment 0 `VirtAddr` and `PhysAddr` are at the same address while they are totally different for the Segment 1 holding the `.data` section. Since we need the data section `VirtAddr` to be in the Cache-As-Ram and its `PhysAddr` right after the `.text` section, the use of a new segment is mandatory. `bootblock` (#2) also uses this new segment to store the data right after the code and load it to Cache-As-RAM at runtime. However, the code involved is different. Not eXecute-In-Place pre-memory stages (#3) do not really need any special work other than enabling a data section as the code and data VMA / LMA translation vector is the same. TEST=#1 and #2 verified on rex and qemu 32 and 64 bits: - The `bootblock.debug`, `romstage.debug` and `verstage.debug` all have data stored at the end of the `.text` section and code to copy the data content to the Cache-As-RAM. - The CBFS stages included in the final image has not improperly relocated any of the `.data` section symbol. - Test purposes global data symbols we added in bootblock, romstage and verstage are properly accessible at runtime #3: for "Intel Apollolake DDR3 RVP1" board, we verified that the generated romstage ELF includes a .data section similarly to a regular memory enabled stage. Change-Id: I030407fcc72776e59def476daa5b86ad0495debe Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-09-14soc/intel/xeon_sp/spr: Bump MAX_ACPI_TABLE_SIZE_KBPatrick Rudolph
When using Intel(R) Xeon(R) Platinum 8490H on IBM/SBP1 the platform runs with 480 cores. With 480 cores coreboot needs at least 440KiB for ACPI tables. Bump the config to 512 KiB to have some free space for future changes. Change-Id: I2c0bbc36f45aab921f3189459de4438a0cd5dd1f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-09-14mb/siemens/mc_ehl3: Enable PWM passthrough mode on PTN3460Mario Scheithauer
The connected panel on this mainboard gets the PWM frequency directly from the Elkhart Lake CPU. The PWM controls the brightness of the backlight. Therefore, it is necessary to activate the PWM passthrough mode in the PTN3460 eDP-to-LVDS bridge (see PTN3460 Programming Guide - 5. Configuration Registers). Link to PTN3460 Programming Guide: https://web.archive.org/web/20230908074244/https://www.nxp.com/docs/en/application-note/AN11128.pdf BUG=none TEST=Boot into Linux and change the brightness of the screen Change-Id: Ia0a329426e585b6243c8888806befbe4f6ec2998 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-09-14soc/cavium: Use weak over attrbute__((weak))Elyes Haouas
Change-Id: Ia0a6ee85d92f43be6bdae36a13c5dd1a02af3568 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-14acpi: Comply with ACPI specification by making _STR unicode stringsCliff Huang
_STR should return Unicode string. From ACPI spec: 6.1.10 _STR (String) The _STR object evaluates to an Unicode string that describes the device or thermal zone. BUG=NA TEST=Check the changed _STR in SSDT to see if Unicode() macro is used Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I1f4b55a268c1dadbae456afe5821ae161b8e15a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77695 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-14mb/google/rex: Enable DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC for ES ↵Jamie Ryu
variants This enables DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC for rex variants boards with ES SoC to load pre-production signed IPU FW from IPU kernel driver to make Camera function properly. BUG=None TEST=Build rex and check if SSDT-IPU0 includes the correct value for "is_es" with Meteorlake ES and QS SoC. Change-Id: I407d1932762622652939e8568fe34c704bc3b433 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77855 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-14drivers/intel/mipi_camera: Add DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOCJamie Ryu
This adds DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC to provide the option to load pre-production or production signed IPU FW from IPU kernel driver. BUG=None TEST=Build rex and brya to check if the build passes without an error. Change-Id: Ib507bceb6fd85d8ed764df82db400526a10e4d6e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77854 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14mb/google/dedede: Update dibbi ec.h settingsReka Norman
Update the dibbi ec.h so that it's correct for a chromebox. Remove everything related to: - Lid - Battery - Built-in keyboard - AC connect/disconnect - Mode changes BUG=b:294963793 TEST=Boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: Idfa5adcec308d68555d292fddc1db43c9a64d649 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77863 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14mb/google/dedede: Use a separate ec.h for dibbi variantsReka Norman
Dibbi variants are chromeboxes, so they need different settings in ec.h. Add a new dibbi baseboard ec.h and use it for dibbi variants. For now it's identical to the dedede baseboard ec.h. It will be updated in the following CL. BUG=b:294963793 TEST=With the following CL, boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: I4075041ab8f02026623d1a26a555bee5eb09e77b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77782 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2023-09-14acpi.c: Add XSDT on QEMUArthur Heymans
Since d8f2dce "acpi.c: Swap XSDT and RSDT for adding/finding tables" XSDT is primarily used to add new tables or to find the S3 resume vector. However with QEMU coreboot does not generate most ACPI tables but takes them from whatever QEMU provides. Qemu only creates an RSDT and lacks an XSDT. To keep the codebase simple with the assumption that XSDT is always present, create an XSDT based on the existing RSDT and update the address in RSDP. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia9b7f090f55e436de98afad6f23597c3d426bb88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77385 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14chromeos/cse_board_reset.c: Clear EC AP_IDLE flagDerek Huang
When CSE jumps between RO and RW, it triggers global reset so the AP goes down to S5 and back to S0. For Chromebox, when AP goes down to S5 EC set AP_IDLE flag. This cause an issue to warm reset the Chromebox device when it is in recovery mode and powered by USB-C adapter. This patch allows AP to direct EC to clear AP_IDLE flag before trigger reset. BUG=b:296173534 BRANCH=firmware-dedede-136-6.B TEST=Chromebox DUT which is powered by USB-C adapter boots up after warm reset in recovery mode Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77632 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
2023-09-14vc/google/chromeos: Move clear_ec_ap_idle() to common codeDerek Huang
Previously the clear_ec_ap_idle() is implemented in cr50_enable_update.c and be called in the file. Move it to common code so that it can be called in cse_board_reset.c TEST=emerge-brask coreboot Change-Id: I2dbe41b01e70f7259f75d967e6df694a3e0fac23 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-09-13mb/google/brya: Create dochi variantMorris Hsu
Create the dochi variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:299570339 BRANCH=firmware-brya-14505.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_DOCHI Change-Id: Iadeb97bd217278cdf777ae350100313b4345ecf3 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77756 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/google/brya/var/craask: Add audio codec ALC5650Ren Kuo
Add audio codec ALC5650 related settings. BUG=b:289969623 TEST=emerge-nissa coreboot confirm the device in kernel log. Change-Id: I4b8a19e6248bd91cfc31feb84c6108413cd719e2 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77701 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/cmd/blk/cse: Shorten CBMEM field name for better alignmentDinesh Gehlot
This patch shortens the name of the CBMEM field CBMEM_ID_CSE_INFO from "CSE SPECIFIC INFORMATION" to "CSE SPECIFIC INFO" to improve the alignment of the text on the screen. The functionality of the field has not been changed. BUG=NA Test=Boot verified on rex board. Change-Id: I39c716dab7d02d49e7d552cff77d544a1c168433 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77743 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13acpi/soundwire.[ch]: Fix dpn entry array overrunMartin Roth
In soundwire.h, SOUNDWIRE_DPN MIN & MAX are set to 1 and 14. When creating the dpn array, the length was set to MAX - MIN or 13, numbered 0 to 12. When accessing the array, the code was bailing out if a value greater than MAX was trying to be accessed, so the array was able to be overrun by two structure lengths. Fix this problem by: 1) Not subtracting the MIN value when creating the array, which does waste a little space. If anyone wants to refactor the code to fix that, please feel free. 2) Breaking out of the loop when the port is equal to the MAX port number instead of just when it's greater than the max port number. Reported-by: Coverity (CID:1429766 & CID:1429771) Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-09-13mb/google/nissa/var/pujjo: Select VBT based on FW_CONFIG for pujjo1eLeo Chou
Select pujjo1e vbt bin files based on PANEL_IVO_BOE field of FW_CONFIG. BUG=b:299852789 TEST=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I344f97331e79e713af47ad743e27794e21be4ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-13mb/google/brya/var/pujjo: modify fw_config to separate pujjo1e wifi sar tableLeo Chou
Use fw_config for a dedicated pujjo1e intel wifi sar table. BUG=b:293360900 Test=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I635d3d23384cc4efd85b0c420817dd18a65d2872 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77648 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/{alderlake,meteorlake}: Remove the dummy PS0 and PS3 methodsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8515407eb10e1a74f37ea5a80fa31533c38badec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77455 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/{tigerlake,meteorlake}: Check ITBT FW versionSean Rhodes
The ensures that ITBT is ready to operate. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If60404a88208c632cd60e8aaa6ba70494eefbed2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77454 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-13soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPISean Rhodes
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very similar, so can be moved to shared code. This commit aligns minor difference between then, such as comments and tabs/spaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/siemens/mc_ehl5: Enable PWM passthrough mode on PTN3460Mario Scheithauer
The connected panel on this mainboard gets the PWM frequency directly from the Elkhart Lake CPU. The PWM controls the brightness of the backlight. Therefore, it is necessary to activate the PWM passthrough mode in the PTN3460 eDP-to-LVDS bridge (see PTN3460 Programming Guide - 5. Configuration Registers). Link to PTN3460 Programming Guide: https://web.archive.org/web/20230908074244/https://www.nxp.com/docs/en/application-note/AN11128.pdf BUG=none TEST=Boot into Linux and change the brightness of the screen Change-Id: Iec9d8ae22fced40c45e5bfa8989ad655a722d7ef Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77702 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-12soc/amd/*/Makefile: drop wrong EFS diagramsFelix Held
The EFS data structure diagrams in the Makefiles of Picasso and newer SoCs were wrong, since the BIOS directory table pointer is in a different location than shown in the diagram. Since the diagram also wasn't that easy to understand and amdfwtool does all of that handling, drop the wrong diagram from the Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f86fea29f956ff10746d35dbe967a4a89e11cca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-12x86/tables: Upgrade error to criticalPatrick Rudolph
When more ACPI tables are written than space is available in CBMEM, the buffer overflow corrupts other CBMEM tables and a successful boot is unlikely. Upgrade the error message to critical and be more precise what to do. Change-Id: I152842945f552905729265f7d623cd581dd0a8d0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-09-12soc/intel/common: Fix invalid MADT entries creationJeremy Compostella
commit f8ac3dda02f22ebf857efb5b845db97f00598f7d ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm walks all the `cpu_info' entries without discarding empty ones. Since `cpu_info' is not initialized, the data that is used is undefined and it generally results in the creation of invalid `Local x2APIC' entries in the MADT ("APIC") ACPI table. Depending on the X2APIC ID value the Linux kernel behavior changes (cf. arch/x86/kernel/acpi/boot.c::acpi_register_lapic()): 1. If (int)ID >= MAX_LOCAL_APIC (32768), the Linux kernel discards the entry with the "skipped apicid that is too big" INFO level message. 2. If (int)ID < MAX_LOCAL_APIC (32768) (including negative) this data is taken into account and it can lead to undesirable behavior such as core being disabled as (cf. "native_cpu_up: bad cpu" ERROR kernel message). TEST=Verified the MADT does not contain any invalid entries on rex. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77615 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2023-09-12drivers/mipi: sta_himax83102: Completely pull GPW to VGL before TP termRuihai Zhou
The sta_himax83102 panel sometimes shows abnormally flickering horizontal lines. The front gate output will precharge the X point of the next pole circuit before TP term starts, and wait until the end of the TP term to resume the CLK. For this reason, the X point must be maintained during the TP term. In abnormal case, we measured a slight leakage at point X. This is because during the TP term, the GPW does not fully pull the VGL low, causing the TFT to not be closed tightly. To fix this, we completely pull GPW to VGL before entering the TP term. This will ensure that the TFT is closed tightly and prevent the abnormal display. BUG=b:299249186 BRANCH=corsola TEST=FW Screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I5dddaaa38917a65990c1474b657db5eb551940b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77692 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-12arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella
On Intel SoCs, if TME is supported, TME key ID bits are reserved and should be subtracted from the maximum physical addresses available. BUG=288978352 TEST=Verified that DMAR ACPI table `Host Address Width` field on rex went from 45 to 41. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-12cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella
It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11mb/packardbell: Remove space between function name and '('Elyes Haouas
Change-Id: Ied86fb05a3930f1bd900d106b5f3c79466a81a6d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11soc/intel: Remove space between function name and '('Elyes Haouas
Change-Id: I1dbfca33c437c680118eb3a92e60b5607c93e565 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77768 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11mb/lenovo: Remove space between function name and '('Elyes Haouas
Change-Id: I9b1e3ad668c332bebdaf48a2e95f1f9e2131d598 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11mb/google: Remove space between function name and '('Elyes Haouas
Change-Id: I0909f24844fab3dfc859ea8c5325344a9872799f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11arch/arm64: Remove space between function name and '('Elyes Haouas
Change-Id: I0cba99070f251d86679c068bb737c05178f4a7c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77771 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11soc/cavium: Remove space between function name and '('Elyes Haouas
Change-Id: I25e3cf15a77cf61a60bd31519eae019742842389 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11sb/intel: Remove space between function name and '('Elyes Haouas
Change-Id: I2e8eb3632c93b4449f108cb690f9bfd8e1ea3776 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77767 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11nb/intel: Remove space between function name and '('Elyes Haouas
Change-Id: Ibffaf86f9e32d747c8f2f7a3643df8935fb00047 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11soc/nvidia: Remove space between function name and '('Elyes Haouas
Change-Id: I5b0cdb7b8484080db6571d70ddef145bbaf2e87d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77769 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11drivers: Remove space between function name and '('Elyes Haouas
Change-Id: I42e995952a72a23a5f3aeadf428ad13f25546854 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-09security/intel/stm: Remove __attribute__(())Elyes Haouas
Change-Id: Id35a0a589128ea2dfb2f0e5873d4fa087b0886a9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-09soc/amd/common: Remove __attribute__(())Elyes Haouas
Change-Id: I2866dcdd6900c98310b4b3736b40ebe4eaa77ea2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77719 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-09drivers/net/ne2k: Remove space before semicolonElyes Haouas
Also move the semicolon on next line. Change-Id: I68412407ec8c8f99c15f39b0ec08d4fb33eb1b3f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08vendorcode/eltan/security: update attribute useJon Murphy
Update the use of __attribute__((weak)) to the preferred __weak BUG=None TEST=Builds BRANCH=None Change-Id: I75a0e7c03e537be2d38b7f9c6b81eafbb5fb8018 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/purism/librem_cnl: Enable HDMI1 output for Mini native graphics initJonathon Hall
Enable HDMI1 output, which corresponds to the physical DisplayPort connector, so passive adapters to DVI or HDMI will work with native graphics init. Change-Id: I95a147978697f4af092fe61ceacd2e725155d489 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-09-08mb/google/rex: Fix ACPI MPTS method for non-5G board SKUsCliff Huang
MPTS method should only be generated for the board sku with 5G. BUG=NA TEST=Check kernel messages when going to S3. The following errors should not be seen: ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.RP06.RTD3._STA] ACPI Error: Aborting method \_SB.MPTS due to previous error (AE_NOT_FOUND) ACPI Error: Aborting method \_PTS due to previous error (AE_NOT_FOUND) Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I78f434c9049773cf5229d3a1f3934ae82d1fe46d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77690 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08mb/starlabs/starbook/rpl: Enable the PD interrupt GPIOSean Rhodes
Enable the PD interrupt GPIO, GPP_B11, so that HPD works when Thunderbolt is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie37976d58921b7a12dff16d93d7ac9bdd92edbea Reviewed-on: https://review.coreboot.org/c/coreboot/+/77673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/starlabs/starbook/rpl: Correct GPP_A19Sean Rhodes
A19 was incorrectly labelled as TCP0 HPD. It is not connected so configure it accordingly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5aea723c2e8c0758d413bbc4bfd0ce92b22d0c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entriesSean Rhodes
Certain devices are enabled in Alder Lakes chipset.cb, so remove them from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/google/rex: Require VBOOT_LID_SWITCH for Chromebook designSubrata Banik
This patch ensures that platforms with lids, such as Chromebooks, only select the VBOOT_LID_SWITCH configuration option. Only samples the LID GPIO if VBOOT_LID_SWITCH config is enabled, otherwise fake LID is open to avoid shutdown after reaching depthcharge. Tested by building and booting Google/Rex with the VBOOT_LID_SWITCH configuration option enabled, and verifying that google/ovis does not required VBOOT_LID_SWITCH config. Change-Id: Ic5123b822a5a7021023319cb08a3f9e5225961ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77693 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-08vc/intel/fsp2/alderlake_n: Drop unused header filesFelix Singer
Change-Id: I870fa65ff05cf5907d62b3af1b2f9c4334b62603 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77260 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08soc/intel/alderlake_n: Hook up the FSP repositoryFelix Singer
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-08arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07drivers/pc80/vga/vga_io: Remove unnecessary parenthesesElyes Haouas
Parentheses are not required. Change-Id: Iad1f766a3eb569af39030e43365e8a0a609f5944 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77706 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07security/intel: Remove unnecessary blank line after '{'Elyes Haouas
Change-Id: I0d2a9c30d332b16efd548433a54f974067bd281e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07drivers/siemens/nc_fpga/nc_fpga: Remove space before '++'Elyes Haouas
Change-Id: I6ff11df45ddc396391efd651f9938e04646dc0d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77707 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-07ec/lenovo/h8/h8.c: Use sizeof()Elyes Haouas
Use 'sizeof(ecfw)' instead of 'sizeof ecfw'. sizeof operator should only be used for types and variables require sizeof(). Change-Id: Ifae1680917bb0ce610e6ba753741aae233a71103 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-07mb/google/myst: Set i2c2 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I41fc7f847ef08138cb0f430bfd1a170f209163f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77681 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/zork: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I19f0a5a72ec409b306be7bc4bb53425870fc6298 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-07mb/google/skyrim: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: Idb5d2cd6eca2a2746e89a371005332e9f621df83 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77675 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/guybrush: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I22b3ccc2c89a3f7ababd0eaf4e35604880aa0ce7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-07mb/google/nissa/var/craask: Modify SD_CARD element to prevent confuseTyler Wang
Modify SD_CARD element "SD_GL9750S" to "SD_PRESENT" to prevent confusion. Origin: 0 --> SD_GL9750S Modify: 0 --> SD_PRESENT BUG=b:296505165 TEST=emerge-nissa coreboot Change-Id: Ic355b7df9f9added4489a764f774851f2e4451c3 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-09-07soc/intel/meteorlake: Update LidStatus UPD dynamicallySubrata Banik
This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:299137940 TEST=Able to build and boot google/rex to redirect the display using external HDMI monitor while LID is closed. Change-Id: I7d7b678227a6c8e32114de069af8455b8c1aa058 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07mb/google/rex/var/karis: Update MIPI User facing camera settingsTyler Wang
Update overridetree and GPIO settings for MIPI UFC due to updated schematic updates. BUG=b:298133153 TEST=emerge-rex coreboot Change-Id: I4c3197e3f15e0cb3fc640b1749d8681299981563 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77591 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-09-07mb/google/brya/var/{kano,osiris,taeko}: Add null pointer checkWisley Chen
Without part no. in CBI, mainboard_get_dram_part_num returns null. To prevent passing this null pointer to strcmp and avoid unexpected behavior, proper handling is necessary. BUG=none TEST=emerge-brya coreboot Change-Id: I47e42376c6b1347c56afaec218aed63c5469f0aa Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77646 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/brya/var/yavilla: Add VBT data fileRobert Chen
Add data.vbt file for yavilla recovery image. Select INTEL_GMA_HAVE_VBT for yavilla which currently have a VBT file. BUG=b:298320552 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I72f98181b3487f8ae9acf6e0f2382a0204f7989c Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-06device/pci_rom: rename pci_rom_acpi_fill_vfct()Matt DeVillier
Rename pci_rom_acpi_fill_vfct() to ati_rom_acpi_fill_vfct() to make it clear that the function is only used for AMD/ATI VGA option ROMs. Change-Id: I0e310dd2d7a0432918861632e09a23e162082ea5 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77634 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06device/pci_rom: Set VBIOS checksum when filling VFCT tableMatt DeVillier
AMD's Windows display drivers validate the checksum of the VBIOS data in the VFCT table (which gets modified by the FSP GOP driver), so ensure it is set correctly after copying the VBIOS into the table if the FSP GOP driver was run. Without the correct checksum, the Windows GPU drivers will fail to load with a code 43 error in Device Manager. Thanks to coolstar for root causing the issue. TEST=build/boot Win11 on google/skyrim (frostflow), ensure GPU driver loaded and functional. Change-Id: I809f87865fd2a25fb106444574b619746aec068d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-09-06soc/amd: correctly report I2C controller state in ACPIFelix Held
Instead of reporting all I2C controllers in the system as enabled in the corresponding ACPI device's _STA method, report the I2C devices that are disabled in the devicetree as disabled in the corresponding _STA method too. This is done by returning the contents of the STAT variable inside each device's scope in the DSDT that have a default value of 0 (device not present/disabled). For all enabled and hidden I2C devices i2c_acpi_fill_ssdt gets called which then writes 0xf (device enabled and visible) or 0xb (device enabled, but hidden) to the STAT name inside the same scope, but in the SSDT. This object in the SSDT will then override the default in the DSDT resulting in the _STA method returning the correct status of each device. The code was inspired by commit 7cf9c7451808 ("soc/amd/*: Fix UART ACPI device status"). TEST=On Mandolin all I2C controllers are disabled and with this patch none shows up in the Windows 10 device manager. When enabling an I2C controller in the devicetree for testing, it shows up again in the Windows device manager. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4cd9f447ded3a7f0b092218410c89767ec517417 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-06soc/intel/common/block/acpi: Change __attribute__((weak)) to __weakElyes Haouas
Change-Id: I9ecd81ffaa48dbed225a23900704b259569cb7c8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77527 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06google/puff: Enable ASPM of RTL8111HAlexis Savery
With kernel 5.15, puff hangs during power idle tests because the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in devicetree for RTL8111H to enable ASPM L1.2. BUG=b:268859220, b:279618219 TEST=emerge and run power.Idle Change-Id: I129dfd79e8112191453be513b2e3a260429b3030 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06google/puff: remove workaround that toggled the #ISOLATE pinAlexis Savery
A workaround was added for puff to assert/deassert the #ISOLATE pin during suspend/resume to resolve the situation where the realtek ethernet device cannot enter L1.2 mode when its ASPM is disabled. The realtek driver has since been fixed and ASPM of realtek devices have been enabled on kernel 5.10 and 5.15 and this original workaround is now causing suspend/resume errors on kernel 5.15: r8169 0000:01:00.0: Unable to change power state from D3cold to D0, device inaccessible Puff devices were originally shipped with kernel 4.19, and applying this change to the firmware on a device running 4.19 causes suspend/resume failures, basically reversing the problem. We are upreving the puff kernel to 5.15 so we need this patch, but since it is incompatible with 4.19 we will have to take that into consideration when pushing new firmware and potentially will need to backport the necessary fixes to 4.19. BUG=b:268859220 TEST=suspend_stress_test -c 500 on wyvern Change-Id: I5eead2d70cd9528b3ca3fadd11f98c0330601324 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77378 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-09-06mb/google/nissa/yaviks: Disable V1P05 control pinWisley Chen
Yaviks already disabled external V1P05, so disable V1P05 control pin which controls the VCC_V1P105_EXT_1P05. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I4128cfcfa5be0d141f0173e87518407331d79e8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77645 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05soc/amd/common/vboot: Drop reporting of Silicon levelMatt DeVillier
Per the PSP team, this field in the transfer buffer isn't used anymore and always set to zero, causing devices to incorrectly report having pre-production silicon. Change-Id: Ida4bf4b9328ac83d905e4c3f822e6ceabe9be79d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77630 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-09-05mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_configShon Wang
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage. SAR_ID_0 : Yaviks_Gfp2 SAR_ID_1 : Yaviks & Yavilla_MT7921 SAR_ID_2 : Yahiko_Gfp2 SAR_ID_3 : Yavilla_MT7922 BUG=b:298138654 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I2f191683d0623aa5dce815998a24fddce2a36b2c Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77559 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05amdfwtool: Add FW type FUSE_CHAIN in the config fileZheng Bao
We don't have file for the fuse chain, but we need to set the level for some cases. Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-05mb/siemens/fa_ehl: Process LPDDR4 SPD files and add MT53E512M32D1NP SPDJohannes Hahn
The board uses soldered down LPDDR4, so process their SPD files, and add the SPD for Micron MT53E512M32D1NP-046WTB provided by Micron. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I978b7450b106b86eef322df8b33df41e038599eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/77349 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-09-05mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIGWisley Chen
Configure the AUX pins as NC based on the FW_CONFIG setting when the C1 port is not present. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-05mb/google/nissa/var/yavilla: Restore WLAN_PERST_L power sequenceTony Huang
Restore TPERST_HIGH to 160ms since it has beed validated in other OEM projects and haven't heard any issue so far. This change back commit d710c6d5a773 ("mb/google/nissa/var/yavilla: Adjust WLAN_PERST_L power sequence"). BUG=b:295277868 TEST=emerge coreboot boot to system and check wifi connection is fine Change-Id: Ifc66e596fc7b6efdc0c286ee187969c8774bdc80 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-05mb/google/nissa/var/pirrha: Use GpioInt instead of GPE for digitizer penSeunghwan Kim
Currently pirrha's digitizer pen uses GPP_F12 for I2C HID interrupt signal. But its IRQ number is the same as GPD2, which is used as EC_SYNC_IRQ. It caused EC driver loading error from dmesg: cros_ec_lpcs GOOG0004:00: Failed to request IRQ 98: -16 cros_ec_lpcs GOOG0004:00: couldn't register ec_dev (-16) cros_ec_lpcs: probe of GOOG0004:00 failed with error -16 So change the digitizer pen interrupt type to GpioInt to prevent the conflict. BUG=b:292134655 TEST=Verified EC driver reported no error and pen device worked Change-Id: Ieb88e87fcfb06544a4b5b5133b752aa821fab76a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77346 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05mb/google/nissa/var/pirrha: Update device configurationsSeunghwan Kim
Based on schematics and gpio table of pirrha, generate overridetree.cb to configure internal devices and generate fw_config.c to override GPIO configurations following FW_CONFIG. BUG=b:292134655 TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: I91013b0ad89e26f0a4c433c305c6b883d000f042 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77116 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jimmy Su <jimmy.su@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-09-05mb/amd/onyx: Add FMD file and update romsizeArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Idd6f711f5ca5c8a421c0c38edd404b1900bb29b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76497 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 21:15:19 +0000