diff options
| author | Eran Mitrani <mitrani@google.com> | 2023-07-21 12:02:33 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-15 13:41:08 +0000 |
| commit | b4f9c8d86ac2aa9664a1d8c7cda1d28870052d22 (patch) | |
| tree | a2df6b528fd418999318c534057a61257c7be3ac /src | |
| parent | 66d846f64aec0dffb5024334d7f5cba920151c68 (diff) | |
mb/google/rex: add support for UWB
UWB on Rex will have 2 options to connect to the SoC:
1. Through GSPI1 (muxed with FP)
2. bit-bang over GPP
This CL adds GSPI1 option. BB may be added later.
BUG=b:263413448, b:263499898
TEST=UWB ranging works on Rex with this CL
Change-Id: I93b3bcef84d775866df43d00c934f013e9f85c47
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76665
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rex/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/fw_config.c | 23 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 15 |
3 files changed, 38 insertions, 1 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 52f241349a..6af9b699bb 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -53,6 +53,7 @@ config BOARD_GOOGLE_MODEL_REX select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_ISH select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_NXP_UWB_SR1XX select DRIVERS_SOUNDWIRE_CS42L42 select DRIVERS_SOUNDWIRE_MAX98363 diff --git a/src/mainboard/google/rex/variants/rex0/fw_config.c b/src/mainboard/google/rex/variants/rex0/fw_config.c index ce5fe8d03c..86cb78102e 100644 --- a/src/mainboard/google/rex/variants/rex0/fw_config.c +++ b/src/mainboard/google/rex/variants/rex0/fw_config.c @@ -116,6 +116,20 @@ static const struct pad_config touchscreen_spi_int_pads[] = { PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, EDGE_SINGLE, INVERT), }; +static const struct pad_config uwb_gspi1_enable_pads[] = { + PAD_CFG_GPO_LOCK(GPP_D07, 0, LOCK_CONFIG), /* FPMCU_UWB_MUX_SEL */ + PAD_CFG_GPO(GPP_E06, 0, DEEP), /* UWB_SOC_SYNC */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), /* EN_PP1800_UWB */ + PAD_CFG_GPI_INT(GPP_F20, NONE, PLTRST, LEVEL), /* UWB_SOC_INT */ +}; + +static const struct pad_config uwb_gspi1_disable_pads[] = { + PAD_CFG_GPO_LOCK(GPP_D07, 1, LOCK_CONFIG), /* FPMCU_UWB_MUX_SEL */ + PAD_NC(GPP_E06, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (!fw_config_is_provisioned()) { @@ -161,4 +175,13 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) printk(BIOS_INFO, "Configure Touchscreen Interrupt for SPI.\n"); GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_spi_int_pads); } + + if (fw_config_probe(FW_CONFIG(UWB, UWB_GSPI1)) && + fw_config_probe(FW_CONFIG(FP, FP_ABSENT))) { + printk(BIOS_INFO, "Configure GPIOs for UWB over GSPI1.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, uwb_gspi1_enable_pads); + } else { + printk(BIOS_INFO, "Disabling UWB (absent or misconfigured)\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, uwb_gspi1_disable_pads); + } } diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index c08ff2b493..c3c4372668 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -776,8 +776,21 @@ chip soc/intel/meteorlake register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" register "enable_delay_ms" = "3" - device spi 0 on end + device spi 0 on + probe FP FP_PRESENT + end end # FPMCU + chip drivers/nxp/uwb + register "name" = ""UWB0"" + register "desc" = ""NXP UWB Module"" + register "speed" = "1000000" # 1 MHZ + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_HIGH(GPP_F20)" + register "ce_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F19)" + register "ri_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E06)" + device spi 0 on + probe UWB UWB_GSPI1 + end + end # UWB end device ref soc_espi on chip ec/google/chromeec |