summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2022-09-12src/soc/intel/mtl: Remove Storage UPDSrinidhi N Kaushik
This change removes all references to HybridStorageMode UPD since it has been deprecated starting from FSP v2344_00 BUG=b:245167089 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12mb/google/brya/acpi: Move dGPU power checks earlierTim Wawrzynczak
Linux always "turns on" a PowerResource when it boots, regardless of _STA, so the _ON routine should be idempotent. In this case, it all is, except for the LTR restore, which would restore a value of 0 when _ON is run the first time, which means that LTR is disabled on the root port from then on, as the save/restore routines will keep saving/restoring that 0. THis patch fixes the problem by moving the power checks from PGON/PGOF to GCOO/GCOI. BUG=b:244409563 TEST=boot agah and verify that LTR is still enabled on the root port Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67278 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12mb/google/brya/acpi: Remove erroneous _PR0/_PR3Tim Wawrzynczak
The Linux kernel runtime D3 framework expects a PCIe device to have a power resource in order to be properly power-manageable. The _PR0/_PR3 values were pointing at the PEG0 Device, which is not a PowerResource, so this must have confused the RTD3 framework and RTD3 was not functional. Removing the _PR0/_PR3 fixes the problem. BUG=b:243888246 TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control; sleep 10; echo on > /sys/bus/pci/devices/0000:01:00.0/power/control After this there are no longer errors seen in dmesg about failing to place the device into D0. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/67212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-12mb/google/brya/acpi/power: Clean up ASL codeTim Wawrzynczak
Mostly there are too many extraneous `\_SB.PCI0.` prefixes, also a few minor cleanups, but nothing functional. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I79d919d2f04f57232f8f6a4e4d0690833faeb834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12mb/google/brya/acpi: Save/restore/clear some registers over GCOFFTim Wawrzynczak
Similar to the prior CL (commit db8ad5e), do the same register dance before/after GCOFF. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67086 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12soc/intel/adl: Disable D3cold when legacy S3 is enabledLean Sheng Tan
D3Cold isn't supported in S3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I072f47737ef38c44b6a676019e9a73868ff17e5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67413 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12drivers/intel/ptt: Use the correct detection methodMichał Żygowski
On some platforms the HFSTS4 bit 19 does not indicate active PTT. Instead of ME HFSTS4, use TXT FTIF register to check active TPM for the current boot. Discrete TPM shall be deactivated when PTT is enabled so this always should return true value of PTT state. Leave the old method for backwards compatibility if TXT FTIF would not be applicable for older microarchitectures. Based on DOC #560297. TEST=Check if PTT is detected as active on MSI PRO Z690-A DDR4 WIFI Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a55c9f38f5bb94fb1186592446a28e675c1207c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-09-12qualcomm/sc7280: remove unnecessary malloc and early return on failureVinod Polimera
Instead of just printing the fatal errors, do early return so that boot up time will be reduced during display init failure. Remove malloc allocation and make tu a local variable. Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66975 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12soc/amd: Refactor DPTC Tablet ModeTim Van Patten
Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-10mb/google/rex: Complete several remaining GPIO configsTarun Tuli
Lists of GPIO PINS being updated: SPKR_INT_L_R RST_HP_L SOC_HDMI_HPD_L SOCHOT_ODL SOC_FPMCU_INT_L EN_PP3300_WLAN BUG=b:24410269 TEST=Build and boot Google/Rex to ChromeOS. Change-Id: If2fb354f931217c09a6c1c81ca780cb121b24468 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67449 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-10mb/google/rex: Enable touchpadKapil Porwal
Enable touchpad for Google Rex. BUG=b:245866939 TEST=Build and boot to Google Rex. Verify touchpad works. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I49fdd72bf3350085e82411b95edcd6a9a09d2df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67471 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
2022-09-10mb/google/rex: Add GPE route for GPP_BKapil Porwal
Add GPE route for GPP_B. BUG=b:245866939 TEST=Build and boot to Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I28066a6cc75908f8ceefbdbf8c088c56833606ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/67469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-10soc/intel/meteorlake: Hook up common code for thermal configurationSubrata Banik
Thermal configuration registers are now located behind PMC PWRMBASE for MeteorLake as well (same as ADL). Hence, using thermal common code to sets the thermal low threshold as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on Google/rex prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Update `pch_thermal_trip` for MTLSubrata Banik
This patch updates `pch_thermal_trip` as per Intel MTL vol1 chapter 14. Additionally, dropped the `FIXME` tag for `pch_thermal_trip`. TEST=Able to boot the Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Drop redundant `MCHBAR` programming in romstageSubrata Banik
This patch drops redundant MCHBAR programming in romstage as bootblock already done with MCHBAR setting up. TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct value as per iomap.h Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10soc/intel/meteorlake: Disable FSP UPDs related to virtualizationSubrata Banik
This patch disables FSP UPDs (`VtdDisable` and `VmxEnable`) as kernel cmdline still passes `intel_iommu=off` to turn off virtualization. BUG=b:241746156 TEST=Able to boot Google/rex to ChromeOS UI. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67452 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-09mb/google/brya: Invoke power cycle of FPMCU on startupTarun Tuli
Add functionality such that the FPMCU is power cycled and has its reset sequenced on boot. This has been added such that we do not need to update the bootblock. We are required to do this as bootblock exists in read-only flash for devices that have already been manufactured and so have no method of updating the sequencing there. Power remains off during coreboot (after briefly being turned on in the unchangeable bootblock). Once control is handed over to the Kernel, it takes care of sequencing the power and reset appropriately and ensures the FPMCU is unpowered for >200ms on boot. BUG=b:240626388 TEST=Confirmed FPMCU is still functional on Vell and Anahera. Confirmed power is off for approximately 6 seconds on boot (target >200ms). Confirmed reset is de-asserted approx 5ms after power application (target >2.5ms) Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-09mb/prodrive/atlas: Set i225 PCIe RP as built inLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4436a9d75cb06f2f51979f2bc57d48fa3dbb9e00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67411 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09mb/prodrive/atlas: Enable resizable BAR supportLean Sheng Tan
Allow up to 4GiB resizable BAR support. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I097483ba8b4479211f67f29a42754d1a51379771 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-09mb/prodrive/atlas: Configure Acoustic noise mitigationLean Sheng Tan
- Enable Acoustic noise mitigation - Set slow slew rate to fast/4 for VCCIA and VCCGT - Disable fast slew rate for deep package C states for VCCIA and VCCGT Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia344d9d939c3323bac82afdf25d5fff81081f9c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67380 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-09soc/mediatek/mt8186: Enable lastbus debug hardwareot_zhenguo.li
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. TEST=build pass. BUG=none Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: Iff39486dfad556a3104b2f2b6811c34c2ded6954 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-09soc/mediatek/mt8186: Enable the protection of DEVAPCRunyang Chen
Enable the protection for DEVAPC registers of AO domain. TEST=build pass. BUG=b:244250435 Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I8535438d4c7da29c9dcd97be9a2af05ea4690064 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67434 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09soc/mediatek/mt8186: Complete DEVAPC settingsRunyang Chen
In the previous patch (CB:60317), only basic settings were added. Now complete DEVPAC settings on MT8186. 1. Update permission setting 2. Update master domain setting: - domain 4: SCP - domain 5: SPM 3. Set domain remap - MMSYS (4-bit to 2-bit) TEST=test on kernel correctly. BUG=b:204229221 Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I40a9b115fb21b6b955fde358241f4483b85e3db3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67433 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09soc/mediatek/mt8186: Enable CPU power hardware tracking for PMIC MT6366Sen Chu
1. There are two power sources for CPU: - Logic power (VPROC). - SRAM power (VSRAM_PROC). 2. There is a constraint between VPROC and VSRAM_PROC: - 0mV <= VSRAM_PROC - VPROC <= 250mV. With software control, the constraint might not always hold. Therefore, we enable hardware tracking from PMIC MT6366 to ensure the constraint is met automatically. BUG=b:236353282, b:241615706 TEST=meet the constrain correctly when adjusting the voltage. Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Change-Id: I6012c57e60c009f1d599b57aab1c2526ee789208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67436 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09mb/google/nissa: Disable the stylus GPIO pins based on fw_configV Sowmya
TEST=Boot to OS on nivviks/nirwen and check that stylus GPIOs are configured based on fw_config. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ibbe9f379abe10a741642e11d4833d3a53489693a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66929 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rplBora Guvendik
Configure GPIO pins, add Kconfig options and enable TPM device in devicetree. Add H1 TPM IRQ GPIO pin in gpio.c BUG=none BRANCH=firmware-brya-14505.B Cq-Depend: chromium:3774914 TEST=Boot the image and check the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-09-09mb/google/dedede/var/shotzo: Config I2C times for touchscreen/audioTony Huang
Config I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). EE measured touchscreen/audio runs at 385.5/397.9kHz after tuning. BUG=b:244403643 BRANCH=firmware-dedede-13606.B TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: I7d9503e5f92295432e31f09ae791eaa18eac9d4d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-09-09mb/google/brya/var/skolas4es: Configure _DSC for camera devicesBora Guvendik
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:194979741 BRANCH=firmware-brya-14505.B TEST=Build and boot skolas to OS. Verify entries in SSDT. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3c32dd71ab454227b15913bda7f542230e5568db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-09mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier
Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-08mb/prodrive/atlas: Disable POST codes by defaultLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib1dd9826cedfd0a3f1ed719cf2e2927f09f783fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67427 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/prodrive/atlas: Update VBT data binaryLean Sheng Tan
The previous VBT binary was not properly configured, there were DP display issues on some of the ports and resulted in hangs when FSP debug was used. The updated VBT fixes all the issues. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I788240e36a9a90a5342ee9761f2c61ebf4caa9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67426 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/google/grunt: Enable AC wakeDaisuke Nojiri
This patch enables AC plug/unplug for resume. BUG=b:188457962 BRANCH=grunt TEST=Verified AC plug/unplug wakes up Treeya. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I10480f8224b909fefe42d46d7c03fc9d3fe5abfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-08mb/google/zork: Enable AC wakeDaisuke Nojiri
This patch enables AC plug/unplug as resume signals. BUG=b:188457962 BRANCH=Zork TEST=Verified AC plug wakes up Ezkinil. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Ib1af6ff9f18544ec6a86e34588fb4d9e8cd3bab2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-09-08soc/intel/meteorlake: Hook up PAVP to KconfigSubrata Banik
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. TEST=Able to boot Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416346995d744990054c8e0c839ada82c84b7550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/google/brya/var/kinox: Update the DPTF parameters and fan tableDtrain Hsu
Follow the Thermal_paramters_list-0902.xlsx to modify DPTF parameters and fan table. 1. Modify CRT of TSR0 - TSR3 to 97. 2. Modify TCC offset to 6. 3. Update new fan table. BUG=b:244657172 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67314 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/google/brya/var/kinox: Modify fan speed/duty tableDtrain Hsu
Modify fan speed/duty table follow "Duty table.xlsx". BUG=b:244262869 TEST=Boot to ChromeOS. Using SDV system, enter duty value, and then system feedback fan speed. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-08acpi/acpigen_dptf: Increase DPTF_MAX_FAN_PERF_STATES to 20Dtrain Hsu
The Kinox fan speed/duty table has 20 elements so raise the DPTF_MAX_FAN_PERF_STATES from 10 to 20. BUG=b:244262869 TEST=Boot to ChromeOS. Using SDV system, enter duty value, and then system feedback fan speed. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iacd3ef0da926df5d174b215ab8ea4adc1a8b672e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67390 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-08mb/google/rex: Add WWAN poweron sequencingIvy Jian
The PCIe WWAN module used on rex requires control over 4 signals to successfully power it on. It is desirable to do this before passing control to the payload, because the modem requires a ~10 seconds initialization phase before it can be used. The corrected sequence looks like: 1) Drive device into full reset and enable power in bootblock 2) Deassert FCPO in romstage, after power rails stabilize 3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage BUG=b:244077118 TEST=FM350 could be enumerated via lspci Measured signals to check start-up Timing Sequence, tpr/ton1/ton2. Tpr = 572mS Ton1 = 6.3s Ton2 = 6.3+4.17ms Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/starlabs/lite/{glk,glkr}: Enable SRAMSean Rhodes
Enable SRAM in devicetree so that resources are allocated properly for it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibdd2ee455f5bf6cd95bba6bab8689da664bfcf54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-08soc/intel/common/smbus: Add missing ID for GLKSean Rhodes
PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I31d4b7edf3288794c86a6d2b78acdc4cf0ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08soc/intel/commmon/fast_spi: Add missing ID for GLKSean Rhodes
PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5812e536f3e1c49a272a0b337cc69f3d8f30677f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67402 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/amd/chausie/ec.c: Clean up definesFred Reitberger
Use the BIT() macro instead of reinventing the wheel. TEST=timeless builds are identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I873013feebd30c86290dda692c7b137d5f3c4729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-08device/pci_device: Add missing spaces to log messagesPaul Menzel
Add the missing spaces to two log message, like the one below. WARNING: Device PCI: 03:00.0 requests a BAR with34 bits of address space, which coreboot is notconfigured to hand out, truncating to 29 bits Change-Id: If933d8fb0db5b58ff12f043cc73172a3f6ffc624 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-08soc/intel/alderlake: add power limits for Alder Lake-N 7W socSimon Yang
Missing power limit setting for Alder-Lake-N 7W soc. Document reference: 645548 and 646929 BUG=b:245440443 BRANCH=None TEST=Build FW and test on nivviks board and there is no error message "unknown SA ID: 0x4617, skipped power limits configuration." Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-08guybrush: remove RO_GSCVD area from FMAPHimanshu Sahdev
This area relates to storing of AP RO verification information. CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and guybrush is using TPM_GOOGLE_CR50. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Harsha B R <harsha.b.r@intel.com>
2022-09-08src: De-conflict CALIBRATION_REGION definitionsMartin Roth
Change the name of the CALIBRATION_REGION definitions used in two separate locations. This conflict was causing an error for the lint-001-no-global-config-in-romstage test. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-08drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-SReka Norman
Currently, the "loading FSP-S" timestamp is added in fsp_silicon_init(). However, most Intel platforms actually load FSP-S earlier than this, in soc_fsp_load(). So the timestamp is added in the wrong place. Add the timestamp in fsps_load() instead, after the load_done early return so that it will only be added for the first call. Before: 949:finished CSE firmware sync 961,833 (17,998) 17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495) 18:finished LZ4 decompress (ignore for x86) 1,018,797 (469) 30:device enumeration 1,035,096 (16,298) 971:loading FSP-S 1,048,082 (12,986) 954:calling FspSiliconInit 1,049,331 (1,249) After: 949:finished CSE firmware sync 959,355 (16,370) 971:loading FSP-S 978,139 (18,784) 17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656) 18:finished LZ4 decompress (ignore for x86) 1,016,271 (475) 30:device enumeration 1,032,567 (16,295) 954:calling FspSiliconInit 1,046,867 (14,300) BUG=b:239769975 TEST="loading FSP-S" is added in the right place on nivviks (see above). Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-08soc/mediatek/mt8188: Enable ARM Trusted Firmware integrationRex-BC Chen
Enable configuration to build with MT8186 arm-trusted-firmware drivers. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id16405c84f6e0a2e21f95cc45babf85bd980b43e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67356 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/intel/adlrvp: Make SOC_INTEL_CSE_LITE_SKU configurableMaximilian Brune
Having a CSE Lite SKU's firmware is not necessarily depending on the underlying hardware nor on having ChromeOS installed as already mentioned in commit f3419b29b7e0 ("soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKU"). For example RVP Boards sometimes have a CSE LITE FW, if Chrome board related stuff is tested, which doesn't necessarily imply a ChromeOS being used. It is therefore changed to an option, which can be changed in menuconfig. Change-Id: I4da7feab881ae43528c9d852cc842ac93fa9c6de Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67078 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07soc/amd/mendocino/Kconfig: Enable APOB_HASHFred Reitberger
Enable the APOB_HASH feature. This improves boot times by ~10ms. BUG=b:193557430 TEST=boot to OS and verify boot time improvement Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9628b67cd3206ffdbef23162c453dc183c69e5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67377 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07soc/amd/common/block/apob: Add hashed APOB supportFred Reitberger
Comparing the APOB in RAM to flash takes a significant amount of time (~11ms). Instead of comparing the entire APOB, use a fast hash function and compare just that. Reading, hashing, and comparing the hash take ~70 microseconds. BUG=b:193557430 TEST=compile and boot to OS in chausie with and without this option set Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I241968b115aaf41af63445410660bdd5199ceaba Reviewed-on: https://review.coreboot.org/c/coreboot/+/67301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07lib/xxhash.c: Add new hash functionsFred Reitberger
Add xxhash functions. This is a very fast hash function, running at RAM speed limits. This code was adapted from the linux kernel with minor modifications to make it fit in coreboot. BUG=b:193557430 TEST=compile Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8108af5ab14d8e6c6f5859bd36155c7d254e892c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07amd: Convert dptc_enable to boolTim Van Patten
dptc_enable is being treated as a bool, so convert to explicitly be a bool. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim Change-Id: I0e93d892b3b8016221812c8b9ec6c257dcf13ef5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67188 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50Werner Zeh
Due to layout restrictions on mc_ehl2, the SD-card interface is limited to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not supported. Limit the capabilities in the SD card controller to DDR50 mode only so that the SD card driver in OS will choose the right mode for operation even if the attached SD card supports higher modes. Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07mb/siemens/mc_ehl2: Set I2C bus 1 speed to 100 kHzWerner Zeh
Since the new RTC is located in I2C bus 1 now, set the bus speed to 100 kHz as well. Change-Id: Ica9468e559bc654545592a9b4d23f3164eafca8a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67102 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/siemens/mc_ehl2: Change to new RTC RV3028-C7Werner Zeh
Since the latest redesign a new RTC was introduced on mc_ehl2. Instead of the old RX6110SA the new Micro Crystal RTC RV3028 is used now. Since the address of this new RTC conflicts with an EEPROM on I2C bus 2, the new RTC was moved to I2C bus 1. As the mainboard is not finished yet, there are no incompatibility issues with this change. Every new mainboard will have the new RTC and the older mainboards are not delivered yet. Change-Id: I3dd00855b8c9b22bdea21d3c8563cdb392868751 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07mb/siemens/mc_ehl: Move RTC Kconfig option to variant levelWerner Zeh
With a redesign of mc_ehl2 the used RTC was changed. In order to be able to select a different RTC type for every variant move the RTC Kconfig switch into the variant's Kconfig file. Change-Id: Ia24703ede6a935e3b9886df87237857baec7d6a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67100 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07drivers/i2c: Add a new RTC RV-3028-C7 from Micro CrystalWerner Zeh
This patch adds a driver for a new RTC from Micro Crystal. Supported features are: * configure backup voltage switchover via devicetree * configure backup capacitor charging mode via devicetree * set date if a voltage drop on backup voltage was detected to either a user definable (devicetree) or coreboot build date Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07mb/google/geralt: Pass reset gpio parameter to BL31Bo-Chen Chen
Pass the reset gpio parameter to BL31 to support SoC reset. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifdfbd6bd82f64b084f6349cb617443053c89a3f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67357 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07soc/mediatek: a common implementation to register BL31 resetHung-Te Lin
The implementations of register_reset_to_bl31() are the same for MedaiTek platforms, so we extract them to soc/common/bl31.c. BUG=None TEST=build pass Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-07soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxesJohnson Wang
Some of the pll settings are incorrect, which cause problems in GPU after booting into kernel. - MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix it to enable MFGPLL properly. - Switch SPMI clock muxes to 260M to avoid kernel hang while probing SPMI kernel driver. TEST=GPU bringup correctly. BUG=b:233720142 Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-09-07mb/google/corsola: Fix ANX7625 power-on T4 sequenceZanxi Chen
The T4 of ANX7625 power on sequence should be larger than 0ms, but it's -59ms now. So add 70ms delay between DSI_TE and LCM_RST. BUG=b:242352915 TEST=The sequence T4 is larger than 0ms when power on. Change-Id: I6b888707ec3c0612e396564e77c4cdbe92614dc5 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-06mb/google/skyrim/var/winterhold: Update devicetree settingEricKY Cheng
Initialize winterhold devicetree. BUG=b:241196632 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I9fe224cdc2acb1f13d3bf9341b487892c15f8ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-06src/soc/intel: remove force-included header compiler.h from fileMartin Roth
The header file `compiler.h` is automatically included in the build by the top level makefile using the command: `-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`. Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06src: remove force-included header rules.h from individual filesMartin Roth
The header file `rules.h` is automatically included in the build by the top level makefile using the command: `-include src/soc/intel/common/block/scs/early_mmc.c`. Similar to `config.h` and 'kconfig.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06mb/hp/z220_series: Add configs for integrated XHCIBill XIE
Without these, all SuperSpeed ports are wired to EHCI #2. "superspeed_capable_ports" and "xhci_switchable_ports" should fit both CMT and SFF variants, while "xhci_overcurrent_mapping" should be consistent with the first 4 elements of mainboard_usb_ports[]. With this commit, SuperSpeed devices plugged in SuperSpeed ports are wired to the XHCI on my own Z220 SFF. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06mb/google/skyrim/var/winterhold: Add gpio override settingsEricKY Cheng
Follow FT6_SOC_GPIO_PM&Strap_20220815A.XLSX update Gpio setting BUG=b:240824497 BRANCH=None Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2086c326cbf46ba6378d18d37dcbbe9fafa6b2bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-06allocator_v4: Disable top-down mode by defaultNico Huber
The top-down allocation feature was merged prematurely before platforms that don't report their resources correctly were fixed. Let's turn it off by default. Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-05Revert "allocator_v4: Treat above 4G resources more natively"Nico Huber
This reverts commit 117e436115484f0ce184114b22b716616592e77e. Depends on top-down allocation to keep the behavior to place hot-plug reservations above 4G. The latter was merged prema- turely, though. Change-Id: I5721cb84b29fc42240dff94f49a94461d88e7fbc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67329 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-05soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66706 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-05ec/google/chromeec: Modify ufp from type-c roleDtrain Hsu
In order to fix the USB port of type-C dongle has no function after reboot/shutdown, modify ufp which is in google_chromeec_usb_pd_get_info from the bit1 of type-c role (PD_CTRL_RESP_ROLE_DATA). BUG=b:239138412 TEST=Built coreboot image and verified that using this patch can detect usb drive after reboot. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I73a4a6ec37129388783599125f067068d155d93f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67168 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04mb/google/rex: Correct GPSI0 muxing for pads requiring NF8Tarun Tuli
GSPI0 pads required muxing to NF8. Support for extended native functions was added in commit b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 BUG=b:244610269 TEST=build and booted on Rex Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-09-04drivers/intel/dptf: Add multiple fan support under dptfSumeet Pawnikar
Add multiple fan support for dptf policies BUG=b:235254828 BRANCH=None TEST=Built and tested on Redrix system for two fans Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-04mb/google/brya/var/ghost: Delete variantJack Rosenthal
This project concluded and the coreboot implementation is no longer required. BUG=b:244596639 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67299 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04mb/google/dedede/var/shotzo: Update DPTF parametersTony Huang
Update DPTF parameters from internal thermal team. BUG=b:244373677 BRANCH=firmware-dedede-13606.B TEST=Build image and verified by thermal team. Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-04allocator_v4: Treat above 4G resources more nativelyNico Huber
We currently have two competing mechanisms to limit the placement of resources: 1. the explicit `.limit` field of a resource, and 2. the IORESOURCE_ABOVE_4G flag. This makes the resource allocator unnecessarily complex. Ideally, we would always reduce the `.limit` field if we want to "pin" a specific resource below 4G. However, as that's not done across the tree yet, we will use the _absence_ of the IORESOURCE_ABOVE_4G flag as a hint to implicitly lower the `limit` of a resource. In this patch, this is done inside the effective_limit() function that hides the flag from the rest of the allocator. To automatically place resources above 4G if their limit allows it, we have to allocate from top down. Hence, we disable the prompt for RESOURCE_ALLOCATION_TOP_DOWN if resources above 4G are requested. One implication of the changes is that we act differently when a cold-plugged device reports a prefetchable resource with 32-bit limit. Before this change, we would fail to allocate the resource. After this change, it forces everything on the same root port below the 4G line. A possible solution to get completely rid of the IORESOURCE_ABOVE_4G flag would be rules to place resources of certain devices below 4G. For instance, the primary VGA device and storage and HID devices could be made available to a payload that can only address 32 bits. For now, effective_limit() provides us enough abstraction as if the `limit` would be the only variable to consider. With this, we get rid of all the special handling of above 4G resources during phase 2 of the allocator. Which saves us about 20% of the code :D Change-Id: I4c7fcd1f5146f6cc287bd3aa5582da55bc5d6955 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65413 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04pciexp_device: Propagate above-4G flag to all hotplug devicesNico Huber
The `IORESOURCE_ABOVE_4G` flag was only explicitly set for our dummy device that reserves resources behind a hotplug port. The current re- source allocator implicitly extends this to all devices below the port, including real ones. Let's make that explicit, so future changes to the allocator can't break this rule. Change-Id: Id4c90b60682cf5c8949cde25362d286625b3e953 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66719 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-04allocator_v4: Introduce RESOURCE_ALLOCATION_TOP_DOWNNico Huber
Add option to resource allocator v4 that restores the top-down allocation approach at the domain level. This makes it easier to handle 64-bit resources natively. With the top-down approach, resources that can be placed either above or below 4G would be placed above, to save precious space below the 4G boundary. Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-04mb/prodrive/hermes: Use snake case for identifiersAngel Pons
There's no reason to use camel case for EEPROM region names or local variables. Use snake case for consistency with coreboot's code style. Change-Id: Id1200a0c778095b109d824a1ca4e3e69591e4165 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-04vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00Saurabh Mishra
Update generated FSP headers for Alder Lake N from v3267.01 to v3301.00. Changes include: - FspsUpd.h: 1. Add VccInAuxImonSlope UPD 2. Update UPD Offset in FspsUpd.h BUG=b:242152105 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-04device/i2c_bus: Add routines to read and write multiple bytesWerner Zeh
Some devices require that several bytes are written with a single I2C write command. Extend the i2c_bus interface functions and add both, read and write for more than one byte at a defined byte offset. Change-Id: I0eec2e1d4185170f02b4ab35aa6546dc69569303 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67098 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-04security/vboot/tpm: Avoid duplicate vb2api_secdata_firmware_create callsYu-Ping Wu
For TPM2, vb2api_secdata_firmware_create() is already called from setup_firmware_space() from _factory_initialize_tpm(). Therefore move the duplicate call from factory_initialize_tpm() to TPM1's _factory_initialize_tpm(). Change-Id: I892df65c847e1aeeabef8a7578bec743b639a127 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-03soc/intel: Add SI_DESC region to GSCVD rangesJulius Werner
Intel platforms have soft straps stored in the SI_DESC FMAP section which can alter boot behavior and may open up a security risk if they can be modified by an attacker. This patch adds the SI_DESC region to the list of ranges covered by GSC verification (CONFIG_VBOOT_GSCVD). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0f1b297e207d3c6152bf99ec5a5b0983f01b2d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02cbfs/vboot: Adapt to new vb2_digest APIJulius Werner
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02amdblocks/alib.h: Add DPTC parameter IDsTim Van Patten
Add additional DPTC parameter IDs that are necessary when throttling the SOC due to low/no battery. These additional parameters are used in later CLs. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I9e944d7c620414ec92d08a3d1173ba281d593ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67182 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-02mb/google/skyrim: Remove elog_gsmi_cb_mainboard_log_wake_sourceRaul E Rangel
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes eSPI transactions. If the SMI interrupts an ongoing eSPI transaction from the OS it will conflict and cause failures. Removing this call to avoid conflicts. This can be re-enabled after refactoring google_chromeec_get_mask to use ACPI MMIO. This is a copy of CB:63280 but for skyrim. BUG=b:227163985, b:243557044 TEST=suspend/resume skyrim and no longer see EC wake sources in elog. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iac56840fe15101bc556d8cce9960f761c6ea7181 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-09-02mb/google/rex: Enable DSP UPDEric Lai
Enable DSP setting. Make sure the SSP can work as expected. BUG=b:243123156 TEST=Dev beep working on Rex. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I6ae28e414ac4ac33f596df57691c979eac5fe132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67270 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-02soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enablingSubrata Banik
Enabling Bus Master isn't required by the hardware, so we shouldn't need to enable it at all. However, some payloads do not set this bit before attempting DMA transfers, which results in functionality failure. For example: in this case, unable to see the developer screen in Depthcharge. In the prior IA SoC platform, FSP/GFX PEIM does the BM enabling for the IGD BAR resources but starting with the MTL platform, it fails to do so resulting into inability to see the Pre-OS display. BUG=b:243919230 ([Rex] Unable to see Pre-OS display although GFX PEIM Display Init is successful during AP boot) TEST=Able to see the developer screen with eDP/HDMI while booting the Google/Rex. Also, this change doesn't impact the previous platforms (ADL, TGL, CML etc.) where the BM is default enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-01mb/google/guybrush: select SYSTEM_TYPE_LAPTOPMatt DeVillier
Select SYSTEM_TYPE_LAPTOP so the FADT PM profile is correctly set to mobile (vs the default of desktop). TEST=build/boot google/dewatt, run FWTS and verify FADT PM profile correct Change-Id: I480fbe85782e2c63efa8d2212d503a47d8149ab9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-01mb/google/skyrim: Add missing USB ports to device treeRaul E Rangel
As part of investigating b/240690391 I noticed that we were missing the daughter board ports. Not all SKUs have these ports connected, but it doesn't hurt to have the extra ACPI nodes. BUG=none TEST=build Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id6fc34acbfa30bc15e697043bf93bcf584256128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-09-01drivers/elog/gsmi.c: Fix compiling for 64bitArthur Heymans
Change-Id: Ic8e04ae043145a3633c0b8379a797724f95fd7ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-01amd/*/Makefile.inc: Put common words into common Makefile.incZheng Bao
Definition of FIRMWARE_LOCATION, POUND_SIGN, DEP_FILES, amd_microcode_bins are moved to common Makefile.inc. Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62658 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-09-01vendorcode/intel/fsp2/glk: Add the FSP headers for version 2.2.3.1Sean Rhodes
Add the headers for 2.2.3.1, which includes the following changes over 2.2.0.0: • [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry failure in less than 5 cycles when a USB2 Ethernet Dongle is connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter 7.20.6 for new Register settings. • [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini Lake/Gemini Lake – R • [Update] MRC new version update to 1.38. • [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from S4 issue with latest Wifi driver. [Update] MRC new version update to 1.39. Included fix for MinRefRate2xEnable and support for Rowhammer mitigation. • [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This change specific to DDR4 memory configuration. • GLK Klocwork Fix • [Update] MRC new version update to 1.40. Added in a separate directory as the default. The 2.2.0.0 headers were left and will be used for Google boards, as some offsets have moved. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-01mb/google/brya/acpi: Save/restore/clear some registers over GC6Tim Wawrzynczak
Nvidia recommends saving and restoring the LTR Enable bit in PCIe config space for the PCIe root port before/after GC6 entry. Also the detectable error bit should be cleared, as there may be errors expected during the GC6 flow. BUG=b:214581763 TEST=no more correctable errors after GC6 entry/exit Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-01mb/google/nissa: Mark PCIe wifi device as untrustedReka Norman
BUG=b:238937091 TEST=Dump SSDT on nereid and check that the wifi device contains the DmaProperty. Also check that the kernel marks the device as untrusted. Change-Id: I0725ea18d52420a3161d6fcfa3bcb72ebe35f3a5 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-31soc/amd/mendocino/Kconfig: select extended eSPI decode range supportFelix Held
Select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES and remove the TODO from SOC_AMD_COMMON_BLOCK_HAS_ESPI. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90e3bf3f196e22b428b01ea0437c1224702d2b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-31acpi: Replace EC_ENABLE_AMD_DPTC_SUPPORT with Kconfig valueTim Van Patten
Compile-time support of DPTC is controlled by EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. Each variant's run-time support of DPTC continues to be controlled by the variant's overridetree.cb "dptc_enable" value. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-31soc/intel/alderlake: Add new pcie5 alias for raptorlakeBora Guvendik
Pcie5_1 is added for DID 0xA72Dh and BDF 0/1/1. References: RaptorLake External Design Specification Volume 1 (640555) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Id7440bf202d5560ff92807877d48b94054cb1de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-31mb/amd/chausie/Kconfig: Re-enable ESPI_RETAIN_PORT80Fred Reitberger
Chausie fails to boot without this option set. Enable in the mainboard rather than the SoC Kconfig to not impact Skyrim. TEST=boot to OS Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9f2a1be9eddb9e17407d00ff50ceb70a2718ce3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-31soc/mediatek/mt8188: Add SPM loader and initialize SPM in RAM stageRex-BC Chen
Add support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. SPM is an essential component on MediaTek SoC, so we initialize PPM in soc_init(). For MT8188, SPM will handshake with DPM to do initialization, so we need to call spm_init() after dpm_init(). This SPM flow adds 33ms to the boot time. firmware log: mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 25 msecs SPM: spm_init done in 33 msecs, spm pc = 0x400 TEST=spm pc is 0x400 which is in idle state. BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I1a1f49383e0ceadc259a18272fc1c277b65406ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/66973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 23:18:31 +0000