diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-09-08 13:15:37 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-09-10 19:00:49 +0000 |
| commit | 8b518776dacc929b52f5d2f89cc36c8eef361daa (patch) | |
| tree | 2f63825bd656f5ba0471421f6b209defc1488aa7 /src | |
| parent | f5afc1a5a2a04c6961b0f86d2b47c801c222f065 (diff) | |
soc/intel/meteorlake: Update `pch_thermal_trip` for MTL
This patch updates `pch_thermal_trip` as per Intel MTL vol1
chapter 14.
Additionally, dropped the `FIXME` tag for `pch_thermal_trip`.
TEST=Able to boot the Google/rex to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/chipset.cb | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 4784e3b38c..af9049076b 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -16,8 +16,7 @@ chip soc/intel/meteorlake # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. - #FIXME: update value for MTL - register "common_soc_config.pch_thermal_trip" = "100" + register "common_soc_config.pch_thermal_trip" = "130" device domain 0 on device pci 00.0 alias system_agent on end |