diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-23 01:06:21 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-12 12:23:19 +0000 |
| commit | ff7725e74281a4ae9c776525891d45233599bce4 (patch) | |
| tree | 0696830d2a497db5b4657d858c5b913542b9b9e2 /src | |
| parent | 042ba16ef8a269932e996e13f85b0767c53c8a19 (diff) | |
drivers/intel/ptt: Use the correct detection method
On some platforms the HFSTS4 bit 19 does not indicate active PTT.
Instead of ME HFSTS4, use TXT FTIF register to check active TPM for
the current boot. Discrete TPM shall be deactivated when PTT is
enabled so this always should return true value of PTT state.
Leave the old method for backwards compatibility if TXT FTIF would not
be applicable for older microarchitectures.
Based on DOC #560297.
TEST=Check if PTT is detected as active on MSI PRO Z690-A DDR4 WIFI
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3a55c9f38f5bb94fb1186592446a28e675c1207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/intel/ptt/ptt.c | 12 | ||||
| -rw-r--r-- | src/security/intel/txt/txt_register.h | 5 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/drivers/intel/ptt/ptt.c b/src/drivers/intel/ptt/ptt.c index 67ed0eebb7..5b0918bada 100644 --- a/src/drivers/intel/ptt/ptt.c +++ b/src/drivers/intel/ptt/ptt.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/mmio.h> #include <soc/pci_devs.h> #include <device/pci_ops.h> #include <console/console.h> +#include <security/intel/txt/txt_register.h> +#include <stdint.h> #include "ptt.h" @@ -27,6 +30,7 @@ static uint32_t read_register(int reg_addr) */ bool ptt_active(void) { + uint32_t sts_ftif; uint32_t fwsts4 = read_register(PCI_ME_HFSTS4); if (fwsts4 == 0xFFFFFFFF) @@ -34,6 +38,14 @@ bool ptt_active(void) if ((fwsts4 & PTT_ENABLE) == 0) { printk(BIOS_DEBUG, "Intel ME Establishment bit not valid.\n"); + sts_ftif = read32p(TXT_STS_FTIF); + + if (sts_ftif != 0 && sts_ftif != UINT32_MAX) { + if ((sts_ftif & TXT_PTT_PRESENT) == TXT_PTT_PRESENT) { + printk(BIOS_DEBUG, "TXT_STS_FTIF: PTT present and active\n"); + return true; + } + } return false; } diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index 2137715edb..95f2a680d9 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -95,6 +95,11 @@ #define TXT_ACM_KEY_HASH (TXT_BASE + 0x400) #define TXT_ACM_KEY_HASH_LEN 0x4 +#define TXT_STS_FTIF (TXT_BASE + 0x800) +#define TXT_LPC_TPM_PRESENT 0x10000 /* Location of TPM: 001b - LPC TPM */ +#define TXT_SPI_TPM_PRESENT 0x50000 /* Location of TPM: 101b - SPI TPM */ +#define TXT_PTT_PRESENT 0x70000 /* Location of TPM: 111b - PTT present and active */ + #define TXT_E2STS (TXT_BASE + 0x8f0) #define TXT_E2STS_SECRET_STS (1ull << 1) |