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2022-08-26soc/intel/p2sb: Refactor `p2sb_execute_sideband_access` functionSubrata Banik
This patch refactors p2sb_execute_sideband_access() to be able to handle SBI operations in both SMM and non-SMM scenarios. Prior to FSP-S operation being done, the IOE P2SB device will be visible on the PCI bus hence, performing the SBI operation using IOE P2SB doesn't involve unhide/hide operation. Post FSP-S, the IOE P2SB device is hidden. Additionally, SBI operations can't be performed as is. The only possible way to send SBI is inside SMM mode and to do that, coreboot needs to unhide the P2SB device prior to sending the SBI and hide it post sending SBI. As a result, the p2sb_execute_sideband_access() function has been refactored to manage these cases seamlessly without users of the p2sb_execute_sideband_access() actually being bothered about the calling mode. BUG=b:239806774 TEST=Able to perform p2sb_execute_sideband_access() function call in both SMM and non-SMM mode without any hang/die. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/amd: rework SPI flash MMIO region handlingFelix Held
Only 16 MByte of the SPI flash can be mapped right below the 4 GB boundary. In case of a larger SPI flash size, still only the 16 MByte region starting at 0xff000000 can be configured as WRPROT and be reserved for the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting at address 0xfe000000 contain for example the LAPIC MMIO region, the ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't be configured as WRPROT. Reserving this region for the MMIO mapped SPI flash would also result in an overlap with the MMIO resources mentioned above. In the case of a smaller SPI flash, reserving the full 16 MByte flash MMIO region makes sure that the resource allocator won't try to put anything else in the lower parts of the 16 MByte SPI mapping region. To avoid the issues described above, always reserve/cache the maximum amount of 16 MBytes of flash that can be mapped below 4 GB. TEST=On boards with 16 MByte SPI flash chips, the resulting image of a timeless build doesn't change with this patch. Verified this on Chausie (Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena (Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the resulting image of a timeless build is different, but neither the coreboot console output nor the Linux dmesg output shows any errors that might be related to this change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25mb/google/brya/variants/crota: fine tune WWAN power sequencingTerry Chen
Because the poweron state of some of the WWAN GPIOs is the asserted state, this patch fixes the poweron sequence so that the WWAN module is always correctly powered on, in both cold and warm reboot scenarios. BUG=b:233564770 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I4ec8312c30392b9ca0a3e0321cb4578e76ec5787 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-25mb/google/rex: Update DQS for RexTarun Tuli
Update the DQS for Rex as per the latest Rex schematics (08/25). BUG=b:243734885 TEST=Built successfully. Confirmed on HW. Change-Id: I2a458a3da725f953cbba8a194ac6f314f5467419 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67041 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up Lp5CccConfig FSP UPDKapil Porwal
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up ECT FSP UPDKapil Porwal
Hook up ECT FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Program MCHBASE prior enabling extended bios rangeSubrata Banik
This patch resolves the SoC programming dependency order where enabling extended bios support requires MCHBASE to be enabled. BUG=b:243693375 TEST=Able to boot from RW-A slot which is mapped to extended BIOS range. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25mb/google/rex: Configure GSC INT GPIO early in the bootKapil Porwal
This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early GPIO tables. BUG=b:243641061 TEST=Able to build rex image. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-25soc/amd/common/fsp/dmi: Set dimm voltage based on memory typeMatt DeVillier
Voltage set based on standard configuration for each type. TEST=build/boot google/skyrim, verify output in cbmem console log, DMI type 17 table. Change-Id: I9b1e68a9417e43cbb9c55b4c471664f3f9090342 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66981 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25soc/amd/common/fsp/dmi: Print MT/s speeds, not frequency in debug outputMatt DeVillier
Since the frequency field is deprecated, print the max/configured MT/s speeds instead. TEST=build/boot google/skyrim, verify output in cbmem console log Change-Id: Icee5af762ca37c3b2ec8c9a52a7f32fb848390b0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66980 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25soc/amd/common/fsp/dmi: Translate DRAM speeds for (LP)DDR5Matt DeVillier
Hook up newly-added method to convert from frequency to MT/s so that boards which use (LP)DDR5 report their capability properly. BUG=b:239000826 TEST=build/boot google/skyrim, verify SMBIOS Type 17 table reports DRAM speeds correctly. Change-Id: I694b6c227a8d8fb40c897053808bc79df330ed0c Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66954 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25device/dram: Add function to convert freq to MT/s for (LP)DDR5Matt DeVillier
As the frequency field in the SMBIOS type 17 table is deprecated, we need to provide the maximum and configured speed in MT/s. Add a method to convert from frequency to MT/s using a lookup table. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I0402b33a667f7d72918365a6a79b13c5b1719c0d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-24mb/google/skyrim: Create morthal variantMoises
Create the morthal variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_MORTHAL Signed-off-by: Moises <moisesgarcia@google.com> Change-Id: I25c25f067a040e6930f4fc60fadb8be85dc8eda6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24mb/google/skyrim: Check if SPD existsIsaac Lee
Update the build script to check if SPD exists, and only if SPD exists the APCB_SBR_D5.gen could be executed. BUG=None TEST=Build Change-Id: Ib7b977a89d403242e8bb1f684269e70082125e88 Signed-off-by: Isaac Lee <isaaclee@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66978 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24soc/intel/common/block: Drop empty smm.hAngel Pons
This file has nothing useful. Get rid of it. Change-Id: Id2a42005d3b4b5161079c9ff48867cfc6fb0413d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-24mb/google/brya/var/agah: Reenable ASPM L1 substatesTim Wawrzynczak
Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates can be enabled and appear functional. BUG=b:240390998 TEST=lspci reports them as functional, MODS does not hang Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/brya/var/agah: Update GPU GPIOsTim Wawrzynczak
Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal explicitly, as the hardware engineers requested this. BUG=none TEST=boot and reboot agah, dGPU still visible on PCIe bus Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/brya/var/agah: Enable DPTF oem_variablesTony Huang
Support oem_variables and change based on EC notify event. BUG=b:238921409 TEST=emerge-draco coreboot 1. check ACPI object ODVX has oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } 2. check can get EC oem variable change notify in the kernel log Change-Id: Ibd856563a43d73a3b1be09b3fbebca1b36b5eab1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66575 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24ec/google/chromeec/acpi: Add support for DPTF oem variable event notifyTony Huang
The agah EC code will monitor adapter current to choose corresponding DPTF oem variable table. When it changes, this event will send to the ACPI FW through host event and then pass onto the DPTF kernel driver. This patch adds support for that feature. BUG=b:238921409 TEST=add Printf() calls to the ACPI, and check these Printf() will show up in the kernel log when EC send oem variable table change notify. Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/adl: Consider INTEL_TME config prior TME MSR programmingSubrata Banik
This patch brings INTEL_TME config check prior programming TME Set Activation Core MSR on all cores. TEST=Able to boot Google/Taeko to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8af7e305da1050f443929ab33be556e713e53e9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66976 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/starlabs/lite: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c12161d4868deae5b8900cfa2f42517a9f0b7e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24drivers: Implement EFI_PEI_MP_SERVICES_PPI with FSP_UNSUPPORTED typeSubrata Banik
This patch implements EFI_PEI_MP_SERVICES_PPI structure definitions with APIs that return mp_api_unsupported(). The reason behind this change is to fix an FSP issue where FSP assumes ownership of the APs (Application Processors) upon passing a `NULL` pointer to the CpuMpPpi FSP-S UPD.Hence, this patch implements `MP_SERVICES_PPI_DEFAULT` config to fill EFI_PEI_MP_SERVICES_PPI with `mp_api_unsupported` APIs. Later this data structure can be passed to the CpuMpPpi UPD to avoid APs from getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. TEST=Able to build and boot Google/Taeko with this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I31fcaa2aa633071b6d6bfa05dbe891ef87978d2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24soc/intel/alderlake/hsphy: Add support for HSPHY firmware loadingMichał Żygowski
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on public Slimbootloader's "Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib". TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded. PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot. [DEBUG] HECI: Sending Get IP firmware command [DEBUG] HECI: Get IP firmware success. Response: [DEBUG] Payload size = 0x6944 [DEBUG] Hash type used for signing payload = 0x3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-08-24soc/intel/meteorlake: Enable GPIO 4 bits pad mode configurationJamie Ryu
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits GPIO pad mode to configure native function 8 to 15. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-24soc/intel/common/gpio: Support 4 bits GPIO pad mode configurationJamie Ryu
Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins that native function 8 to 15 is assigned. This adds native function definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support 4 bits pad mode configuration. Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not assigned, this change would not cause an issue but Kconfig option is added to minimize an impact and support 4 bits pad mode configuration. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24mb/google/rex: add arbitrage gpio.c headerKevin Chowski
This comment header is necessary for supporting propagation of overrides to variants. Change-Id: Iee92fa4fbc4851c7032401cff99ea49f87717c7f Signed-off-by: Kevin Chowski <chowski@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24src/arch/x86/smbios.c: remove unneeded bracesFabio Aiuto
fix the following checkpatch errors: WARNING:BRACES: braces {} are not necessary for any arm of this statement 354: FILE: src/arch/x86/smbios.c:354: + if (CONFIG_ROM_SIZE >= 1 * GiB) { [...] + } else { [...] WARNING:BRACES: braces {} are not necessary for single statement blocks 561: FILE: src/arch/x86/smbios.c:561: + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I14c29e4358cad4cd5ef169ebab7079db2129d8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-24vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPEMatt DeVillier
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h. Add/correct values for DDR5, LPDDR5, LPDDR5X. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-24drivers/spi/tpm: Add Ti50 entry to dev_mapYidi Lin
BUG=none TEST=See "[INFO ] Initialized TPM device TI50 revision 83" Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I3af5f4653b6b8ecd086f85ec573530a4e5c57211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-23mb/**/hda_verb.c: Drop empty filesAngel Pons
These files are no longer required by the build system. Change-Id: I327e7c9211f46d4694591abab11cb38c9180bddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-23{sb,soc}/intel: Do not require hda_verb.cAngel Pons
Just use the conditional inclusion through `device/Makefile.inc`. Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-23drivers/siemens/nc_fpga: Fix typo in commentAngel Pons
earyl ---> early Change-Id: I06412fd9487aaa1115fdbd86ff44b34db97d97d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-08-22brya: add new skolas variantNick Vaccaro
Add a new skolas variant, which is a variant of brya's skolas baseboard. BUG=b:242869976 BRANCH=firmware-brya-14505.B TEST=none Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-22soc/intel/alderlake: Perform TME core activation on all CPUsSubrata Banik
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per Alder Lake Processor EDS. TEST= Able to build and boot Google/Redrix. Dumping MSR 0x9FF on all logical processors shows zero value being set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I130480d4fba413d47d0d0137932ec1fb041a88d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66753 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22soc/intel/cmn/cpu: API to set TME core activationSubrata Banik
This patch implements API to program TME core activation MSR 0x9FF. Write zero to TME core activate MSR will translate the TME_ACTIVATE[MK_TME_KEYID_BITS] value into PMH mask register. Note: TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35] TEST=Able to build and boot Google/Redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48cf8e255b294828ac683ab96eb61ad86578e852 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-22Add SBOM (Software Bill of Materials) GenerationMaximilian Brune
Firmware is typically delivered as one large binary image that gets flashed. Since this final image consists of binaries and data from a vast number of different people and companies, it's hard to determine what all the small parts included in it are. The goal of the software bill of materials (SBOM) is to take a firmware image and make it easy to find out what it consists of and where those pieces came from. Basically, this answers the question, who supplied the code that's running on my system right now? For example, buyers of a system can use an SBOM to perform an automated vulnerability check or license analysis, both of which can be used to evaluate risk in a product. Furthermore, one can quickly check to see if the firmware is subject to a new vulnerability included in one of the software parts (with the specified version) of the firmware. Further reference: https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/ - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode, amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM, intel ME and compiler (gcc,clang,other) - Add Kconfig entries to optionally supply a path to CoSWID tags instead of using the default CoSWID tags - Add CBFS entry called SBOM to each build via Makefile.inc - Add goswid utility tool to generate SBOM data Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-21soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik
This patch removes the static kconfig being used to fill in TME enable FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check if the CPU has required TME support rather than hardcoding. TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the TME-supported CPU SKUs. As per FSP-M debug log: Without this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x1 With this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21tpm: Correct TI50_FIRMWARE_VERSION_NOT_SUPPORTED help textYu-Ping Wu
Reading firmware_version register is supported on Ti50 version 0.22.4. Therefore correct the help text of the Kconfig option TI50_FIRMWARE_VERSION_NOT_SUPPORTED. Also change the message level to BIOS_WARNING. BUG=b:234533588 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I66a0ef896c9dc4cd0f586555a55dbcd1cfd863f9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66906 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Pronin <apronin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-08-21mg/google/corsola: Disable TI50_FIRMWARE_VERSION_NOT_SUPPORTEDYu-Ping Wu
Reading Ti50 version is now supported on Ti50 version 0.22.4. Therefore stop selecting TI50_FIRMWARE_VERSION_NOT_SUPPORTED for corsola. BUG=b:234533588 TEST=emerge-corsola coreboot TEST=cbmem -1 | grep 'Firmware version' BRANCH=none Change-Id: Id8d849eaf99542363c64e27411549eb6dddfd059 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66905 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Pronin <apronin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-08-21mb/google/rex: Reshuffle CHROMEEC_* related configsEran Mitrani
1. Moved CHROMEEC_* to common (required for all boards) 2. added missing EC_GOOGLE_CHROMEEC_SKUID TEST=Verified with simics on RVP Change-Id: I26a01e5d1c78d4cd83b1aa53e68b2c3059da6061 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66762 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel/common/block/cpu: API to check if TME is supportedSubrata Banik
As per the Alder Lake FAS coreboot shall detect the existence of TME feature by running the CPUID instruction: CPUID leaf 7/sub-leaf 0 Return Value in ECX [bit 13]=1 If TME is supported then only access to TME MSRs are allowed otherwise accessing those MSRs would result in GP#. TEST=Able to detect the existence of TME feature across different Alder Lake and Meteor Lake CPU SKUs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd4fcf15a66d27748ac7fbb52b18d7264b901cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66749 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21Revert "mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants"V Sowmya
This reverts commit 2b19d547c0866fef84bdb7b226ce7a4ac81af64f. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BUG=b:240669428 TEST=verify that EPP is back to the by default 50% setting `iotools rdmsr 0 0x774' Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Usha P <usha.p@intel.com>
2022-08-21mb/google/brask/variants/moli: Support DPTF oem_variablesRaihow Shi
Enable DPTF oem_variables and override based on CPU match id. BUG=b:236294162 TEST=emerge-brask coreboot and check the value in odvp0 is correct. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21mb/google/nissa/var/pujjo: Add FW_CONFIG probe for Pujjoteen disableLeo Chou
bypass power Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen and others(Pujjo and Pujjoflex) BUG=b:242663554 TEST=Boot to OS and verify that ext_fivr_settings are set based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21mb/google/dedede/var/shotzo: Enable ILITEK touchscreenTony Huang
The current reset delay is not enough to make touchscreen IC ready, ILITEK feedback their requiremt is 400ms in spec T2. After changing the reset_delay_ms and check touchscreen works, ILITE also change the IRO to low level trigger. This CL is to reflect that. BUG=b:235929123 BRANCH=firmware-dedede-13606.B TEST=check touchscreen function work Change-Id: I126b2d74c1d7a1799e2f67a8ab01cba074447c06 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-08-21mb/google/nissa/var/yaviks: Update GPIO settingWisley Chen
Configure GPIOs according to schematics. BUG=b:242277219 TEST=emerge-nissa coreboot Change-Id: Id7412059ba98d58f7014ab7201ea8958ede5905e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21mb/google/nissa/var/yaviks: Update devicetree settingWisley Chen
Update Devicetree according to yaviks's design. BUG=b:242277219 TEST=emerge-nissa coreboot Change-Id: I5d91cccbb44787bcbe7258a817ff97b6dce86c2e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-21intel/systemagent: Align debug outputNico Huber
Output should be easier to read as a table. Change-Id: I32e3e0aab5afd25c0b004d18f64de76445d9a0ed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-21mb/starlabs/*: Disable INTEL_LPSS_UART_FOR_CONSOLESean Rhodes
Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2. This decreases boot time on all boards by around 60%. TGL before: Total Time: 10,110,807 TGL after: Total Time: 3,851,641 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21mb/starlabs/starbook/kbl: Update verb tableSean Rhodes
The ALC269 does not support the hardware equaliser, so remove the entries related to this, as they have no effect. Revert to the ALC269 defaults which work correctly with Linux. This also corrects the subsystem id from 0x10ec111e to 0x10ec10d0. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I82647f67730ec344591f7dbd759a421c116d4fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-20mb/google/skyrim: Add ELAN touchscreenAmanda Huang
Add ELAN touch support BUG=b:243120074 TEST=emerge coreboot and check ELAN touch screen is workable Change-Id: If30232b3da9af0015d6d87535b53f905c5a30bcb Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66912 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Isaac Lee <isaaclee@google.com>
2022-08-20soc/amd/common/block/psp/psb: add missing amdblocks/smn.h includeFelix Held
smn_read32 is used in this file, so include the header file with the function prototype so that the file compiles successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5bef96cd08f22b3475e8b5ba4e984a6e1ab4da36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-20soc/amd/stoneyridge: move early I2C init to early_fch.cFelix Held
Since the I2C controller is part of the FCH, move the early initialization from bootblock.c to early_fch.c which also matches what the newer AMD SoCs do. TEST=Successfully boots on google/liara and all I2C/cr50/TPM functions appear to work properly Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22d3a8888eaa34ea612da719c408c0083769e806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66866 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-20soc/amd/stoneyridge/early_fch: use common lpc_early_init functionFelix Held
The functionality of sb_enable_lpc is implemented in the common LPC support code as lpc_enable_controller. This gets called by the common lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase. The lpc_set_spibase call was already done in bootblock_fch_early_init, so the main change in code behavior is that now lpc_disable_decodes gets called during early FCH initialization. The lpc_enable_port80 and sb_lpc_decode calls after the lpc_early_init code will reenable some of the decodes. TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-20soc/amd/common/dmi: Add missing newline in printkMatt DeVillier
Change-Id: I35dd9a2f0520077913bd3d8f408206dea1b30acb Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66867 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-20soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI configKyösti Mälkki
The PCI config space of the SMBus device has a secondary mapping as an ACPIMMIO bank. Since the PCI device is on bus 0, it's already available early in boot after the enable_pci_mmconf call, so there's no need to use the ACPIMMIO mapping instead of the PCI config space mapping. Verstage on PSP could theoretically access the PCI config space via the 0xcf8/0xcfc register pair, but since verstage on PSP doesn't have the ACPIMMIO mapping anyway, we won't loose any functionality here. Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-19mb/starlabs/lite/glkr: Remove old comment from devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib203451bb3da06efd1d3f6e48496b370d81f4b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66196 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/starlabs/lite: Use chipset.cb aliasesSean Rhodes
GLKs chipset configures the devices, so use these aliases and remove the entries when they are identical. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic29e5305346c3b7fbf66b027754a9ddd16b16269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66195 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/google/nissa/var/pujjo: Add DPTF setting for pujjoLeo Chou
DPTF Policy and temperature sensor values from thermal team. BUG=b:242797681 TEST=build FW and boot to OS. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Id4365f87843a4408ae457e7ef27291fdaa0d5bde Reviewed-on: https://review.coreboot.org/c/coreboot/+/66827 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/intel/adlnrvp: Skip sending the MBP HOB to save boot timeV Sowmya
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40msec on ADL-N. Boot time data: Before: * 955:returning from FspSiliconInit 956,832 (110,268) After: * 955:returning from FspSiliconInit 944,528 (74,213) BUG=b:241850107 TEST=Verified that boot time is reduced by ~40msec and also S0i3 is working. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I05d226fb5f05463341358cd20655f06376778bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/66676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-19mb/google/nissa: Skip sending the MBP HOB to save boot timeV Sowmya
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40msec on ADL-N variants. Boot time data: Before: * 955:returning from FspSiliconInit 1,231,364 (117,051) After: * 955:returning from FspSiliconInit 1,198,221 (79,497) BUG=b:241850107 TEST=Verified that boot time is reduced by ~40msec and also S0i3 is working. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iaeaa8bcdf8467fdd467a10a98dd7582e8e0b067c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-19soc/intel/alderlake: Add support to skip the MBP HOBV Sowmya
This patch adds the support to enable/disable skipping MBP HOB from the devicetree based on mainboard requirement. Only ADL-N FSP has the required support to skip the MBP HOB and enabling it is saving the Boot time. BUG=b:241850107 TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iddeb2c652fac9513b14139d6f732d333bbb989d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-19mb/google/nissa: Remove runtime descriptor updates and VBT selectionSam McNally
The infrastructure for selecting an appropriate firmware image to use the right descriptor is now ready so runtime descriptor updates are no longer necessary. Since the different descriptor builds split along HDMI/USB-C lines for nereid, a single VBT file can be used for each, removing the need for runtime VBT selection as well. BUG=b:229022567 TEST=Nereid type-C and HDMI outputs work as expected Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: Idf1fbd6c26203adbda002dec3f11e54a7b9f9b82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-19mb/system76/gaze16: Move stray header to include folderTim Crawford
Change-Id: Id3367a708744d6a3ed0ba69ed8e0cafe0a5934b6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-19mb/system76/gaze16: Configure GPIOs in mainboard_init()Tim Crawford
Configure GPIOs in `mainboard_init()` instead of during FSP config. Change-Id: Icc40ce71d2bd104c5f41e992f9b28824a3b734d6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66169 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/system76/gaze16: Split gpio.h into data filesTim Crawford
Split `gpio.h` into `gpio_early.c` for bootblock and `gpio.c` for ramstage to match other System76 boards. Change-Id: I24398ad459754ac80d92d70687ab70b22894a01c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-18mb/google/trogdor: remove variant "pazquel360"Chao Gui
This reverts commit feb551a92550fcc28b32aca77117aa743018b233. Adding new variant "pazquel360" is not needed. BUG=b:239599467 TEST=emerge-trogdor coreboot Signed-off-by: chaogui@google.com BRANCH=none Change-Id: I4878d3a54f96fb9d38f2da1a1c918dfdef80a301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66805 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18mb/google/brya/var/crota: update DPTF setting in CrotaJohnny Li
DPTF Policy and temperature sensor values update from thermal team. BUG=b:237640264 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I45b4f80cbec0723c63ac7fc7176e13ae5a2b54c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66365 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18soc/intel/tigerlake/fsp_params.c: Add INT D routing for PEG60Frans Hendriks
Debian 11 reports ´0:6:0 can´t derive routing for PCI INT D´. Use FIXED_INT_PIRQ for INT D to PIRQ routing table. BUG=NA TEST=Boot Debian 11 on Siemens AS_TGL1 and verify no PIRQ error message in ´dmesg´ Change-Id: If38c7b6f664e0f6533e583ce62504281a4092720 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-18mb/google/brya/acpi: Add PCIe SRCCLK# control to RTD3 methodsTim Wawrzynczak
This patch adds support for turning the PCIe SRCCLK# on and off during RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver). TEST=GC6 and GCOFF sequences still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-18mb/google/brya/var/agah: Update NVVDD VR PGOOD GPIOTim Wawrzynczak
For board revs 3 and later, the PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that this code will write the correct GPIO # to depending on the board rev, and we'll use that instead. BUG=b:239721380 TEST=still works on board rev 2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-18soc/mediatek/mt8186: spm: Remove redundant callYidi Lin
spm_set_power_control() is already called in spm_init(). It is not necessary to call spm_set_power_control() again in the mtk_mcu reset callback. TEST=check SPM PC value (0x250) after SPM is loaded. [INFO ] SPM: spm_init done in 54 msecs, spm pc = 0x250 Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I7ee517e1eb6485c52155a69d05781a61ddfe4cad Reviewed-on: https://review.coreboot.org/c/coreboot/+/66785 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18mb/google/brya/var/pujjo: Modify GPIO for SD_WAKE_NLeo Chou
Modify GPP_D17 setting for SD_WAKE_N. BUG=b:242647845 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Iacd89d27174869e34c48d1f62793ddc45b43f3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-18ec/google: Notify DPTF driver power participant on PD eventVarshit B Pandya
The DPTF power participant device needs to be notified when power source changes so it can re-evaluate power source and power source change count, this can be later used by DPTF along with methods provided by EC. Corresponding changes in EC are https://crrev.com/c/3545778 and https://crrev.com/c/3547317 BUG=b:205928013 TEST=Build, boot brya0 and dump DSDT to check change Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-18soc/amd/mendocino: enable CPPC featureFelix Held
This is sort-of reverts commit cbf290c692b2 ("soc/amd/sabrina: drop CPPC code"), since it turned out that the CPPC feature is supported on Sabrina (now Mendocino) despite this being missing from the documentation I looked at when writing the patch referenced above. Since the CPPC ACPI code generation functionality has been moved to common code, this isn't a direct revert. BUG=b:237336330 TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-18mb/google/rex: Create 64MB AP Firmware binary for Proto 0Subrata Banik
This patch provides a mitigation path for having different size SPINOR parts across Rex board revisions. Rex Proto 0 only has 64MB SPINOR mounted on the board, and the plan is to use 32MB later with Proto 1 onwards. Hence, the idea here is to maintain a 32MB SPI Flash layout across all Rex board revisions, but the Proto 0 build only selects BOARD_ROMSIZE_KB_65536 config for adding padding at the end of the 32MB range. BUG=b:242825380 TEST=Able to create 64MB AP Firmware for Rex with below layout: SI_ALL: 0-9MB SI_BIOS: 9MB-32MB Padding/Unused: 32MB-64MB Additionally, able to hit CPU reset on MTLRVP (has 64MB SPINOR) with Rex AP Firmware binary. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibcc2206456639ef4ff22e0c4069521e583be58cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66828 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-18Revert "soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS"Subrata Banik
This reverts commit eb80b1efa36c99e485b2604e913c2aa316168eea. Reason for revert: Results into hard hang with serial debug msg inside FSP-S. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8e7cf804828da8939f591eb0770c8daf830c8d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-17mb/google/nissa: Simplify LTE GPIO config using pad-based overridesReka Norman
Currently, to enable/disable LTE based on fw_config on nissa, we have two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to prevent the SAR interrupt pin GPP_H19 from floating for the short period of time between enabling it in gpio.c and disabling it in fw_config.c (see CB:64270 for more details). With the new pad-based GPIO overrides (CB:64712), this is no longer an issue since the gpio.c and fw_config.c overrides are applied at the same time. So simplify the LTE GPIO configuration by enabling all the LTE pins in the variant gpio.c, then disabling them in fw_config.c if needed. BUG=b:231690996 TEST=LTE still works on nivviks Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17mb/google/skyrim/port_descriptors: replace sbna acronym with mdnFelix Held
Since the SoC that was upstreamed as Sabrina was finally renamed to Mendocino, also adjust the abbreviation used for the DXIO/DDI descriptor struct array names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14ecf98e4a94376a70e783774c8f7b8701581220 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66815 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17ec/google/chromec: Add BFIV, BFCTTim Van Patten
The flag EC_BATT_FLAG_CUT_OFF was added with the CL: 3704470: battery: Set battery cutoff flag https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704470 This flag is set in the ACPI memory mapped area when the command `ectool batterycutoff` is issued so ACPI code can respond appriopriately. This CL adds the flags to coreboot ACPI. BRANCH=none BUG=b:217911928 TEST=Boot nipperkin with low & no battery TEST=Boot skyrim with low & no battery Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I4e63ff4fc2d6b0ecf767a6bffd81f823c74c15bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66803 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17commonlib/clamp.h: Relicense file to be BSD-compatibleAngel Pons
I added this header in commit a6c8b4becbd12fe6043557ca1e398c1a7c691007 (nb/intel/sandybridge: Rewrite get_FRQ). Relicense it as "BSD-3-Clause OR GPL-2.0-or-later" and move it into the BSD-licensed commonlib part. Change-Id: I89ebdcdf8d06e78e624e37a443696981b3b17b7d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66711 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17soc/intel/apollolake: Add the remaining CSE Firmware Status RegistersSean Rhodes
Add the Shadow Registers from 2 through 5 and print information from them accordingly. All values were taken from Intel document number 571993. Tested on the StarLite Mk III and the correct values are shown: [DEBUG] CSE: IBB Verification Result: PASS [DEBUG] CSE: IBB Verification Done : YES [DEBUG] CSE: Actual IBB Size : 88 [DEBUG] CSE: Verified Boot Valid : FAIL [DEBUG] CSE: Verified Boot Test : NO [DEBUG] CSE: FPF status : FUSED Please note, the values shown are in an error state. This replaces the Fuse check that is done via Heci, as this will only work whilst the CSE is in a normal state. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17soc/intel/apollolake: Enable DPTF & SMBus as it is a required deviceSean Rhodes
coreboot is unable to disable certain devices, whilst many are hidden DPTF and SMBus are not. Set this to enabled chipset so that it is enabled by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85d74179b6fe3c6126566422f82f7b806f80d0c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17mb/google/nissa/var/yaviks: Generate SPD ID for supported memory partsWisley Chen
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) BUG=b:242277219 BRANCH=None TEST=run part_id_gen to generate SPD id Change-Id: I46c168482113beb7cd28f387ed495847aba8602f Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-17mb/google/nissa: Create yaviks variantWisley Chen
Create the yaviks variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:242277219 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVIKS Change-Id: Id60fe0e54a8e0196a302141f58c6695779ac251a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-17soc/intel/tigerlake: Disable DISPLAY_FSP_VERSION_INFO on IOTFrans Hendriks
Build error for platforms using Intel FSP for TGL_IOT (FSP_TYPE_IOT). File FirmwareVersionInfoHob.h does not exist in Intel FSP TGL IOT package. File FirmwareVersionInfoHob.h is included when DISPLAY_FSP_VERSION_INFO is enabled. Enable this config for non TGL_IOT only. BUG = NA TEST = Verify that DISPLAY_FSP_VERSION_INFO is disabled by default for TGL_IOT configuration (Build Siemens AS_TGL1). Change-Id: Ief5a7222daf6f1658e8dc04f97b4ddc2bcb74905 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66636 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17soc/amd/common/include/espi: add more decode rangesFelix Held
Mendocino has more eSPI decode ranges than Picasso or Cezanne. To support these additional ranges, introduce a new Kconfig option SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by the SoCs that support the additional eSPI IO/MMIO decode ranges. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-17mb/google/brya/var/ghost: Enable NXP UWB SR150 chipJack Rosenthal
Add GPIO configuration and device tree to enable the chip. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=Patch linux with NXP's pending drivers UWB device is probed and can respond to a simple hello packet Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17soc/intel/common: Update the comments for CSE RX and TX functionsSridhar Siricilla
The patch updates the comments on return values and heci_reset() triggering during error scenarios of heci_receive() and heci_send() functions to reflect the current implementation. Test=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6c6c3312602c772147cb315db9ea1753d84a0fb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17mb/google/nissa/var/pujjo: Configure EE noise mitigation for pujjoLeo Chou
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 - Set pre-wake randomization time (DPA) to 100 BUG=b:241349500 TEST=build FW and checked fsp log. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Id4a1540de8c3ee74695631acc8181dcc446fe137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66783 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17mb/google/nissa/var/pujjo: Add FW_CONFIG probe for supported devicesStanley Wu
Add FW_CONFIG probe based on pujjoteen boxster of below devices: LTE, SD card, stylus, WFC camera, AUDIO BUG=b:236158122 TEST=Boot to OS and verify that above devices are set based on fw_cofnig. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I49fc5461e7affba68a6b89bf166c84598fbfa088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66741 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17mb/google/brya/var/ghost: Add max98396 supportEric Lai
Ghost has two amps and address are 0x3c and 0x3d. BUG=b:231581723 BRANCH=firmware-brya-14505.B TEST=max98396 driver can get the DSD property correctly. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17drivers/i2c: add MAX98396 driverEric Lai
Add MAX98396 support. BUG=b:232606045 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I835b51ea1fcc9363992d43a625f80cb545802fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17soc/intel/broadwell: Unselect VBOOT_STARTS_IN_ROMSTAGEYu-Ping Wu
Starting vboot earlier in bootblock instead of romstage is usually preferred (smaller root of trust, among other things). Therefore unselect VBOOT_STARTS_IN_ROMSTAGE for broadwell. Also remove the unused BROADWELL_VBOOT_IN_BOOTBLOCK option. Change-Id: If8feea403ee4cd3a16ed8cb0faf9f4ccb34feaaf Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17Revert "soc/intel/broadwell: Drop vboot support"Yu-Ping Wu
This reverts commit f87489bbae5bb1ae3b17b6a03af9e309769b1f72. Reason for revert: Broadwell actually supports early flash writes. Change-Id: I342aefe464c72a32b41a40062b62d871caa0707b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17mb/google/skyrim: Move I2C config to devicetreeJon Murphy
The I2C config was unnecessarily placed in the overridetree. As we prepare for fanout, this is going to cause unnecessary noisy changes. Move the I2C config to the devicetree to avoid this. BUG=None TEST=Build Change-Id: I09ad5c911a0fd00274761cb71e9b659b47cd6da1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66802 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17pciexp_device: Fix offset handling for extended capabilitiesNico Huber
The PCIe spec explicitly states that the bottom-two bits of the next offset are reserved for future use and should be masked. We can also change the loop condition to avoid wrong offsets below 0x100 (exten- ded capabilities always reside in the extended config space). The whole patch series was tested on Google Samus and keeps the L1ss configuration of the WiFi device in tact. Change-Id: I0b622a0ce0a4a1127d266226ade0ec1e66e9fb79 Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66459 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17pciexp: Refactor extended capability handlingNico Huber
Add some inline functions for the bit-wise operations, change the loop body to an if-bail-out style and remove stateful variables. Change-Id: Ia8db915f375737064e3486d313383d9b6c3eb2b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66458 Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17pciexp_device: Drop quirk handling in pciexp_get_ext_cap_offset()Nico Huber
Keeping these checks in generic code seems rather dangerous. In theory, it could lead to endless loops even for compliant devices, if we accidentally detect arbitrary register contents as capability and use them as a pointer to another one. Not to forget that the register reads can have side effects. All users of this `cafe` have been converted to use pciexp_find_ext_vendor_cap(). Change-Id: I70d21534e04282a4156572a290b83c46be085e0c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66456 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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