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2023-06-22arch/x86,lib: Migrate SMBIOS implementation to common codeBenjamin Doron
SMBIOS is not specific to architecture, and this is mostly a generic implementation. Therefore, move it to common code, having architecture-specific code define some functions to fill this data. Change-Id: I030c853f83f8427da4a4c661b82a6487938b24e6 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75886 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-06-22soc/amd/common/psp_verstage: move post codes to own headerlilacious
In order to clean up the post code macros, move them to a separate header away from unrelated code. The new header file is included in the file where the post codes are moved out of, so that the current state remains unchanged. Change-Id: I28a932ce071488e90000e1bbd30b4d739a4bae43 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-22mb/qemu/aarch64: Add PCI supportArthur Heymans
Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and see that it gets found and picked up by the resource allocator. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22allocator_v4: Remove redundant parameterNico Huber
update_bridge_resource() already gets the type passed as part of the resource. Change-Id: I6b3c9809caecdd1bad5b98891a00c3392190a3e0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-06-22allocator_v4: Manually inline some thin functionsNico Huber
Inline functions that are only called once to improve readability. The calling functions still have rather short bodies, and the reader won't have to look down yet another layer to understand what they are doing. Change-Id: Ib4aa5d61dfa88c804a1aaee028185e00c5fbb923 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-22allocator_v4: Factor resource printing outNico Huber
Factor all the resource printing out into separate functions. This results in one-liners in the actual program code which hopefully will distract less during reading. Change-Id: I766db379f3b62d641cb3c41ebe0394b60ba57f7a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65421 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22allocator_v4: Use memranges only for toplevelNico Huber
During phase 1 of the resource allocation we gather all the size requirements. Starting from the leafs of our devicetree, we cal- culate the requirements per bus, until we reach the resource do- main. However, because alignment plays a role, we can't just accumulate the sizes of all resources on a bus. Instead, we already sort all the resources per bus to predict their relative placement, inclu- ding alignment gaps. Then, phase 2 has to perform the final allo- cations with the exact same relative placement. This patch introduces a very simple mechanism to avoid repeating all the calculations: In phase 1, we note the relative `base` of each resource on a bus. And after we allocated all the resources directly below the domain in phase 2, we add the absolute `base` of bridge resources to the relative `base` of child resources. This saves most of the computational complexity in phase 2. How- ever, with a shallow devicetree with most devices directly below the domain, this won't have a measurable impact. Example after phase 1: domain | `-- bridge #0 | res #0, base 0x000000 (relative), | size 12M, align 8M | |-- device #0 | res #1, base 0x800000 (relative), | size 4M, align 4M | `-- bridge #1 | res #2, base 0x000000 (relative), | size 8M, align 8M | `-- device #1 res #3, base 0x000000 (relative), size 8M, align 8M After phase 2 allocation at the domain level (assuming res #0 got 0xa000000 assigned): domain | `-- bridge #0 | res #0, base 0xa000000 (absolute), | size 12M, align 8M | |-- device #0 | res #1, base 0x800000 (relative), | size 4M, align 4M | `-- bridge #1 | res #2, base 0x000000 (relative), | size 8M, align 8M | `-- device #1 res #3, base 0x000000 (relative), size 8M, align 8M Now, all we need to do is to add the `base` of bridge resources recursively. Starting with resources on the bus below bridge #0: domain | `-- bridge #0 | res #0, base 0xa000000 (absolute), | size 12M, align 8M | |-- device #0 | res #1, base 0xa800000 (absolute), | size 4M, align 4M | `-- bridge #1 | res #2, base 0xa000000 (absolute), | size 8M, align 8M | `-- device #1 res #3, base 0x000000 (relative), size 8M, align 8M And finally for resources on the bus below bridge #1: domain | `-- bridge #0 | res #0, base 0xa000000 (absolute), | size 12M, align 8M | |-- device #0 | res #1, base 0xa800000 (absolute), | size 4M, align 4M | `-- bridge #1 | res #2, base 0xa000000 (absolute), | size 8M, align 8M | `-- device #1 res #3, base 0xa000000 (absolute), size 8M, align 8M Change-Id: I70c700318a85f6760f27597730bc9c9a86dbe6b3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65420 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-22allocator_v4: Treat above 4G resources more nativelyNico Huber
We currently have two competing mechanisms to limit the placement of resources: 1. the explicit `.limit` field of a resource, and 2. the IORESOURCE_ABOVE_4G flag. This makes the resource allocator unnecessarily complex. Ideally, we would always reduce the `.limit` field if we want to "pin" a specific resource below 4G. However, as that's not done across the tree yet, we will use the _absence_ of the IORESOURCE_ABOVE_4G flag as a hint to implicitly lower the `limit` of a resource. In this patch, this is done inside the effective_limit() function that hides the flag from the rest of the allocator. To automatically place resources above 4G if their limit allows it, we have to allocate from top down. Hence, we disable the prompt for RESOURCE_ALLOCATION_TOP_DOWN and turn it on by default. Platforms that are incompatible should be fixed, but can also override the default as a temporary measure. One implication of the changes is that we act differently when a cold-plugged device reports a prefetchable resource with 32-bit limit. Before this change, we would fail to allocate the resource. After this change, it forces everything on the same root port below the 4G line. A possible solution to get completely rid of the IORESOURCE_ABOVE_4G flag would be rules to place resources of certain devices below 4G. For instance, the primary VGA device and storage and HID devices could be made available to a payload that can only address 32 bits. For now, effective_limit() provides us enough abstraction as if the `limit` would be the only variable to consider. With this, we get rid of all the special handling of above 4G resources during phase 2 of the allocator. Which saves us about 20% of the code :D An earlier version of this change (commit 117e43611548) had to be reverted because of missing resource reservations in platform code. This is worked around now with commit ae81497cb6c7 (device/pci: Limit default domain memory window). Change-Id: Ia822f0ce648c7f7afc801d9cb00b6459fe7cebea Signed-off-by: Nico Huber <nico.h@gmx.de> Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/65413 Original-reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-22mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2msTarun Tuli
Reducing the polling time from 16ms to 2ms. Experimentally we have determined that the link state normally takes approximately 3.5ms to update and therefore we were waiting longer than necessary. TEST=build and confirm we are not waiting the extended period. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8fabb5ac46cae5c92d5b6f1dc0641a4d121c61dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76052 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-22mb/google/brya/acpi: Set power down delay to 2ms after PEXVDDTarun Tuli
Reduce the delay between PEXVDD and NVVDD from 3ms to 2ms during power down sequences. The hardware discharge is aggressive enough that we can safely optimize this. BUG=b:288267305 TEST=build and measured delay is acceptable Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I7c65301414044487e50bbbca618c4e602e571cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76051 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-22mb/google/brya/acpi: Don't wait for PG in GPU off sequencesTarun Tuli
When powering rails down, there is no value in waiting for the PG signal to de-assert. Instead, shut the rails off as quickly as possible while maintaining a controlled ordering. BUG=b:288266850 TEST=build and measured delays are gone Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: If31691a7d62b72661fcbacb34e90f3a6adec8134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76050 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22mb/google/rex: Disable TCSS config for pre-boot displayKapil Porwal
Pre-boot display is not POR for google/rex hence disable the config ENABLE_TCSS_DISPLAY_DETECTION. BUG=b:247670186 TEST=Build and boot to google/rex and make sure that display over TCSS works in the OS Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib55e251a4620c7a375ee2f27763154c39207236e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-22mb/google/nissa/var/joxer: Disable GPIOs for SD card readerTerry Chen
the board won’t have a SD card reader, so disable it. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Change-Id: I6a55058b453771d264700a1364ef538f831148e4 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-22vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mappingFelix Held
For Phoenix the lane numbers in the DXIO descriptor match the ones in the schematic, so remove the corresponding text and the table from the comment on the fsp_dxio_descriptor struct. Since there's no logical to physical lane number remapping needed for the lanes in the Phoenix DXIO descriptors, drop the 'logical' from the start_logical_lane and end_logical_lane fields in the DXIO descriptor and rename those to start_lane and end_lane. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-21mb/google/rex/var/screebo: set HBR smbus pin as NCSimon Zhou
Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin as NC, in case it prevents ese and cse from entering suspend. BUG=b:283053968 TEST=Verified on screebo non-TBT SKU, suspend and resume works. Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21soc/mediatek: Add a prompt string for MEDIATEK_DRAM_SCRAMBLEXi Chen
Make the default MEDIATEK_DRAM_SCRAMBLE value overridable by adding a prompt string. BUG=b:285474337 TEST=build pass and check scramble feature is disabled on serial build Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I703ac9aa3ccc4dd9d0fef9949c6b0d49449971a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75815 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21mb/intel/adlrvp_rpl: Add initial code for adlrvp_rpl variantHarsha B R
This patch adds the initial code for adlrvp_rpl variant board which includes 1. Add overridetree.cb to corresponding variant directory 2. Update mainboard name in Kconfig and Kconfig.name 3. Add config option to select corresponding overridetree.cb BUG=b:286030718 BRANCH=firmware-brya-14505.B TEST=Able to build with the patch and boot the adlrvp_rpl platform to ChromeOS on Windows SKU. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ifb95ff705189863d23894769ff450f9528e73b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73962 Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-06-21mb/google/rex: Fix PLD for USB type-A portKapil Porwal
USB type-A port with same PLD.token information as USB type-C port, causes conflict while generating ACPI code for the EC CONN device. Use a different PLD.token number for type-A port to fix the issue. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. before patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS01 }, after patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS03 }, Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-21mb/google/rex/var/ovis: Select SOC_INTEL_METEORLAKE_U_HJakub Czapiga
Ovis uses MTL-H. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis TEST=cros build-packages --board ovis chromeos-bootimage Change-Id: I284c72b902490187d0b15e4fc81650af1cfa16d7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75887 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDSSubrata Banik
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228). With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-20arch/x86: Introduce DUMP_SMBIOS_TYPE17 configEric Lai
DDR5 spd is not supported read by coreboot. But FSP can read it, so print the memory information from smbios type17 dimm information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-20mb/intel/mtlrvp: disable acpi timer for xtal shutdownSukumar Ghorai
acpi timer needs to be disabled for xtal shutdown, requirement for platform to enter deepest sleep state (s0i2.2). BUG=b:274744845 TEST=Able to boot and verify S0ix is working w/o this cl: > iotools mmio_read32 0xfe0018fc 0x0 > iotools mmio_read32 0xfe4018fc 0x0 w/ this cl: > iotools mmio_read32 0xfe0018fc 0x2 > iotools mmio_read32 0xfe4018fc 0x2 Change-Id: Ib87b7555217b6954fca98f95b86d03016cd9b783 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75898 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-20mb/google/hades: Update typeC usb PLDEric Lai
get_usb_port_references refer the PLD group. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3 to group 1. Update the PLD panel to back as well. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75912 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-20treewide,intel/skylake: Use boolean type for s0ix_enable dt optionFelix Singer
Using the boolean type and the true/false macros give the reader a better understanding about the option. Thus, use the bool type for the attribute and use the macros for assignments. Skylake mainboards which use that option were changed by the following command ran from the root directory. socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \ option="s0ix_enable" && \ grep -Er "${socs}" src/mainboard | \ cut -d ':' -f 1 | \ awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \ xargs grep -r "${option}" | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-06-20soc/amd/common/iommu: Use preprocessor values for IOMMU baseArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I85f58565bf1f955f704e223d538d0b374bc6fbda Reviewed-on: https://review.coreboot.org/c/coreboot/+/75915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-06-20mb/google/rex/var/rex0: Configure I2C timing for I2C devicesIvy Jian
Configure I2C0/1/3/4 timing in devicetree to ensure I2C devices meet timing requirement. Note that I2C5 timing will be updated separately when the tuning done BUG=b:280559903 TEST=Build and check I2C devices timing meet spec. | | I2C0-Codec | I2C0-WFC | I2C1 | I2C3 | I2C4 | |-------------|------------|----------|--------|-------|---------| | FSMB(KHz) | 347 | 343.2 | 389.3 | 393.7 | 381.9 | | TLOW(us) | 2.1 | 2.093 | 1.895 | 1.902 | 1.953 | | THIGH(us) | 0.647 | 0.628 | 0.602 | 0.62 | 0.612 | | THD:STA(us) | 0.633 | 0.64 | 0.601 | 0.6 | 0.601 | | TSU:STA(us) | 0.617 | 0.621 | 0.619 | 0.659 | 0.61 | | TSU:STO(us) | 0.656 | 0.647 | 0.667 | 0.727 | 0.634 | | TBUF(us) | 86.15 | >14.088 | >9.833 | >8 | >10.366 | Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I5421e4fe68e856bbe9f19544954a94670c895a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75150 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-20mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3Rui Zhou
Remove rp2 and add rp1/rp3 for screebo BUG=b:286187816 BRANCH=none TEST=emerge-rex coreboot and verify TBT works. Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75832 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19device/resource_allocator_v4: Remove "ERROR: " from log messageElyes Haouas
It is no longer necessary to explicitly add "ERROR: " in front of BIOS_ERR message. Change-Id: I3ff2081d38f94556481efa02f242795bbfc77517 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75876 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19mb/google/nissa/var/joxer: enable ELAN and G2touch touchscreenMark Hsieh
Update overridetree to support ELAN and G2_G7500 touchscreen. BUG=b:285477026 TEST=emerge-nissa coreboot and check touchscreen function Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I236a2815f956929c6cd84c981cb15e9ab0f657b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75762 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/amd/common/block/include/amdblocks/data_fabric: fix typo in 'IOAPIC'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie17fd14bed9ec91c5f11aee00bf5d2d2e253ec08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75897 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/amd/*: Use proper resource function to declare GNB IOAPICsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I296697d579b9ad8e35b22ada939a74a5ef6d6f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75828 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/cometlake: Enable early caching of RAMTOP regionSean Rhodes
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I579f85e84e0aba7f192ff81a6725d65b7f79ff75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74517 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19cbfs: Allow controlling decompression of unverified filesJulius Werner
This patch adds a new Kconfig that controls whether CBFS APIs for unverified areas will allow file decompression when CBFS verification is enabled. This should be disallowed by default because it exposes the attack surface of all supported decompression algorithms. Make allowances for one legacy use case with CONFIG_SOC_INTEL_CSE_LITE_ COMPRESS_ME_RW that should become obsolete with VBOOT_CBFS_INTEGRATION. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ieae420f51cbc01dae2ab265414219cc9c288087b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75457 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-06-19soc/intel/apollolake: Switch to snake case for SataPwrOptimizeDisableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPwrOptimizeDisable'. Change-Id: I35b36f60d2f00bfad307dff7bd131c20ebccf60b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75859 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableSataSalpSupportMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableSataSalpSupport'. Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for PmicVdd2VoltageMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicVdd2Voltage'. Change-Id: I179b8f5b56c5bfe7f6fc3148e4c95954c0755ffd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75857 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyVoltageBumpMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyVoltageBump'. Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75856 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-19soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrlMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicPmcIpcCtrl'. Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for SataPortsHotPlugMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsHotPlug'. Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75852 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Fix FSP SATA speed limit configuraionMario Scheithauer
With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit configurable") came the expansion to adjust the SATA speed. Unfortunately, APL FSP-S sets only the default value, so Gen 3, and ignores the passing parameter value. Since the corresponding register entry can only be changed once, the setting must be made on coreboot side before FSP-S is called. This patch fixes the SATA speed configuration for Apollo Lake CPUs. Link to Intel Pentium and Celeron N- and J- series datasheet volume 2: https://web.archive.org/web/20230614130311/https://www.intel.com/content/www/us/en/content-details/334818/intel-pentium-and-celeron-processor-n-and-j-series-datasheet-volume-2.html BUG=none TEST=Boot into Linux and check SATA configuration via dmesg ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA mode ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126 ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75820 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18acpi/acpi.c: Return function argument when bailing outArthur Heymans
Returning a constant value makes the function easier to read and think about. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ifdf7acec38a7c958aac2cf1f3bbf16c27fa90b8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75903 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18acpi/acpi.c: Change signature of write_acpi_tablesArthur Heymans
The argument is copied into current and is never modified. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3084e43ccbe9749bc726af3120decfe8b52e1709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75902 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18mb/google/rex/variants/ovis: Add display configurationJakub Czapiga
Enable DDI on ports 1 to 4 for Type-C DisplayPort. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I40f967b12b11c10a1a9329bfb42ebec5a8d7738f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75579 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18drivers/intel/fsp2_0: Correct FPDT timestamp unit and macro nameRonak Kanabar
FSP performance timestamp is in nano second by default. This patch is to correct unit in FSP performance timestamp data print and macro name to avoid confusion. Change-Id: I4aec4f63beddbd7ce6e8e3fc1b53a45da2ee0b00 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75816 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-17acpi/acpi.c: Fix printing all ACPI tablesArthur Heymans
Loop over tables in xsdt instead of maintaining a list of local variables to loop over. Some tables were not generated directly in the write_acpi_tables function, like IVRS or SRAT. Now those tables are printed too and the code is simpler. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie0a6e2b6e2b72b5c8f59e730bea9b51007b507b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75860 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-06-17vc/intel/edk2: Remove edk2-stable202111 supportRonak Kanabar
This patch removes the support for edk2-stable202111 as MTL has migrated to edk2-stable202302, and no other platform is utilizing edk2-stable202111. The support for edk2-stable202111 is no longer necessary. Change-Id: Ide1864e0a42a4c0a81c3c94b1b1254f8fad062af Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75817 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17lib/fw_config: Make fw_config_is_provisioned() always availableJakub Czapiga
Move fw_config_is_provisioned() implementation to header file and make it static inline. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I2ea21b19339cd93ba78dbe25213cbfb40e012937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-17mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the anx7452 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The anx7452 retimer does not appear to support this feature, so let the SoC do the flip. BUG=b:267589042,b:281006910 TEST=verified DP-ALT mode works on rex using both cable orientations Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75827 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-17mb/google/myst: Update WWAN usb entryEric Lai
USB3 is used for both typeA and WWAN based on different DB. BUG=b:287159026 TEST=change FW config and check typeA and WWAN can work. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba Reviewed-on: https://review.coreboot.org/c/coreboot/+/75819 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17mb/google/nissa/var/gothrax: Generate RAM IDs for new memory partsYunlong Jia
Add the support RAM parts for gothrax. Here is the ram part number list: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) BUG=b:284388714 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75834 Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-17soc/intel/meteorlake: Update tcss_usb3 aliasEric Lai
TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-16soc/intel/meteorlake: select UDK_202302_BINDING KconfigRonak Kanabar
MTL FSP uses 202302 Edk2. select UDK_202302_BINDING Kconfig for MTL SoC. BUG=b:261689642 TEST= Build and boot to Google/rex. Change-Id: I9167e3b08a2a1fa2f4cc6ca11cb8308dc56fd940 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75728 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16vendorcode/intel: Add edk2-stable202302 supportRonak Kanabar
edk2-stable202111 is older release of edk2. MTL FSP uses 202302 Edk2. There are structure definition changes between 202111 and 202302. One of change is in FSP_INFO_HEADER structure. Also, Next Gen Intel SoC needs 202302 Edk2. This patch includes (edk2/edk2-stable202302) all required headers for edk2-stable202302 EDK2 tag from EDK2 github project using below command: git clone -b edk2-stable202302 https://github.com/tianocore/edk2.git commit hash: f80f052277c88a67c55e107b550f504eeea947d3 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Add UefiCpuPkg/Include Because `MpServices2.h` file is part of `UefiCpuPkg/Include/Ppi/` Add following fixes from edk2-stable202111 060492ecd2 Safe guard enum macro in SmBios.h 2bf9599cf1 Use fixed size struct elements BUG=b:261689642 TEST= select UDK_202302_BINDING Kconfig for MTL, Test Build and boot rex Image Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-06-16mb/google/nissa/var/joxer: Disable storage devices based on fw_configMark Hsieh
- Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this. (it disables all probed devices when fw_config is unprovisioned.). - Removed `bootblock-y += variant.c` from Makefile.inc based on CL:3841120.(The infrastructure for selecting an appropriate firmware image to use the right descriptor is now ready so runtime descriptor updates are no longer necessary.). BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I6920d88dfec86676ff6733146f748e06d4085c49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75743 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-16google/zork: Convert baseboard directory layoutKyösti Mälkki
There are two baseboards within the set of mainboards built here, with baseboard name appended in the filenames. Take the style and variable BASEBOARD_DIR from google/brya, then move and rename the supporting files under separate directories. Change-Id: I2046b6f82519540b8596ce925203bd60d1870c1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74471 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16mb/amd/birman/devicetree_phoenix: update USB PHY settingsFelix Held
Update the initial USB PHY tuning values that were a copy of the ones from the Chausie mainboard to the values used in the Birman UEFI firmware reference implementation. The USB3 PHY tuning values are still the same while some of the USB2 PHY tuning values are different. The last two USB2 PHYs that are used by the USB4 controllers have a different parameter set compared to the other USB2 PHYs. TEST=All USB ports on Birman function as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75823 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16soc/intel/common: Add configs for TME exclusion range and new key genPratikkumar Prajapati
Add following config options. 1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. 2. TME_EXCLUDE_CBMEM_ENCRYPTION This option allows to exclude the CBMEM region from being encrypted by Intel TME. When TME is enabled it encrypts whole DRAM. TME provides option to carve out a region of physical memory to get excluded from encryption. With this config enabled, CBMEM region does not get encrypted by TME. If TME is not programmed to generate a new key in warm boot, exclusion range does not need be programmed due to the fact that TME uses same key in warm boot if TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed to generate a new key in warm boot, contents of the CBMEM get encrypted with a new key in each warm boot case hence, that leads to loss of CBMEM data from previous warm boot. So enabling this config allows CBMEM region to get excluded from being encrypted and can be accessible irrespective of the type of the platform reset. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75625 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16mb/google/myst: Add additional memory configurationsRob Barnes
Add additional ram parts and generate strapping ids. BUG=b:285216975 TEST=Build myst image Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75821 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-16soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMCSubrata Banik
This patch disables the ACPI PM timer which is necessary for XTAL OSC shutdown. Also, disabling ACPI PM timer switches off TCO. BUG=b:274744845 TEST=Able to boot and verify S0ix is working even with EC reset and cold boot scenarios. w/o this cl: > iotools mmio_read32 0xfe4018fc 0x0 w/ this cl: > iotools mmio_read32 0xfe4018fc 0x2 Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPDRen Kuo
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I3797de01629fdb5ace4c610943d88db525da112b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75826 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-06-15security/intel/cbnt/Makefile: Fix invalid char '*'Elyes Haouas
It seems that using a wildcard (*) in the import path is not supported in the context of the Makefile. This to fix this error: malformed import path "cmd/cbnt-prov/*.go": invalid char '*' Change-Id: I953e06f1ff70a2b61bc5f505f7df9936b7f9b55b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-15mb/google/rex: Enable audio BT offloadRavi Sarawadi
This patch enables BT offload feature on Rex over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15mb/google/nissa/var/pujjo: Set GPIO of WWAN_SAR_DETECT to NCLeo Chou
Pujjo does not support GPIO based D-SAR, so set GPP_D15 and GPP_H23 to NC. BUG=b:275264095 TEST=boot on pujjo and no impact WWAN dynamic SAR function Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75403 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15mb/google/myst: Add PSP verstage callbacksKarthikeyan Ramasubramanian
Lay the groundwork to prepare for enabling PSP verstage. This change adds PSP verstage callback to enable eSPI, TPM etc. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75585 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-15soc/intel: Add max memory speed into dimm infoEric Lai
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check dmidecode dump the max speed. Handle 0x000C, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR5 Type Detail: Unknown Synchronous Speed: 5600 MT/s Manufacturer: Micron Serial Number: 3f064d84 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: MTC8C1084S1SC56BG1 Rank: 1 Configured Memory Speed: 5200 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15drv/i2c/pi608gp: Fix styleJan Samek
In commit e59f18bf29a8 ("drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)"), there were some suggestions after it's been already merged. This patch addresses the points regarding the code style and comments. BUG=none TEST=Build OK, no behavioral changes in the pi608gp driver, console logs without changes. Change-Id: I5fc54708e0085fea4bd1f2fbf2afb400d2ccbd46 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-15drv/i2c/pi608gp: Fix typesJan Samek
In commit e59f18bf29a8 ("drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)"), there were some suggestions after it's been already merged. This patch addresses the points regarding the number types - fix of the printk format strings, inclusion of 'stdint.h' and marking the set of allowed values as constant. BUG=none TEST=Build OK, no behavioral changes in the pi608gp driver, console logs without changes. Change-Id: I34c664f6a8a257b260facdbf9043825ff4a4c932 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75500 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-06-15soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bitsMichał Żygowski
Based on: - Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 - 7th Generation Intel Processor Families I/O for U/Y Platforms Datasheet Vol.2 August 2017: https://cdrdv2.intel.com/v1/dl/getContent/334659 - edk2-platforms source for Whitley and Purley platforms (Xeon SP) Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_BMichał Żygowski
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72072 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_BMichał Żygowski
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I11241836ecc9066d323977b030686567c87ed256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15soc/amd/*/root_complex: reserve IOMMU MMIO areaFelix Held
This makes sure that the resource allocator won't use this address range for anything else. In the systems I looked at, this was between the end of the above 4GB memory and the beginning of the above 4GB PCI BAR MMIO region, but better reserve it here so nothing else will get allocated there if this expectation isn't met. TEST=Reserved region is printed in the console logs: update_constraints: PCI: 00:00.0 09 base fd00000000 limit fdffffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-15mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1Jan Samek
It's been decided not to use the USB 3.0 port 1 on this board anymore, so disable it also with the corresponding USB 2.0 lane. BUG=none TEST=USB 3.0 port 1 not functional anymore after boot, while others continue working. Change-Id: I2799e3d9d7232743c9480dd9611d94ed3249f53b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-15soc/intel/cmn/cse: Read ISH FW version if avilable in CSE partitionSubrata Banik
This patch reduces the redundant config check to understand if an ISH FW partition is available and to fetch the ISH FW version. The goal is to fetch the ISH FW version if the ISH FW belongs to the CSE firmware partition table. Change-Id: I689a71377e7aea0fa3bc1835f355708c33c2caea Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75811 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`Dinesh Gehlot
This patch calls get CSE RW version function from .final hook if the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected. BUG=b:280722061 TEST=Able to build and boot google/rex. > cbmem -c | grep "CSE RW Firmware Version:" [DEBUG] CSE RW Firmware Version: 18.0.0.1682 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75749 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/cmn/cse: Always save CSE RW version to CBMEMSubrata Banik
This patch renames `cse_store_rw_fw_version` function that store currently running CSE RW FW version inside CBMEM. Additionally, perform the CSE RW FW storing operation unconditionally. TEST=Able to build and boot google/marasov. Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version configSubrata Banik
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15mb/google/dedede/var/boxy: Update audio codec HID to use correct ALC5682I-VDKevin Yang
Boxy audio codec chip uses ALC5682I-VD, not ALC5682I-VS. It needs to modify codec HID to "10EC5682" in coreboot to fix audio no output sound issue. BUG=b:286970886 BRANCH=dedede TEST=confirm audio soundcard can be list by command "aplay -l" Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-15mb/google/rex: add Elan HID over SPI ASL for Rex0Eran Mitrani
This patch enables adding variant specific ASL code TEST=Kernel driver is able to communicate with device Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I231482d56dd4afa150766c07cfde105158e5e124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/var/rex0: add HID over SPI ACPI driverEran Mitrani
Add driver to support ELAN touchscreen using SPI for rex * See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum * https://www.microsoft.com/en-us/download/details.aspx?id=103325 BUG=b:278783755 TEST=Kernel driver is able to communicate with device. Also tested S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14soc|vc/amd/phoenix: Prepare for PSP verstageKarthikeyan Ramasubramanian
Update all the required sources to lay the ground work to enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75584 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-14soc/intel/alderlake/vr_config.c: Fix GT domain TDC currentMichał Żygowski
Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder Lake-S SKUs have GT TDC of 22A. Based on the default settings of ADL-S FSP. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-14acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic()Arthur Heymans
In soc/amd this function is unused so drop it and rename _acpi_fill_ivrs_ioapic(). Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-06-14soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOCArthur Heymans
By adding all DXIO IOAPIC with the same resource index, the IVRS code can always pick that resource which simplifies the code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-06-14acpi: Add a debug option to print out tables in ACPICA compatible hexArthur Heymans
Sometimes systems don't boot to the OS due to wrong ACPI tables. Printing the tables in an ACPICA compatible format makes analysis of ACPI tables easier. The ACPICA format (acpidump, acpixtract) is the following: " FACS @ 0x0000000000000000 0000: 46 41 43 53 40 00 00 00 E8 24 00 00 00 00 00 00 FACS@....$...... 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ " To achieve analyze ACPI tables capture the coreboot log between "Printing ACPI in ACPICA compatible table" and "Done printing ACPI in ACPICA compatible table". Remove the prefix "[SPEW ] " and then call 'acpixtract -a dump' to extract all the tables. Then use 'iasl -d' on the .dat files to decompile the tables. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75677 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAMMatt DeVillier
One specific Hynix LPDDR5x DRAM part requires an ABL workaround to eliminate DRAM-related failures during a FAFT test, but due to the use of generic/common SPDs, there is no way for the ABL to determine the DRAM part # itself. Consequently, we will have coreboot check the DRAM part #, and set/clear a CMOS bit as appropriate, which the ABL will check in order to apply (or not apply) the workaround. The ABL already uses byte 0xD of the extended CMOS ports 72/73 for memory context related toggles, so we will use a spare bit there. BUG=b:270499009, b:281614369, b:286338775 BRANCH=skyrim TEST=run FAFT bios tests on frostflow, markarth, and whiterun without any failures. Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2023-06-14soc/intel/xeon_sp: Fix HEST table lengthJeff Li
"current" points to the start of HEST table, so "next - current" already includes the size of its header, no need for increment here. This issue was found on SPR-SP platform. The length of HEST table is now correct with this patch. Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Signed-off-by: Jeff Li <lijinfeng01@inspur.com> Signed-off-by: Ziang Wang <ziang.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-14mb/google/nissa/var/joxer: Add DmaProperty for ISHMark Hsieh
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on joxer. BUG=b:285477026 TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA-FQ After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75758 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/rex/variants/ovis: Add basic DTTJakub Czapiga
Add default Intel DPTF. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/variants/ovis: Add USB and TCSS configurationJakub Czapiga
+-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/nissa/var/joxer: Remove fw_config probe for storage devicesMark Hsieh
When fw_config is unprovisioned, devicetree will disable all probed devices. However, boot-critical devices such as storage devices need to be enabled. As a temporary workaround while adding devicetree support for this, remove the fw_config probe for storage devices so that all storage devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI scan, but keeping it enabled should have no functional impact, only a possible power impact. BUG=b:285477026 TEST=On joxer eMMC and UFS SKUs, boot to OS and `suspend_stress_test -c 10` Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I834bd81ce636a6f32d50434cbf07b1d572620492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75757 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14drivers/wwan/fm: Fix format string vulnerability with snprintfJamie Ryu
This fixes format string vulnerability issues with snprintf statement found by klocwork scan. Foundby=klocwork BUG=NONE TEST=Boot to OS on Meteor Lake rex platform and run klocwork scan. Check related ACPI tables and modem driver behavior after changes. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ia6b7d70c0b2b86d0918e58348dccd206a7ee9193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75733 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14vc/intel/fsp/fsp20/meteorlake: Add VR config entriesSubrata Banik
This patch adds UPD entries into the FSP header file to configure VRs (IA, GT and SA). - `IccLimit` : VR Fast Vmode ICC Limit support - `EnableFastVmode` : Enable/Disable VR FastVmode - `CepEnable` : Enable/Disable CEP (Current Excursion Protection BUG=b:286809233 TEST=Able to build google/rex. Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-06-13mb/google/myst: Update PCIE_RST_L driveJon Murphy
PCIE_RST_L is attached to a pull down, change the init to NC. BUG=None TEST=Boot to OS Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-13mb/google/myst: Update PCIe romstage gpiosJon Murphy
Update PCIe GPIOs during rom stage to properly initialize the PCIe devices and allow the NVMe/eMMC to be properly detected. BUG=b:284213391 TEST=Boot to OS Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-13soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bitsFelix Held
Rename get_smee_reserved_address_bits to get_sme_reserved_address_bits since the feature is called secure memory encryption and the last 'e' in SMEE bit in the SYSCFG MSR just stands for enable. The function will return a valid number of reserved address bits no matter if this is enabled or not, so drop the second 'e'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-13mb/google/brya/variants/hades: Set WP signal to GPP_E12Tarun Tuli
Move the WP signal to GPP_E12 from the current GPP_E15 to match the design. BUG=b:285084125 TEST=WP signal reports as we expect Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-13mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPDDavid Wu
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-12soc/amd/stoney: Expand the SMM region for cacheZheng Bao
Currently the data to be put to cache region is 0x14FF90. With the limit size 0x150000, the data for S3 can not be put into. So we expand it a little. Change-Id: If6b03b713059c54c7dae8f2db0f6426d8aa1aab1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69782 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>