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2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-07soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSIONRonak Kanabar
This patch introduces support for storing the MRC cache based on the MRC version for both ADL-N and TWL platforms. It select the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_ALDERLAKE_PCH_N is chosen. BUG=b:296433836 Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81038 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brandon Weeks <bweeks@google.com>
2024-06-07intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSPRonak Kanabar
This patch is to switch Client ADL-N FSP headers to vendorcode from IOT headers. Also guard IOT headers & bin path with FSP_TYPE_IOT Kconfig. BUG=b:296433836 TEST=Able to build and boot google/nivviks Change-Id: I1ffcc3f284c213ff0533de3a0e228aacf523b380 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07mb/cwwk/adl: Select FSP_TYPE_IOTRonak Kanabar
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT FSP for both Client and IoT configurations, despite the Client FSP requiring distinct headers. The CWWK CW-ADL-4L-V1.0 board relies on the FSP provided by the 3rdparty/fsp submodule, which means it has been using the IoT FSP by default. To ensure the board continues to use the correct FSP as we plan to introduce Client FSP headers into vendorcode, we are now explicitly select FSP_TYPE_IOT for the CWWK CW-ADL-4L-V1.0 board. Change-Id: Ie3844cb24740e4d95ee835a44e55b4d5cb6854e5 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Brandon Weeks <bweeks@google.com>
2024-06-07mb/aoostar/wtr_r1: Select FSP_TYPE_IOTRonak Kanabar
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT FSP for both Client and IoT configurations, despite the Client FSP requiring distinct headers. The aoostar/wtr_r1 board relies on the FSP provided by the 3rdparty/fsp submodule, which means it has been using the IoT FSP by default. To ensure the board continues to use the correct FSP as we plan to introduce Client FSP headers into vendorcode, we are now explicitly select FSP_TYPE_IOT for the aoostar/wtr_r1 board. Change-Id: I68feeaaffd825013ae1012694047b067535e7341 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82914 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDsRonak Kanabar
PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating programming for ADL_N FSP. Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-06nb/intel/haswell: Synchronize lists of graphics PCI IDsNico Huber
Both, the list of IDs that we hooked our driver up to and the list that we use for VBIOS mapping, had gaps. Fill those. Change-Id: I97c09bb113cf0f35ae158abbd0ba2632dbad7cad Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-06mb/siemens/chili: Remove superfluous device entries from dtFelix Singer
Remove the entries which have the same state as the ones from the chipset devicetree. Change-Id: I4981cd835ef28a673d480808dd486fed4d9b45e5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-06arch/io.h: Add port I/O functions to other architecturesAlper Nebi Yasak
The QEMU Bochs display driver and the QEMU Firmware Configuration interface code (in the qemu-i440fx mainboard dir) were written for x86. These devices are available in QEMU VMs of other architectures as well, so we want to port them to be independent from x86. The main problem is that the drivers use x86 port I/O functions to communicate with devices over PCI I/O space. These are currently not available for ARM* and RISC-V, although it is often still possible to access PCI I/O ports over MMIO through a translator. Add implementations of port I/O functions that work with PCI I/O space on these architectures as well, assuming there is such a translator at a known address configured at build-time. Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80372 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-06mb/google/brox/var/lotso: Add dq map settingJian Tong
Based on lotso EVT schematics add dq map settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82600 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
2024-06-06mb/asrock: Add Z87E-ITX (Haswell)Nicholas Chin
This was done using Haswell autoport, with manual fixes to get the output to build against current main. I do not physically have this board; I was sent the output of autoport with some fixes on top of which I added additional changes. The VBT was copied from /sys/kernel/debug/dri/0/i915_vbt on version 2.70 of the vendor firmware. The flash chip is 8MiB in a socketed DIP8 package, making it easy to externally flash to recover from a brick. Working: - Haswell MRC.bin - S3 suspend and resume - Libgfxinit - HDMI - DVI-I (including passive DVI to VGA adapter) - DisplayPort - SATA ports - mSATA SSD - mPCIe WiFi slot - Rear USB ports - USB 3.0 header - Audio header - Ethernet - x16 PCIe slot - EHCI debug with the CH347 (top USB 2.0 port by the PS/2 connector) - edk2 (MrChromebox uefipayload_202309) Not Tested: - PS/2 keyboard/mouse - eSATA - USB 2.0 header Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81022 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/intel/coffeelake_rvp: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I98aa3f582963f76690f907b678ac322ed4cc99d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82846 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/starlabs/starbook: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I972516443bc57e193aefd54516ca994087d92054 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-05cpu/x86: Make 1GB paging the defaultJulius Werner
This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaning CPUs added in the future will automatically build the smaller 1GB pages. We can expect support for this feature to be available on all future CPU generations (with the possible exception of embedded edge cases), so this default setting should make mistakes less likely and keep maintenance effort lower. (Besides, enabling the support where it doesn't work fails fast, whereas keeping it disabled where it could work is an inefficiency that can easily go overlooked for a long time.) While this is technically a CPU feature, not a northbridge feature, we support a lot more individual CPUs than northbridges in the pre-SoC era, and they tend to be closely coupled anyway. So select the option at the northbridge level for older CPUs to keep things simpler. Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-05mb/google/brox/var/lotso: Update gpio settingJian Tong
Based on lotso EVT schematics update gpio settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82573 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-06-05arch/arm64: Support FEAT_CCIDXYidi Lin
ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented. If numsets and associativity from CCSIDR_EL1 are not correct, the system would hang during mmu_disable(). Rather than assuming that FEAT_CCIDX is not implemented, this patch adds a check to dcache_apply_all to use the right register format. Reference: - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770 BUG=b:317015456 TEST=mmu_disable works on the FEAT_CCIDX supported SoC. TEST=manually add mmu_disable to emulation/qemu-aarch64/bootblock.c and verify with the command qemu-system-aarch64 -bios \ ./coreboot-builds/EMULATION_QEMU_AARCH64/coreboot.rom -M \ virt,secure=on,virtualization=on -cpu max -cpu cortex-a710 \ -nographic -m 8192M Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82635 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-06-05mb/ibm/sbp1: Update PCIe port slot number for NICNaresh Solanki
Based on schematic, update slot number for PCIe port used for NIC controller. Change-Id: I7a1ead8f7e4588db45303041e60dbfe27ee12ea7 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-05Xeon-SP boards: Factor out OCP VPD `get_cxl_mode()` implAngel Pons
There's two copies of the `get_cxl_mode()` function to map the OCP VPD value to the values expected by platform code. As this is unnecessary, have a single copy of this function in the OCP VPD driver code. As the `get_cxl_mode()` function is Xeon-SP only, keep it in a separate file. This change simplifies things for boards using OCP VPD for CXL and has no impact for boards *not* using OCP VPD: - Boards not using OCP VPD can still define get_cxl_mode() in mainboard code as needed, just like they were able to do before. - Boards using OCP VPD but without CXL (`SOC_INTEL_HAS_CXL` is not enabled), this code won't get compiled in at all (see `Makefile.mk`). - Boards using OCP VPD and CXL will automatically make use of this `get_cxl_mode()` definition, which should be the same for all boards. It is possible that this may need to be expanded/adapted in the future, which is easy to handle in a follow-up commit when the need arises. TEST=Build and boot on intel/archercity CRB Change-Id: I935c4eb5b2392e2d0dc01b9f66d46c79b8141ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82224 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-05soc/intel/xeon_sp: Remove duplicated Kconfig POSTCAR_STAGEJincheng Li
POSTCAR_STAGE is already selected in XEON_SP_COMMON_BASE Change-Id: I3f94e6cc76c8f376119ffa8ec43fa1a43fb40977 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-05mb/google/trulo/var/orisa: Configure TPM IRQ for orisaAmanda Huang
Set GSC_SOC_INT_ODL to GPP_A17 instead of GPP_A13. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82717 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-04mb/starlabs/lite: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: Ib8f7ac7e586390a1d25cbe84d6d4c3ba31ff078f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-04soc/intel/xeon_sp: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I950b8859b51fb61edc0cf1115f6665378bc0b836 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82887 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-04soc/mediatek/common: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I50e874790dedcb6bf3b3ac8368821f22611aa3b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82894 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-04mb/google/brya/var/xol: Enable FSP UPD LpDdrDqDqsReTrainingSeunghwan Kim
Set LpDdrDqDqsReTraining to 1 for xol. Value 0 will cause black screen issue. Reference: https://review.coreboot.org/c/coreboot/+/79527 > FSP default value for LpDdrDqDqsReTraining is 1. For boards > that didn't set LpDdrDqDqsReTraining to any value, 0 was being > assigned and it caused black screen issue. BUG=b:332980211 BRANCH=brya TEST=Built and verified there is no black screen issue during power on/off test for over 100 cycles. Change-Id: Ia346ce559b4509ea1a63abe28b12ad909f9b7b0d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82778 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-04mb/google/brask/var/bujia: change ALC5650 to ALC5682I-VSShon Wang
Due to system spec change, change audio codec ALC5650 to ALC5682I-VS BUG=b:329787697 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I38e5c58b3ef3fbe709b98601975ae3821bb77213 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-04vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00Ronak Kanabar
Update generated FSP headers for Alder Lake N from v5021.00 Changes include: - Add FspProducerDataHeader.h header file - Open Usb4CmMode & CnviWifiCore Upd in FspsUpd.h - Update UPD Offset in FspsUpd.h BUG=b:296433836 TEST=Able to build and boot google/nivviks Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82780 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-04Revert "vc/intel/fsp2/alderlake_n: Drop unused header files"Ronak Kanabar
This reverts commit 79503ef515967ffceab7bd2a16a381e6a02c3d30. The Intel FSP repository at https://github.com/intel/FSP.git currently lacks the Client ADL-N headers. The existing coreboot code references the "IoT/AlderLakeN/" directory for these headers, but it is missing the crucial FspProducerDataHeader.h file. Without this header, the ADL-N platform is unable to utilize the appropriate MRC version needed for updating MRC caches. This patch aims to restore the necessary FSP headers for the ADL-N platform within the vendorcode directory. Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-03tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n)Elyes Haouas
Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03mb/razer/blade_stealth_kbl: Add H3Q variantReagan Bohan
The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U variant, as originally committed, with the SKU number RZ09-01962, also known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963 and RZ09-01964, known as the Mid 2017 model. This commit adds support for the H3Q model. With respect to coreboot, there are few known differences: 1. Only the H2U has TPM. 2. The USB ports are different. 3. The screen size (and therefore VBIOS Table) is different. 4. The hda_verb is very slightly different. 5. The gpio is different. Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-03soc/intel/meteorlake: Enable USB2 port reset message on Type-C portsJeremy Soller
Apply commit c6b65c1a811e ("soc/intel/alderlake: Enable USB2 port reset message on Type-C ports") to Meteor Lake. This change is added to address the issue of USB3 ports downgrading to high speed during low power modes and not returning back to super speed. The patch enables port reset event on USB2 ports. This event is is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82730 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03mb/system76/rpl: Fix addw4 Kconfig nameTim Crawford
Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Fixes: 29f1b791270b ("mb/system76/rpl: Add Adder WS 4 as a variant") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03mb/system76/rpl: Hook up TAS5825M initTim Crawford
Ensure per-board smart amp init is configured. Fixes speaker output on oryp12. Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd Fixes: 8b9716e2269d ("mb/system76/rpl: Add Oryx Pro 12 as a variant") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-06-03mb/system76: Add SPDX ID to devicetree filesTim Crawford
Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82700 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeMichał Kopeć
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this to 1 is needed to enable HDA audio link. Same exact situation as with Alder Lake in CL 71715. Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-06-03ec/dasharo/ec: Add initial copy of ec/system76/ecMichał Kopeć
Initial commit is a copy of ec/system76/ec from tag v24.02.1 (commit 0a280ff7) with string changes. Dasharo-specific features will be added in subsequent commits, similar to how Librem EC support was added in changes 52390 and 52391. Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03device_tree: Add function to get top of memory from a FDT blobAlper Nebi Yasak
coreboot needs to figure out top of memory to place CBMEM data. On some non-x86 QEMU virtual machines, this is achieved by probing the RAM space to find where the VM starts discarding data since it's not backed by actual RAM. This behaviour seems to have changed on the QEMU side since then, VMs using the "virt" model have started raising exceptions/errors instead of silently discarding data (likely [1] for example) which has previously broken coreboot on these emulation boards. The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt" models and had this issue, which were mostly fixed by using exception handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on 64-bit RISC-V we had to limit probing to 16383 MiB because it can run into MMIO regions otherwise. The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM which doesn't appear to suffer from this issue. Still, the issue can be observed on the ARMv7 "virt" model via a port based on qemu-aarch64. QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the device tree blob it provides for device information (incl. RAM size). Implement functions that parse the device tree blob to find described memory regions and calculate the top of memory in order to use it in mainboard code as an alternative to probing RAM space. ARM64 code initializes CBMEM in romstage where malloc isn't available, so take care to do parsing without unflattening the blob and make the code available in romstage as well. [1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.maydell@linaro.org/T/#u [2] https://review.coreboot.org/c/coreboot/+/34774 [3] https://review.coreboot.org/c/coreboot/+/36486 [4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html [5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80322 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-03Revert "tree: Use Wcalloc-transposed-args command option"Elyes Haouas
This reverts commit b3db3abd6311924930f3250c9f9fc3157fbbf7da. Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it. Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82759 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03lib/device_tree.c: Fix wrong check for FDT validityMaximilian Brune
Obviously one should return NULL if a FDT is not valid an not the other way around. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I77c0e187b841e60965daac17025110181bdd32bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-01tree: Add some SMBIOS_PROCESSOR_FAMILY macrosElyes Haouas
Change-Id: Ibe551a4c83f416ba30326077aa165818cf79c1fd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82648 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-31mainboard/google/rex: Enable Rex64 build configurationSubrata Banik
- Add Rex64 board to Kconfig menu - Enable building for Rex64 with x86_64 support Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel: Fix pointer size mismatch errors in crashlogAppukuttan V K
The crashlog code in intel/common/block and meteorlake soc was casting integer addresses directly to pointer types, which caused compilation errors in x86_64 bit builds. This commit fixes the issue by using uintptr_t for casting integer addresses to pointer types before dereferencing. BUG=b:329034258 TEST=Successfully build Meteor Lake (rex) in both x86_32 and x86_64 modes. Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31mb/google/brya/var/nova: Update USB ports settingKenneth Chan
Update used USB port[2][3](type-a) setting for nova. BUG=b:328711879 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-05-31soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO domainsShuo Liu
For multi-SKU/SoC supports, IIO domain layouts are returned from FSP HOBs. Add _OSC ASL generation utils so that static IIO domain layout definition file per SKU/SoC are not needed any more. The _OSC generation codes is a thin AML generation layer which further invokes \_SB.POSC which is defined in ASL. The ASL handler is able to handle boot-time generated info as parameters while keeps good readability for the ease of maintenance. In this case, firmware granted capabilities are calculated in boot time and passed to ASL handler as parameters. TEST=Build and boot on intel/archercity CRB Change-Id: Ibd3bfa2428725fe593754436d5ed75a3a11b4cdc Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2024-05-31vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guardAppukuttan V K
This commit removes config guard around FSPM_ARCH_UPD from the FspApi.h header file. This change is done to ensure that this header file can be used with both x86_32 and x86_64 architectures and also with different FSP specification versions. The following modifications are made: - Removes PLATFORM_USES_FSP2_X86_32 config guard around FSPM_ARCH_UPD, this was added to isolate the structure from x64 build. This is not really required since the x64 build uses FSP2.4 structures. BUG=b:343428206 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82425 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-31mb/google/trulo: Support OCP fault on A0/1 portsPranava Y N
The devicetree entry and gpio.c updated as per the schematics of Trulo to map the OC fault signals from A0/A1 USB ports. BUG=b:335858378 TEST= Able to build google/trulo Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-31soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 buildsAppukuttan V K
EnableMultiPhaseSiliconInit upd is deprecated and has been removed starting with v2.4 of FSP specification. Multi-phase silicon initialization is mandatory for all FSP implementations compliant to v2.4. The following modifications are made: - In fsp_params.c and silicon_init.c EnableMultiPhaseSiliconInit update is guarded so that it will get included only if FSP2.4 is not selected. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/meteorlake: Tailor FSP Version Selection for ArchitectureSubrata Banik
* Conditionally select FSP 2.4 when x86_64 support is available (HAVE_X86_64_SUPPORT). * Default to FSP 2.3 otherwise. * Adjust default FSP header path to align with architecture. BUG=b:242829490 TEST=Able to build google/rex in both 32-bit and 64-bit mode. Change-Id: Ib77a34c6bf7bca3485a197f109d1550ac3d51cc0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/meteorlake: Enable eSOL without 64-bit supportSubrata Banik
This change allows eSOL to be enabled on production Meteor Lake silicon even when 64-bit support is not present. eSOL support is still TBD for 64-bit FSP hence, skip adding this support for 64-bit build. TEST=Able to build and boot google/rex64 w/o eSOL. Change-Id: I16762e5b74ae0aaa3c28730479a1fd9defc4d93c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82716 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30tree: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> is supposed to chain-include <soc/gpio.h>. Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headersAppukuttan V K
This commit introduces new header files of V3471.91 for the x86_64 architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP 64-bits support and the soc Kconfig file has been updated to select this new header path when FSP2.4 is in use. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30vc/intel/fsp/mtl: Organize FSP headers into x86_32 directoryAppukuttan V K
This commit moves FSP V3471.91 header files for Meteor Lake into a new x86_32 directory to better organize the files based on the architecture. The Kconfig file has been modified accordingly to reflect the new paths of the relocated headers. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-30soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibilityAppukuttan V K
This commit updates the type definitions for FSP parameters in the Meteor Lake platform to ensure compatibility with the FSP2.4 specification, that supports 64-bit builds for the first time and this also ensures that parameter types works for both 32-bit and 64-bit builds. - In fsp_params.c, FSPS_ARCH_UPD macro is changed to FSPS_ARCHx_UPD which supports FSP2.4 and older specifications. Special handling is added for FspEventHandler assignment to handle as the variable type is different in both cases. - In meminit.c, the type for SPD pointers is changed from uint32_t to efi_uintn_t to support both 32-bit and 64-bit builds. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30mb/siemens/mc_ehl5: Remove DDI settings from devicetreeMario Scheithauer
Since this mainboard no longer uses the FSP GOP driver, the DDI port settings are no longer necessary. The GOP driver was used in the initial phase of development where we used Tianocore as payload for some test cases. Finally, this mainboard uses a self-made Linux payload, which does the graphic initialization. BUG=none TEST=Boot into Linux and check if graphic works correctly Change-Id: Ie9e135fbc2627546d6ef95d7d5ff3e9a9222b5d2 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82663 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29mb/system76/rpl: Add Adder WS 4 as a variantTim Crawford
The Adder WS 4 (addw4) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - All USB ports - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Detection of devices in TBT slot on boot Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29mb/system76/rpl: Add Oryx Pro 12 as a variantTim Crawford
The Oryx Pro 12 (oryp12) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: I11cf2dbd1512ebae44e0109bdb78e6eafa027444 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29mb/system76/rpl: darp9: Add SSD RTD3 configsTim Crawford
Some drives block the CPU from reaching C10 during S0ix suspend without the RTD3 configs. Fixes suspend with the following drives: - Kingston KC3000 (SKC3000D/4096G) - Kingston HyperX (SHPM2280P2H/240G) - Solidigm P44 Pro (SSDPFKKW010X7) The following drives continue to work: - Samsung 970 Evo (MZVLB250HAHQ) - WD Black SN770 (WDS250G3X0E) - WD Green SN350 (WDS240G2G0C-00AJM0) - WD Blue SN570 (WDS100T3B0C) Change-Id: Ia369727d0f1aa5ff546cfb5700a63063730e8248 Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-05-29mb/intel/mtlrvp: Enable EC MKBP deviceJay Patel
MKBP device is required for passing events from input sources to AP. Input sources include buttons (power, volume); switches (lid, tablet mode) and sysrq. BUG=b:342227155 TEST=Able to build coreboot for mtlrvp platform and switch tablet mode. Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47 Signed-off-by: Jay Patel <jay2.patel@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82612 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-05-29cpu/x86/pae/pgtbl.c: extract reusable code from memset_pae()Krystian Hebel
Code dealing with PAE can be used outside of memset_pae(). This change extracts creation of identity mapped pagetables to init_pae_pagetables() and mapping of single 2 MiB map to pae_map_2M_page(). Both functions are exported in include/cpu/x86/pae.h to allow use outside of pgtbl.c. MEMSET_PAE_* macros were renamed to PAE_* since they no longer apply only to memset_pae(). Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82249 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29mb/google/nissa/var/sundance: Add WWAN power off sequenceLeo Chou
Sundance support FM101 WWAN, use wwan_power.asl to handle the power off sequence BUG=b:343139385 TEST=Build and boot on sundance Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/pujjoga: Update touchscreen IC settingsRoger Wang
Modify the Goodix touchscreen from new vendor and remove 3 unused touchscreens. According to the information provided by the key-part team. BUG=b:340689681 TEST=Build and check Goodix touchscreen can work. Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/sundance: Update eMMC DLL settingsRoger Wang
Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally. According to Intel provides eMMC DLL delay patch that tuning on each Sundance different eMMC system to modify some system can't boot to OS problem. BUG=b:342057438 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Use Wcalloc-transposed-args command optionElyes Haouas
GCC-14 documentation says "The first argument to calloc is documented to be number of elements in array, while the second argument is size of each element, so calloc(n, sizeof (int)) is preferred over calloc(sizeof(int), n)." Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82658 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <stddef.h>Elyes Haouas
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-28mb/system76/tgl: Update VBTs to version 250Tim Crawford
Commit 4c7e97b26a34 ("Update fsp submodule to upstream master branch") included an update to the VBT from 240 to 250, breaking parsing of existing VBTs. After that commit, the VBT was parsed as (from gaze16-3060-b): [DEBUG] PCI: 00:02.0 init [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32 [INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0xd0000000 [DEBUG] PCI: 00:02.0 init finished in 6 msecs When the expected output is: [DEBUG] PCI: 00:00:02.0 init [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 [INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000 [DEBUG] PCI: 00:00:02.0 init finished in 6 msecs Generate blobs for the new version using Intel Display Configuration Tool (DisCon) v3.3, based on the existing 237 and 240 VBTs. (For our edk2 payload, the UEFI GOP driver was updated to 17.0.1077.) Tested on all affected systems: - darp7 - galp5 - gaze16-3050 - gaze16-3060 - gaze16-3060-b - lemp10 - oryp8 Tested: - Boot splash displays on screen again - Firmware setup menu is rendered, at correct resolution Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Daniel Sutton <daniel@system76.com> Tested-by: Jacob Kauffmann <jacob@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-28mb/google/brox: Add romstage early graphicsSowmya Aralguppe
Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image. This patch enables Sign of Life image during MRC training. BUG=b:335369811 TEST=Able to boot to ChromeOS with SOL image. CPU log: [SPEW ] bootmode is set to: 0 (boot with full config) [0.384818] DP PHY mode status not complete [0.388911] DP PHY mode status not complete [0.393197] DP PHY mode status not complete [0.397484] DP PHY mode status not complete [0.401771] DP PHY mode status not complete [0.406057] DP PHY mode status not complete [0.410345] DP PHY mode status not complete [0.414632] DP PHY mode status not complete [0.418916] DP PHY mode status not complete [0.423203] DP PHY mode status not complete [0.427491] DP PHY mode status not complete [0.431777] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. [DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes) [WARN ] CBFS: 'preram_locales' not found. [ERROR] ux_locales_get_text: preram_locales not found. [DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes) [INFO ] ELOG: NV offset 0xf20000 size 0x4000  elogtool list: 0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088 1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success 3 | 2024-05-10 02:27:09-0700 | System boot | 4 4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled 5 | 2024-05-10 02:27:11-0700 | System Reset 6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5 8 | 2024-05-10 02:27:36-0700 | System boot | 5 9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled 10 | 2024-05-10 02:27:37-0700 | System Reset 11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
2024-05-28tree: Add smbios_processor_typeElyes Haouas
Change-Id: I46f799ad255993ac42dab11b5c1d2608daa52b42 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82645 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28mb/google/trulo: Add initial devicetree.cbSubrata Banik
This patch adds initial PCI device entries into the baseboard devicetree.cb. TEST=Able to build google/trulo. Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28mb/google/trulo: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Trulo variants to override the USB ports as per the target board design. TEST=Able to build google/trulo. Change-Id: I6240e66ed3d1a7198c1a526fdca2483910157235 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28mb/google/trulo: Program EC ranges (host cmd and memory map)Subrata Banik
This patch adds chip config entries for EC host cmd and memory map ranges. TEST=Able to build Google/Trulo. Change-Id: Id4b0f3bba934c8da56b6d7ca8579b46b6cccac28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28soc/intel/xeon_sp: Add PD_TYPE_CLUSTERShuo Liu
Add a new proximity type to represent the sub-NUMA cluster (SNC). This patch adds necessary Xeon-SP common code level support for SNC support. When SNC on, each SNC cluster will have a proximity domain. DIMMs and CPU cores are attached to SNC proximity domains instead of the processor proximity domains. With SNC, there are 3 types of proximity domains, PD_TYPE_PROCESSOR, PD_TYPE_GENERIC_INITIATOR and PD_TYPE_CLUSTER. proximity domain type checks in Xeon-SP codes are updated to correctly handle the adding of the new type. This patch doesn't actually enable SNC. To fully enable SNC, SoC codes need to override soc_get_cluster_count(), soc_set_cpu_node_ id() and memory_to_pd(), and call soc_set_cpu_node_id() in its per-CPU init routine. Change-Id: I32558983780f302ff4893901540a90baebf47add Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-28include/device: Fix IO resource handling covering 0xFFFFShuo Liu
IO resource creation utils taking 'from' and 'to' as parameters use uint16_t for them, where 'to' equals the resource limit plus 1. When a resource is with a limit of 0xFFFF, the value of 'to' will be clipped to 0x0000 by uint16_t. Fix this problem by use uint32_t and checks the effective range to make sure it no larger than UINT16_MAX + 1. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: Ie83045683094d6330c1676809f83acf30175cc90 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-28soc/intel/xeon_sp: Add domain resource window creation utilsShuo Liu
It might be benefical to have utils for domain resource window creation so that the correct IORESOURCE flags used could be guaranteed. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-28tree: Remove unused <stdarg.h>Elyes Haouas
<stdarg.h> header is used to define macros for handling variable argument lists in functions like printf. It does not depend on the string or memory manipulation functions provided by <string.h>. So let follow conventions and include only the necessary headers in each header file. Change-Id: I07ffc65b7feefb8ec4ab8dd268113f9ed8d24685 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82664 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28spd_bin.h: Use same macro for DDR3 and LPDDR3Elyes Haouas
DDR3 and LPDDR3 share the same PART_NUM and PART_LEN. So use the same macro. This is to prepare SPD de-duplication in following patch. Change-Id: Iea824a847b5072b1cbaa38dc38deae1d484d5b16 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28soc/mediatek/mt8188: Decrease OP-TEE image size from 80 MB to 70 MBGavin Liu
The secure buffer shrank from 42 MB to 32 MB, decreasing the total OP-TEE image size from 80 MB to 70 MB. BUG=b:246837563 TEST=emerge-geralt coreboot build coreboot and verify SVP works well Change-Id: I6729e65f83ef994fe59b5bd4ed098e6d3a847695 Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-05-27acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 caseFelix Held
Both acpi_create_madt_sci_override and acpi_sci_int have special handling for the ACPI_NO_PCAT_8259 case, but those cases weren't exactly obvious, so add a comment with the reason for that. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82643 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)Federico Amedeo Izzo
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200 SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - DDR4 RAM (tested with Crucial 16GB 3200MHz CL22) - Automatic FAN control (IT8613E Super I/O) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2 - Windows 10 UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the Super I/O registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64 (Build date and time 11/29/2023 10:57:44) Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor UEFI firmware (see above). The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Patchset 13: Change Super I/O Fan configuration to reduce fan noise Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27mb/google/ovis/var/deku: Set PsysPL2 value to 178WTony Huang
Adjust setting as recommended by power team. Add ramstage.c in Makefile.inc to set psys_pl2_watts in variant_devtree_update(). Also copy CPU power limit values from ovis baseboard. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=FSP debug emerge-ovis coreboot intelfsp check overrides setting [INFO] CPU PsysPL2 = 178 Watts [INFO] Overriding PsysPL2 (178) [INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-27mb/google/ovis/var/deku: Increase TDP PL1 value from 28 W to 33 WTony Huang
Adjust settings as recommended by thermal team. Set PL1 max value tdp_pl1_override from 28W to 33W. PL2, PL4 remain the same as CPU default. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27mb/google/ovis/var/deku: Set TCC_offset to 5Tony Huang
Adjust settings as recommended by thermal team. Set tcc_offset value to 5 in devicetree. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27mb/google/rex/var/deku: Update DPTF parametersTony Huang
Adjust settings as recommended by thermal team. Update DPTF parameters based on b:308704811#comment4. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27security/memory_clear: fix wrong size of reserved memory rangeKrystian Hebel
The code used to reserve MEMSET_PAE_PGTL_SIZE (20 KiB) for page used for clearing the memory above 4 GiB that was assumed to be 2 MiB page. memset_pae() checks only the alignment and not the size of this region, so no error was reported by it. In most cases this reserved memory in 2-4 MiB range, and because this range isn't usually used by coreboot (architectural stuff is located in lower 1 MiB, coreboot tables and ramstage are close to TOLUM and payload isn't yet loaded when the broken code is executed), it never caused any problems. Change MEMSET_PAE_PGTL_SIZE to MEMSET_PAE_VMEM_SIZE and fix wrong macro definition to reserve properly sized region. Change-Id: I0df15b0d1767196fe70be14d94428ccdf8dbd5d3 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-27acpi/acpi_apic: use generic MADT IRQ override function for SCI overrideFelix Held
Call acpi_create_madt_irqoverride from acpi_create_madt_sci_override with the correct parameters instead or re-implementing the same functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e6ee0eed837c2d46da62092b7cc5669dc177d8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/82644 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-05-25acpi: add and use defines for LAPIC feature flagsFelix Held
Both the processor local APIC structure and the processor local x2APIC structure use the same flag bit definitions. ACPI spec 6.4 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8101c2ea874c8b12b130dbe9a0a7e0f0d94adffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-25acpi: introduce and use ACPI_MADT_PCAT_COMPAT defineFelix Held
The multiple APIC flags table from the ACPI specification version 6.4 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I36f67ca21465bc8753bb36896ee05669de6de333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82640 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-25arch/arm64: Implement initial set of SMBIOS tablesBenjamin Doron
Implement the two architectural tables: processor and cache. Note that SoC/board code should override core-thread count and, for spec-compliance, create CBMEM_ID_MEMINFO. Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-05-25arch/arm64: Support calling a trusted monitorBenjamin Doron
Implement support for generating an SMC to call a trusted monitor. Some functions are provided to read the SoC ID from the monitor, if supported. Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78284 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.hShuo Liu
get_cxl_mode() is the interface for CXL mode config check used by SoC codes. It could be implemented by mechanisms outside of the SoC codes, e.g. board codes or OCP VPD driver. Move the interface declaration out of soc/util.h to a dedicated header, a.k.a., soc/config.h, so that the implementation codes do not need to include soc/util.h where there are lots of irrelevant definitions. Future SoC config check interfaces could be added to soc/config.h as well. The default weak implementation is moved out of util.c to config.c as well. TEST=Build and boot on intel/archercity CRB Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24device/pci_rom: handle non-remapped VGA_BIOS_IDFelix Held
While the SoC-level defaults for VGA_BIOS_ID are the expected correctly remapped PCI VID/PID of the GPU which matches the PCI VID/DID inside the VBIOS file, some mainboards override the VGA_BIOS_ID setting to the non-remapped PCI ID. This resulted in coreboot not finding the VBIOS file after commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"). The proper solution would be to not override this SoC-level config in neither the mainboard code nor some external config file. This however requires adding/using some mechanism to tell SeaBIOS which VBIOS image to use for the GPU device. Once this is implemented, the SoC default for VGA_BIOS_ID shouldn't be overridden any more and this patch can be reverted again. This sort-of reverts parts of commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"), but it still tries to find the VBIOS image with the expected remapped PCI ID and only adds trying the non-remapped PCI ID as a fallback when the file with the remapped PCI ID doesn't exist and prints a notice in that case. Before the patch referenced above, using the correct remapped PCI VID/DID resulted in a warning about the CBFS file with the non-remapped name not being found, but first checking the remapped version solves that problem. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-24mb/google/trulo: Refactor gpio pad configurationSubrata Banik
This patch tries to simplify the baseboard/variant GPIO programming for Google/Trulo. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant) TEST=Able to build google/orisa. Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-24mb/google/nissa: Fix potential null pointer dereferenceSubrata Banik
* Introduce a null check before calling `gpio_padbased_override` in `variant_configure_pads`. * This prevents potential errors in cases where the `variant_gpio_override_table` function returns a null pointer, indicating that there are no override pads to configure. BUG=b:334826281 TEST=Able to avoid hang incase there is no GPIO override. Change-Id: I733210a08091b37eda6e6b0d6924aafd5e7e6280 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82628 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23device: drop unnecessary CHECK_REV_IN_OPROM_NAME optionFelix Held
The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the problem of the PCI VID/DID combination of the Picasso iGPU not being sufficient information to know which VGA BIOS file to run, so a new function that additionally checks the PCI revision of that device was introduced. Later it turned out that there might be a case where even that isn't sufficient, so the soc_is_raven2() function is used in the remap function to always use the correct VBIOS file. Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME Kconfig option, so all other SoCs are unaffected by this change. Now that we use the VBIOS images with only the PCI VID and DID in the CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID as the iGPU in CBFS and we don't need the workaround to add a third VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects. This will result in SeaBIOS now running the VBIOS that has the same PCI VID/DID as the hardware which will be the wrong one in the RV2 silicon showing the PCO silicon PCI VID/DID, but that was also the case with the VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one of the two possible images during build time and hoped that it was the correct one for that actual hardware. The only board where this patch might cause a regression compared to the old behavior is the AMD Cereme reference board with Pollock APU, but I'm not even sure if any coreboot developer still has one of those boards, so I'm willing to accept that. To properly solve the problem with SeaBIOS using the correct VBIOS file in all cases, we'd need to generate that info during coreboot runtime and somehow pass it to SeaBIOS, but that's out of scope for this patch. TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS and Ubuntu still works. Booting Windows 10 via the pre-built EDK2 payload that I'm using also resulted in the display output working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6de533c536044698d85404427719b8f534870fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82598 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23soc/intel/xeon_sp/gnr/soc_iio: Remove unused <string.h>Elyes Haouas
Change-Id: I8d4500edaa0739921831a3b04131046599c35a87 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-23mb/google/brox/var/brox: Remove mux references from typec portPrashant Malani
The Type-C kernel driver no longer programs the AP mux, as of https://review.coreboot.org/c/coreboot/+/82077. So remove device references to the TCSS Mux control device from the Type-C port driver. This eliminates the following kernel error which was observed as a result of the kernel trying to program muxes it no longer has control over: [ 4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95 [ 4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95 BUG=b:341331428 TEST=Run system reboot; configure mux kernel errors no longer seen. Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/amd/birman/display_card_type.h: add missing includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5208ceeec17051e7849263a4caa0838efd59c044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-23mb/amd/birman/display_card_type.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf4478814e672fb8cfae5ffc4fa89c475f5bb0b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82607 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23soc/amd/phoenix/chip_opensil.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iba17d44772333ed59e3fdde1443a1862bae8e32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/82606 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-23mb/google/brya: Add romstage early graphics for nissaRonak Kanabar
1) Add all changes needed for early graphics 2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa The InnoLux (N156HCN-EBA C7) panel is used for the device tree. BUG=b:296433986 TEST=On-screen text message seen during MRC training on Craask Logs: [NOTE ] MRC: no data in 'RW_MRC_CACHE' [SPEW ] bootmode is set to: 0 [0.171409] DP PHY mode status not complete [0.175509] DP PHY mode status not complete [0.179799] DP PHY mode status not complete [0.184087] DP PHY mode status not complete [0.188376] DP PHY mode status not complete [0.192665] DP PHY mode status not complete [0.196954] DP PHY mode status not complete [0.201243] DP PHY mode status not complete [0.205532] DP PHY mode status not complete [0.209821] DP PHY mode status not complete [0.214110] DP PHY mode status not complete [0.218397] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 11:39:14 +0000