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authorSubrata Banik <subratabanik@google.com>2024-05-25 17:53:11 +0000
committerFelix Held <felix-coreboot@felixheld.de>2024-05-28 13:17:27 +0000
commit23e3ea889f62d0052ac8ec4815937344e60cb213 (patch)
tree5aac6b89eb48ce46a207d1e101caa58ced0ab94b /src
parente75148cd13e68338f7323c932f512a01e59ef6b7 (diff)
mb/google/trulo: Add initial devicetree.cb
This patch adds initial PCI device entries into the baseboard devicetree.cb. TEST=Able to build google/trulo. Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index 3e77896fdd..9e6378f6e7 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -41,5 +41,17 @@ chip soc/intel/alderlake
device domain 0 on
+ device ref igpu on end
+ device ref dtt on end
+ device ref tcss_xhci on end
+ device ref xhci on end
+ device ref shared_sram on end
+ device ref heci1 on end
+ device ref uart0 on end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
end
end