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2024-07-25soc/amd/common/psp_gen2: use MMIO access againFelix Held
Now that we have a get_psp_mmio_base function that will work on all SoCs that use the psp_gen2 code, we can move back to accessing the PSP registers via their MMIO mapping. This sort-of reverts commit 198cc26e4951 ("soc/amd/common/block/psp/psp_gen2: use SMN access to PSP"). When doing SMN accesses from the SMI handler after the OS has taken over ownership of the platform, there's the possibility to cause trouble by clobbering the SMN access index register from SMM. So that should be either avoided completely or the SMI code needs to save and restore the original contents of the SMN index register. The PSP MMIO base will be set up by the FSP before the resource allocation in coreboot and be treated like a fixed resource by the allocator. The first SMI where corresponding handler calls 'get_psp_mmio_base' happens when ramstage triggers the APM_CNT_SMMINFO SMI right after mpinit which happens after the resource allocation. So the PSP MMIO base address is expected to be configured and so the 'get_psp_mmio_base' function will cache the base address and won't need to do any SMN access in subsequent calls that might happen after the OS has take over control. This isn't currently an issue, since the only PSP mailbox command from the SMI handler after coreboot is done and the OS has taken over will be during the S3/S4/S5 entry, and this will be triggered by the OS as the last step after it is done with all its preparations for suspend/ shutdown. There will however be future patches that add SMI-handlers which can send PSP mailbox commands during OS runtime, and so we have to make sure we don't clobber the SMN index register. TEST=PSP mailbox commands are still sent correctly on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83448 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25soc/amd/common/psp_gen2: return status from soc_read_c2p38Felix Held
This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/ psp_gen2: simplify soc_read_c2p38") and is done as a preparation to switch back to using the MMIO access to the PSP mailbox registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25soc/amd/common/block/psp_gen2: add get_psp_mmio_baseFelix Held
Add get_psp_mmio_base which reads the PSP MMIO base address from the hardware registers. Since this function will not only be called in ramstage, but also in SMM, we can't just look for the specific domain resource consumer like it is done for the IOAPICs in the northbridge, but have to get this base address from the registers. In order to limit the performance impact of this, the base address gets cached in a static variable if an enabled PSP MMIO base register is found. We expect that this register is locked when it was configured and enabled; if we run into the unexpected case that the PSP MMIO register is enabled, but not locked, set the lock bit of the corresponding base address register to be sure that it won't change until the next reset and that the hardware value can't be different than the cached value. This is a preparation to move back to using MMIO access to the PSP registers and will also enable cases that require the use of the MMIO mapping of the PSP registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/83446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25soc/amd: add SoC-specific root_complex.c to SMMFelix Held
The PSP code introduced in a following patch needs both SoC-specific functions get_iohc_info and get_iohc_non_pci_mmio_regs to also be available in SMM, so add those compilation units to the corresponding target. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e32084b45f07131c80b642bc73d865fc57688a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-07-25soc/amd/*/root_complex: introduce and use domain_iohc_info structFelix Held
Instead of implementing the functions get_iohc_misc_smn_base and get_iohc_fabric_id in the SoC code, move those functions to the common AMD code, and implement get_iohc_info in the SoC code that returns a pointer to and the size of a SoC-specific array of domain_iohc_info structs that contains the info needed by the common code instead. This allows to iterate over the domain_iohc_info structs which will be used in a later patch to find the PSP MMIO base address in both ramstage and smm. TEST=Mandolin still boots and all non-PCI MIO resources are still reported to the resource allocator Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/83443 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25acpi,soc: use is_domain0 functionFelix Held
No need to open-code this when we have a function for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83643 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-25device: move is_domain0 and is_dev_on_domain0 to common codeFelix Held
Move is_domain0 and is_dev_on_domain0 from the Intel Xeon SP code to the common coreboot code so that it can be used elsewhere in coreboot too, and while moving also implement it as functions instead of macros which is more in line with the rest of helper functions in that new file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I954251ebc82802c77bf897dfa2db54aa10bc5ac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83642 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25mb/protectli/vault_[adl_p,bsw]/Kconfig: drop unneeded MAINBOARD_VENDORFelix Held
MAINBOARD_VENDOR is already provided by the Kconfig file on the vendor level, so there's no need to redefine it to the same value at the mainboard level. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icfcbcec005fadb8eaf1b8f90e1d71b3c6ee32088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83640 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-25soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOSYu-Ping Wu
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver accesses VBNV via Bank 0, the bit must be cleared before we can save VBNV to CMOS in verstage. Usually there's no problem with that, because the Register A is configured in cmos_init() in ramstage. However, if CMOS has lost power, then in the first boot after that, the bit may contain arbitrary data in verstage. If that bit happens to be 1, then CMOS writes in verstage will fail. To fix the problem, define vbnv_platform_init_cmos() to call cmos_init(0), which will configure the Register A and therefore allow saving VBNV to CMOS in verstage. [1] 48751_16h_bkdg.pdf BUG=b:346716300 TEST=CMOS writes succeeded in verstage after battery cutoff BRANCH=skyrim Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83495 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25mb/google/nissa/var/riven: Add Fn key scancodeDavid Wu
The Fn key on riven emits a scancode of 94 (0x5e). BUG=b:345231373 TEST=Flash riven, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Iddedd08fc50e8e8e369ce3d73edf0f3077867e87 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83614 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-25ec/starlabs/merlin: Improve accuracy of RSOCSean Rhodes
Multiply before dividing to improve accuracy of the result. Change-Id: I974cad3af4e1f86ae58e90c68db463fc436223af Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83619 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25mb/google/brya/var/trulo: Configure GPIO pins for ramstageSubrata Banik
This patch configures GPIO pins as required for booting the Trulo device from ramstage. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7b540416083a923ba4d2e52aa8edafb4bfb9ac0e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-25soc/amd/psp_verstage: Add -Oz flag for clangYu-Ping Wu
When we tried to add CMOS support to PSP verstage (CB:83495), the clang builds failed on boards with cezanne SoC (such as Guybrush), due to over-sized verstage. On the other hand, there is no such problem for gcc builds on the same boards. Building PSP verstage by clang generates much larger verstage size (81K) compared with using gcc (67K). To unblock adding features to verstage, temporarily enable -Oz for clang builds. Change-Id: I033458556986ade88fb8e68499b632deae4dd419 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-24mb/google/volteer/{delbin,drobit}: Use alias name for DPTF PCI deviceFelix Singer
Change-Id: If514ee7c1174d13b8ca8eb7fd20359e0730a8893 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83525 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24mb/protectli/vault_cml: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: Ie485684747efccb8fb0ab87f10694c52a98f3c88 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83455 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24mb/google/dedede/var/awasuki: Initialise overridetreeWeimin Wu
Initialise overridetree based on the schematics revision 20240715. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-24soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCsJincheng Li
TEST=Build and boot on archercity CRB No changes in boot log and 'dmidecode' result under centos TEST=Build and boot on avenuecity CRB It will add DMI type 16,17,19,20 Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-24arch/x86/Makefile.mk: Remove obsolete romcc referenceArthur Heymans
No assembly.inc file is being generated by romcc anymore. The -I. was only used in a single place that can use the common -Isrc instead. Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83563 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24arch/x86: Build all stages using the same functionArthur Heymans
There is no difference in how early and later stages are linked so rename the same function. Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-07-24arch/x86: Link ramstage in one stepArthur Heymans
We only use the bfd linker currently but partial linking is not supported by other linkers and is also a problem for LTO. Change-Id: I3b23d86e604229262d7c762e23bb963a0e944b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71910 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23mb/google/dedede/var/galtic: Group fw_config fields togetherMatt DeVillier
No need to have separate sections, and will be cleaner when adding another section in a subsequent patch. Change-Id: I4ad6be9dd67b5adbc9c5b0fcab51ce0c54351173 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-23mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670Michał Żygowski
It is a new incoming Protectli product based on Alder Lake-P SoC. More details and documentation will be added later. TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670. Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80501 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23mb/google/rauru: Add MediaTek MT8196 reference boardJarried Lin
Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83573 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoCJarried Lin
Add new folder and basic drivers for Mediatek SoC 'MT8196'. Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for MT8196 SPEC detail. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-07-23mb/google/brya/var/xol: Limit power limits for low/no battery caseSeunghwan Kim
Xol has a shutdown issue on our reliability test environment: - High temperature - No battery condition It needs to have margin for the PL2 and PL4 values from the adapter power, this will limit the PL2/PL4 values up to 30W/40W for xol's 45W power adapter. The new values are confirmed by our power team. BUG=b:353395811 BRANCH=brya TEST=built and verified MSR PL2/PL4 values. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:18000000 <= MSR PL1 (18W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) [When connected 60W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:60000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 [When connected 45W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:45000000 constraint_2_power_limit_uw:45000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-23drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMDYu-Ping Wu
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A is bank selection. Since the MC146818 driver accesses VBNV via Bank 0, the value set in cmos_init() must not contain that bit. To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add an static assertion about the bank selection for AMD. Note that the kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157 BUG=b:346716300 TEST=none BRANCH=skyrim Change-Id: I6122201914c40604f86dcca6025b55c595ef609e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-22lib/smbios: Create SMBIOS type 4 entryJincheng Li
One smbios type 4 should be provided for each CPU instance. Create SMBIOS type 4 entry according to socket number, with a default value of 1. TEST=Boot on intel/archercity CRB No changes in boot log and 'dmidecode' result under centos Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83331 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INTSeunghwan Kim
If user continues to use the touchpad for over 3 minutes on Xol, the pointer movement is stuttering. Touchpad I2C transaction should appear during the interrupt signal level is low, but we could see some more I2C transaction after the interrupt signal(GPP_F14) went to high. We found experimentally that changing the interrupt type to GPIO_INT from APIC_IRQ improved this issue. We are still investigating, would like to apply this change first for Xol's dogfooding. BUG=b:350609957 BRANCH=brya TEST=built and verified there's no stuttering issue on touchpad movement Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-22mb/google/brya/var/trulo: Configure early and romstage GPIOsSubrata Banik
This change adds early and romstage GPIO configurations for the trulo variant, including: Early GPIOs: - GSC (Google Security Controller) - WP (Write Protect) - UART0 (for serial debug) Romstage GPIOs: - Touch Screen early power sequencing CrOS GPIOs: - CROS_GPIO_VIRTUAL - GPIO_PCH_WP BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic1b84f61ef62ddbadc2a45758fb3fce90fce0e88 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83568 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add fw_config for PDCSubrata Banik
This patch adds FW Config to the device tree for choosing between the discrete PD chip. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I0a8fb0225edecb063dede31efaec6f2502476977 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add PnP descriptionsSubrata Banik
This patch adds power related entries (FIVR and policy to control lower power c-state transitioning) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-22mb/google/brya/var/trulo: Add Thermal descriptionsSubrata Banik
This patch adds Thermal related entries (like, TDP, TCC and enabling DPTF config with required sensor configuration) to the devicetree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83565 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-22soc/mediatek: Move memmory macros into MediaTek common directoryJarried Lin
To reduce duplicate memmory macros of MediaTek SoCs, move the header file to a common directory. TEST=Build geralt pass BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/mediatek: Move symbols.h into MediaTek common directoryJarried Lin
To reduce duplicate region declarations of MediaTek SoCs, move the header file to a common directory. BUG=b:317009620 TEST=Build geralt pass. Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83570 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/intel/xeon_sp/spr: Return updated resource index for create_ioat_domainShuo Liu
create_ioat_domain creates the domain device with a number of resources. Return the updated resource index so that the updated index could be used as the starting index for additional resource creation outside create_ioat_domain. TEST=Build and boot on intel/archercity CRB Change-Id: I9e719ae8407c7f31f88dbb407f003e2ded8f0faf Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-22vc/google/chromeos: Add configurable compression for logo file in cbfsAshish Kumar Mishra
This patch enables LZMA or LZ4 compression algorithm for the logo cbfs file based on BMP_LOGO_COMPRESS_LZMA or BMP_LOGO_COMPRESS_LZ4 Kconfig. Logo cbfs file is compressed based on CBFS_COMPRESS_FLAG, by default. Based on logo file content and target platform, enabling LZ4 could save significant boot time, with increase in file size. For brox: cb_logo LZ4 is +1265 bytes than LZMA, saves ~0.760ms in decomp. cb_plus_logo LZ4 is +2011 bytes than LZMA, saves ~0.880ms in decomp. BUG=b:337330958 TEST=Able to boot brox and verified firmware splash screen display with LZMA and LZ4 compression. Change-Id: I57fbd0d3a39eaba3fb9d61e7a3fb5eeb44e3a839 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83420 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/intel/alderlake/tcss: Add definition of IOM_READY bitMichał Żygowski
Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1 register. Needed by Protectli VP66XX boards to poll for this bit for about 2 seconds before FSP Silicon Init to have USB functionality. ME is supposed to start fetching and executing the TCSS IPs FW right after DRAM Init Done message, which happens after MRC. For most platforms the time interval between the end of MemoryInit and start of SiliconInit is enough for IOM_READY to get set. TEST=Poll the IOM_READY bit on VP66XX platform and observe the TCSS XHCI is up in lspci. Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83356 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/system76/mtl: Add Darter Pro 10Tim Crawford
The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board. There are 2 variants to differentiate them as they have different keyboards and so use different EC firmware. - darp10: 16" model with 102 key keyboard - darp10-b: 14" model with 83 key keyboard Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82609 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/amd/common/root_complex: move IOHC_MMIO_EN definition to headerFelix Held
To be able to use the IOHC_MMIO_EN define in other compilation units, move the define to the corresponding header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If88950418406d1709ed95b3d05f7e6ad66438f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-07-22mb/google/brya: change NAU8825 config to fix headset button detectionTerry Cheong
Brya/brask devices using NAU88L25 are not recognizing headset buttons correctly. The reason is we are using wrong reference voltage of MICBIAS. Use VDDA instead. BUG=b:352215240 TEST=test with 3.5mm headset with buttons on volume up/down and pause Change-Id: I0619021c6fd0a196c318aee58e07dc4149f1d64e Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/variants/orisa: Change board strap memory configRishika Raj
Reorder GPIO pin mapping as per platform documentation: * GPIO_MEM_CONFIG_0 -> GPP_E2 * GPIO_MEM_CONFIG_1 -> GPP_E1 * GPIO_MEM_CONFIG_2 -> GPP_E12 * GPIO_MEM_CONFIG_3 -> NC BUG=None TEST=emerge-nissa coreboot Change-Id: I4e979686833095a904b114500dc1142def583afa Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83549 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-22mb/google/brya/var/trulo: Add Audio descriptionsSubrata Banik
This patch adds descriptions for Audio device (Speaker, Jack and Mic) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ied531dde856fb7c9a410b5667843c9be759cfc8f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add eMMC descriptionsSubrata Banik
This patch adds descriptions for eMMC device (supported mode and DLL tuning) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I8f1310313b8114731aa417610f245f94c8978ac0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add fw_config probe for storage devicesSubrata Banik
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree, to avoid suspend(s0ix) fail issue. 3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config is enabled. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ifdaa0bf35413981327097c260ab47e757f697e37 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add CNVi descriptionsSubrata Banik
This patch adds descriptions for CNVi WiFi and BT device to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7396917ca7875dcbe1d35a371cc450a9e070b18d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add LSIO descriptionsSubrata Banik
This patch adds descriptions for Low Speed I/O (I2Cx, GSPIx, UARTx) to the device tree. It also includes entries that will generate ACPI code at runtime with LSIO end-point device. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83550 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add TCSS port descriptionsSubrata Banik
This patch adds descriptions for TCSS port, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. Additionally, implement the TCSS PMC MUX programming. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add USB2/3 port descriptionsSubrata Banik
This patch adds descriptions for USB2/3 ports, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/rex/variants/screebo: Generate RAM IDsKun Liu
Generate 3 Samsung RAM IDs K3KL9L90CM-MGCT Samsung K3KL6L60GM-MGCT Samsung K3KL8L80CM-MGCT Samsung BUG=b:331539447,b:333145301,b:333220620 TEST=Run part_id_gen tool without any errors Change-Id: I4ba0fb409015c24446b2ae8e224fbce3910715e3 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83501 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled settingFelix Singer
Change-Id: I6155ec45408dca83573c86e6db1ead5a82a0d77a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-21mb/google/brya/var/trulo: Add minimal devicetree entries to bootSubrata Banik
This patch adds minimal device entries and chip configs for Trulo overridetree.cb to boot. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83546 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Centralize EC configuration in trulo baseboardSubrata Banik
This change moves the EC configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83544 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Centralize GPIO configuration in trulo baseboardSubrata Banik
This change moves the GPIO configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variantSubrata Banik
This change enables SKIP_RAM_ID_STRAPS for the TRULO board variant as this board design won't stuff MEM strap GPIO hence, sets the static SPD ID to 0 for the MT62F512M32D2DR-031 DRAM part. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-21mb/google/brya/var/trulo: Populate DRAM configuration parametersSubrata Banik
This patch adds key DRAM configuration parameters as below: - Rcomp - DQ byte map - DQS CPU<>DRAM map - ECT - CCC Mapping - SPD Index Source: Trulo Schematics Rev0.5 (dated June'24) BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-21mb/google/brya/var/trulo: Add LPDDR5 DRAM (MT62F512M32D2DR-031)Subrata Banik
This patch adds Micron Technology LPDDR5 DRAM (part: MT62F512M32D2DR-031) for Trulo. Make use of spd_tools to generate SPD file after following the below steps: 1. make -C util/spd_tools 2. ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt Output files are: 1. dram_id.generated.txt 2. Makefile.mk BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Id35f6b57b716375abb66db187413f0f82361d962 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83539 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19mb/google/dedede/var/awasuki: Add initial GPIOs configTongtong Pan
Configure GPIOs according to schematics revision 20240712. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72 Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83449 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-07-19mb/google/dedede/var/awasuki: Generate 3 RAM IDsTongtong Pan
Vendor DRAM Part Name Type SAMSUNG K4U6E3S4AB-MGCL LP4X SAMSUNG K4UBE3D4AB-MGCL LP4X MICRON MT53E1G32D2NP-046 WT:B LP4X BUG=b:351968527 TEST=Run part_id_gen tool without any errors Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83427 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-19mb/google/dedede: Create awasuki variantTongtong Pan
Create the awasuki variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:351968527 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_AWASUKI Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0 Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-19superio/ite: Enable common driver for GPIO and LED configurationMichał Żygowski
Enables the driver for ITE SIOs supporting the GPIO register layout (confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs with unavailable datasheets are unmodified). Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM and must then provide the number of GPIO sets specific to a chip via SUPERIO_ITE_COMMON_NUM_GPIO_SETS. Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-19superio/ite/common: Add common driver for GPIO and LED configurationMichał Żygowski
Add a generic driver to configure GPIOs and LEDs on common ITE SuperIOs. The driver supports most ITE SuperIOs, except Embedded Controllers. The driver allows configuring every GPIO property with pin granularity. Verified against datasheets of all ITE SIOs currently supported by coreboot, except IT8721F (assumed to be the same as IT8720F), IT8623E and IT8629E. Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83355 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-19arch/x86: Decouple socket type from SoC typeJincheng Li
Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83330 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-07-19cpu/intel: Add socket typesJincheng Li
Add socket types for LGA1700, LGA3647_1, LGA4189, LGA4677. Select the socket type for different boards. For the socket types which are not defined in SMBIOS type4, CPU_INTEL_SOCKET_OTHER could be used. Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83329 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for CNViSubrata Banik
This patch adds new CNVi PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CNVi driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused BT PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I7d80403b87537aea41ff48ff6d274180577f1ac6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83520 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Remove unused Intel UFS device IDsSubrata Banik
This patch removes the PCI device IDs for Intel LNL and PTL UFS devices from `pci_ids.h` as they appear to be unused in the codebase. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ic795dd2e83c361a2aa04267d4663cf6bb9a755e2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83519 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XDCISubrata Banik
This patch adds new XDCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XDCI driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused TCSS XDCI PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I51196401904e2402ac7669fa852a541bb7c2d453 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83518 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for CSE0Subrata Banik
This patch adds new CSE0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CSE0 driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused CSE1-3 PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for AudioSubrata Banik
This patch adds new Audio (HDA/DSP) PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the Audio driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I3c9e420a6ae19d00fb5510c99d4c219dc43ad3c0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83516 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SRAMSubrata Banik
This patch adds new SRAM PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SRAM driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ib6d62dad59965258dab453533dface9c359de586 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83515 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for P2SBxSubrata Banik
This patch adds new P2SBx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the P2SBx driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie1c36bc1c014bb1e219afe0cafb6c9941f253b0c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XHCI/TCSS XHCISubrata Banik
This patch adds new XHCI/TCSS XHCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XHCI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5ae8f493374087a5e684e0a04486cd64cea6f335 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83513 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SMBUSSubrata Banik
This patch adds new SMBUS PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SMBUS driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I4b8b59cf4e005f0e17a25d0fbe761404dab432b3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83512 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIxSubrata Banik
This patch adds new Fast-SPI and GSPIx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SPI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5c7c0be6f219c93d4520494857d31ce1cf939f36 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83511 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for UARTxSubrata Banik
This patch adds new UARTx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the UART driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I384a753f08ae5a752cef6009d07104e8ff4b4a6e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for I2CxSubrata Banik
This patch adds new I2Cx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the I2C driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I79ba0b563146d658521cdd40aabb3ee882f4d187 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83509 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for PMCSubrata Banik
This patch adds new PMC PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the PMC driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Iae468fdace2d9cfd532957e4f3c55b89b96a52a0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83508 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for PCIeSubrata Banik
This patch adds new PCIe Root Port PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the PCIe driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5913c6ac0a4766c14f23954be1e885d45f69d36a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83507 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for eSPI/LPCSubrata Banik
This patch adds new eSPI/LPC PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the LPC driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie9f0ea9536e2f73c2258e9e12b510d21212248ea Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for ISHSubrata Banik
This patch adds new ISH PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the ISH driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I280cfdb50e8d453e957cb4bccff3a7ee2fb3bd10 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83505 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for DID2Subrata Banik
This patch adds new DID2 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the graphics driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Iab499070c87e020e36901b4ea453a1893bd16ea0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83491 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for DID0Subrata Banik
This patch adds new DID0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the System Agent driver's `systemagent_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie4d77eb489e16d18b996fdda3216e1275083d7e7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83490 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19security/vboot: Introduce vbnv_platform_init_cmos()Yu-Ping Wu
Most x86 platforms use CMOS as the vboot nvdata (VBNV) backend storage. On some platforms such as AMD, certain CMOS registers must be configured before accessing the CMOS RAM which contains VBNV. More precisely, according to AMD's spec [1], the bit 4 of Register A of CMOS is bank selection. Since VBNV is accessed via bank 0 (see the MC146818 driver), the bit must be cleared before the VBNV can be successfully written to CMOS. Saving VBNV to CMOS may fail in verstage, if CMOS has lost power. In that case, all the CMOS registers would contain garbage data. Therefore, for AMD platforms the bit must be cleared in verstage, prior to the first save_vbnv_cmos() call. Introduce vbnv_platform_init_cmos(), which is no-op by default, and can be defined per platform. The function will be called from vbnv_init() if VBOOT_VBNV_CMOS. [1] 48751_16h_bkdg.pdf BUG=b:346716300 TEST=none BRANCH=skyrim Change-Id: Ic899a827bd6bb8ab1473f8c6c03b9fde96ea6823 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83494 Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18tgl,adl,rpl mainboards: Drop superfluous cpu_cluster deviceFelix Singer
The cpu_cluster device is defined in the chipset devicetree. So drop it from the mainboards. Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83523 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/tigerlake: Add cpu_cluster device to PCH-H devicetreeFelix Singer
Change-Id: I30a98ae4989edc97d56d2b538930b3c67565d9dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-07-18mb/google/nissa/var/glassway: Add WIFI_SAR_ID_1Daniel_Peng
Set "option WIFI_SAR_ID_1 1" for WIFI_SAR_ID field in fw_config. BUG=b:347108861 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I179dad5eeabc1d84aa0a2de5359be5848a2ecc39 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83478 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18drivers/pc80/rtc/mc146818rtc: Use macros for CMOS addressesYu-Ping Wu
Replace integer literals with macros for CMOS addresses for readability. Change-Id: I454662c90fabb41af864728febdefa57f5ff2cb2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-18soc/intel/meteorlake: Remove p2sb.c from bootblock buildSubrata Banik
This patch removes `p2sb.c` from the bootblock build for the Meteor Lake platform. BUG=none TEST=Builds successfully for google/rex. Change-Id: Ib2beeee68bb20568888d4b555c2fa82e0bf0fd3c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-18soc/intel/tigerlake: Switch to common eSPI headerSubrata Banik
This patch updates Tiger Lake code to use the common eSPI header file (`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for google/volteer. Change-Id: I01eca0ab132b1788c4633d0e214d4dfde25f5b98 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83488 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/meteorlake: Switch to common eSPI headerSubrata Banik
This patch updates Meteor Lake code to use the common eSPI header file(`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for google/rex. Change-Id: Ibb37413bb6c925650f55b0dcf70e7483bf257888 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/jasperlake: Switch to common eSPI headerSubrata Banik
This patch updates Jasper Lake code to use the common eSPI header file (`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for google/dedede. Change-Id: I93dcd26588111d848be1580220945687890ef3b8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/elkhartlake: Switch to common eSPI headerSubrata Banik
This patch updates Elkhart Lake code to use the common eSPI header file(`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for Intel Elkhartlake platform. Change-Id: Iaef308ad1c8ecfb11448e75f39285a2170bbc49c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83485 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/alderlake: Switch to common eSPI headerSubrata Banik
This patch updates Alder Lake code to use the common eSPI header file (`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for google/redrix. Change-Id: Ib4452547325042de48ee4fca3d3910a031b56b64 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83484 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/cmn/pch: Consolidate eSPI.h into IA common codeSubrata Banik
This patch moves the SoC-specific `eSPI.h` file into the IA common code to promote code reuse and reduce duplication across different SoC generations. TEST=Builds successfully for google/rex. Change-Id: Icb09421eec45c1ef8ab50252543b000078f18b21 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/meteorlake: Use common CAR API for cache reportingSubrata Banik
Replace the SoC-specific `report_cache_info()` function with the common `car_report_cache_info()` API from `car_lib`. This promotes code reuse and reduces SoC-specific implementation for cache reporting. BUG=none TEST=Builds and boots successfully on google/rex platform. Change-Id: Id5ffcab54232294ffa101f975d0ec51ac63f1910 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/alderlake: Use common CAR API for cache reportingSubrata Banik
Replace the SoC-specific `report_cache_info()` function with the common `car_report_cache_info()` API from `car_lib`. This promotes code reuse and reduces SoC-specific implementation for cache reporting. BUG=none TEST=Builds and boots successfully on google/marasov platform. Change-Id: I18be2c33dbe5186643af52823eb2fb185a296909 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83481 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/cmn/cpu: Introduce common CAR APIsSubrata Banik
This patch adds `car_lib.c` to the IA common code to consolidate SoC-agnostic CAR APIs. Initially, it includes `car_report_cache_info()` to provide a unified way to read cache information, reducing the need for SoC-specific implementations. TEST=Builds successfully for google/rex. Change-Id: I2ff84b27736057d19d4ec68c9afcb9b22e778f55 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/mtl: Enable eSOL for x86_64 archSubrata Banik
This change removes the condition that SOC_INTEL_METEORLAKE_SIGN_OF_LIFE is only enabled for x86_32 arch. Now, it is safe to enable eSOL for x86_64 platform as well. BUG=b:346682156 TEST=Able to see eSOL on google/rex64. Change-Id: I825c988800ec303a8f37141f6487115b1c7c5d3a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83498 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya: Add config options for TRULO boardSubrata Banik
This change adds the necessary Kconfig options to enable support for the TRULO board, including selecting the appropriate baseboard, HDA verb table, and TCSS configuration. Additionally, corrected the TPM_TIS_ACPI_INTERRUPT from `13` to `17` for Trulo as applicable. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I5c1cbd56cf2734058aced35868ae42c1c160f62e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83500 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya/variants/trulo: Include hda_verb.cSubrata Banik
This change adds hda_verb.c to the ramstage build, but only when the CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB config option is enabled. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I9b17126ff1493b5714d6ae715ad2863bdff4ed46 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83499 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya: Standardize TPM TIS ACPI interrupt configurationSubrata Banik
This patch sets a default value of 13 (GPE0_DW0_13/GPP_A13_IRQ) for the `TPM_TIS_ACPI_INTERRUPT` configuration option across most Google Brya variants. The HADES board uses interrupt 20 (GPE0_DW0_20/ GPP_A20_IRQ), and the ORISA board uses interrupt 17 (GPE0_DW0_17/ GPP_A17_IRQ). This refactoring simplifies future additions of board-specific TPM interrupt configurations, improving maintainability. BUG=none TEST=The timeless builds with this patch for both Nissa and Brya devices produce the same binaries. Change-Id: I9d913bf3da6957ab5c700dd746bc4b5350427d73 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83493 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>