diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2024-07-04 17:19:38 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-07-22 13:59:32 +0000 |
| commit | 203b9fb352f89c112325286cc651596da906a848 (patch) | |
| tree | 12c71c4f20e6ff6438d0dd12480bd5668b20a04f /src | |
| parent | 8b17b9b1967c5299c021cb65e9322668ad32b9cc (diff) | |
soc/intel/alderlake/tcss: Add definition of IOM_READY bit
Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1
register. Needed by Protectli VP66XX boards to poll for this bit
for about 2 seconds before FSP Silicon Init to have USB functionality.
ME is supposed to start fetching and executing the TCSS IPs FW right
after DRAM Init Done message, which happens after MRC. For most
platforms the time interval between the end of MemoryInit and start of
SiliconInit is enough for IOM_READY to get set.
TEST=Poll the IOM_READY bit on VP66XX platform and observe the
TCSS XHCI is up in lspci.
Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83356
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/tcss.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h index 014e3076e6..825b6c78b9 100644 --- a/src/soc/intel/alderlake/include/soc/tcss.h +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -7,6 +7,10 @@ #define IOM_CSME_IMR_TBT_STATUS 0x14 #define TBT_VALID_AUTHENTICATION (1 << 30) +/* TCSS IP status */ +#define IOM_TYPEC_STATUS_1 0x50 +#define IOM_READY (1 << 30) + /* IOM aux bias control registers in REGBAR MMIO space */ #define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 #define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4) |