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The temperature values were taken from guybrush as a starting point for
skyrim.
BUG=b:230428864
TEST=Boot skyrim to OS and verify thermal zones are populated and
working in /sys/class/thermal/
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6669b32f5e3dd63c6523f74166089eb4eb2d7848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed. After confirmed with the owner, the expect behavior is
only wake when eject the pen.
BUG=b:233159811
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7a82e5e8935c9ea27e923661f66809e9169bc86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65379
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add MIPI WFC based on schematics
BUG=b:236576117, b:235446911
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bd2ba187729a55c00369b218ca0414e0162b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Follow latest schematic to modify SPI flash to 16M.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I56be68b962c38d3f885dcf25a0251b8d9ab6ff3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65446
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE.
Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Extend the code to support ADL-S PCIe Root Ports.
Based on DOC #619362 and #619501.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset.
Add IRQ routing tables for PCIe Root ports up to 28th.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As we walk the results of largest_resource(), we actually know that the
condition can only be true for the first return value. So there's no
need to keep track of the first loop iteration.
Change-Id: I6d6b99e38706c0c70f3570222d97a1d71ba79744
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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While what this round() function does is documented, it still seems
hard to follow what happens when reading a call. I tried to come up
with a better name, but eventually reading an explicit ALIGN_UP()
worked best.
Change-Id: Ifd49270bbae0ee463a996643fc76bce1f97ec9b7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65400
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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These comments are a very nice example of documented code. The
comment blocks use the full, allowed line length, though. That
is nice for code, but can make text blocks harder to read. So
reflow the comments to a 72-char width (like we use in emails
and commit messages).
Also add some articles where they seemed missing and fix some
smaller nits.
Change-Id: If4cdbb383cf67f01200c8e4163fc3c576a5c3a87
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The comment said special care needs to be taken if a resource cannot
be allocated. However, the opposite seems true: There is nothing to
be done, we simply leave the resource w/o the IORESOURCE_ASSIGNED
flag. There's also no code to be found that would currently do some-
thing special. allocate_child_resources() directly continues with
the next resource after printing an error.
Change-Id: I21acbc891ea4dfb62decf9abe0ace91016486116
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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clcok ---> clock
Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Modify ddi_ports_config based on schematic Kinox_SCH_20220602.pdf.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_2 = DP or HDMI
BUG=b:233338341
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib2dbb34af1f85585b77638710d3799520c3f016f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The details about how the CPU multiprocessor init (MP) has migrated
from coreboot to FSP can be found in
https://doc.coreboot.org/soc/intel/mp_init/mp_init.html.
The major reason behind this migration is to support the Intel
proprietary and restricted CPU feature programming which can't be
performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part
of coreboot MP Init flow (prior to calling FSP-S). Hence, the new
flow introduced with Tiger Lake platform forced having monolithic
MP Init peformed by FSP (using coreboot MP PPI wrapper code).
The last 3-4 years of FSP doing MP Init has demonstrated ample
issues during platform bringup which is specific to UEFI MP Service
implementation and not relevant to open source coreboot. This new
flow makes the debug and validation aspect complicated where
any FSP MP Init code changes should have been validated with coreboot
MP PPI wrapper else might cause some failure, unfortunately,
the validation commitment has never been met, hence, issue debugging
is the only solution that remains in practice.
Most importantly, the restricted feature programming which demanded
closed source MP Init (for features like SGX and C6DRAM) has never
been enabled in coreboot (starting with Alder Lake, the SGX feature
has been dropped).
This patch attempts to decouple FSP-S doing MP Init from the rest
of the FSP-S silicon init and introduces 2nd MultiPhase SI init
which allows bootloader to perform the mandatory SoC programming
before FSP-S has done with PM programming (a.k.a set the reset CPL).
The core/uncore BWG suggests the minimum SoC programming before
BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2
to perform the required CPU programming before enabling the BIOS
Reset CPL.
This implementation would allow us to get rid of FSP running CPU
feature programming and additionally make several EDK2 MP service
modules optional (those are packed to create FSP-S blob).
In summary, this change would allow coreboot to utilize open source
MP init without running into FSP-S related code blocks.
Note: At present, Intel Alder Lake FSP doesn't have support for
MultiPhase SI Init, Index 2 (submitted a FSP code changes over
chrome-internal to enable this feature to decouple MP Init from
FSP-S init).
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Perform several thousands cycles of suspend test and power cycle
without running into any issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I314c63c917ef6fdd32f364b2c60bae22486b8b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64979
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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mc_apl7 does not use security features like VBOOT and TPM.
Test: flash mc_apl4 mainboard and ensure the disabled features via log.
Change-Id: I16683b92deb047208848b69c5aa79dc4212ce930
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65284
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add a new board 'Tentacruel', and enable SDCARD_INIT for it.
BUG=b:234409654
BRANCH=corsola
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ia10efeead575b4e193a73562275a78839415a706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65192
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change makes mdss configuration common for both sc7180 & sc7280
to avoid code duplicacy.
Changes in v2:
- Move soc related mdss changes to soc specific disp.c
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Change-Id: Ibc43ab6ee5ced08e34625e1485febd2f4717d6a0
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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In order to improve gpio merge mechanism. Change iteration override
to padbased table override. And the following patch will change fw
config override with ramstage gpio table override.
BUG=b:231690996
TEST=check gpios in pinctrl are the same.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3d0beabc2c185405cb0af31e5506b6df94e9522c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Introduce three functions:
- new_padbased_table:
Returns the gpio pad number based table
- gpio_padbased_override:
Must pass the table with padbased table
- gpio_configure_pads_with_padbased:
Must pass the table with padbased table, will skip configures the
unmapped pins by check pad and DW0 are 0.
Some boards may have complex, SKU-based GPIO programming. This
patch provides for a simpler pattern of controlling overrides of
GPIO programming by providing a table of pad configuration indexed
by pad number. Thus, pad state can be overwritten over multiple
overrides until the final takes place, and then all GPIO
programming is performed at once.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8b99127b73701b50a7f2e051dee9d12c9da9b741
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64712
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia44be7d63b0e6e16a49695d430715a7e5785d530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic31eb81bc98fd94877a51ebf44cfb2c69e4db0ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55923
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9c680d12f023d8682288e9d3619f549484f3b975
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I80ee3a8bb28d5f7b2a47b0a98abbc53a95ad25bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55917
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0e68912bf7f1ccb130b8bc6213308ec2e846efc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55920
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I668a39c603870329fd1528ddc5f3a42a379e1e76
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65267
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The only callsites in intel/xeon_sp were replaced with calls to
log_resource() and functionality is provided with LOG_RESOURCE()
now.
Change-Id: Ie44694f7a0b119d10f1bef9158fa30e71c312a55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55478
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace xx_resource() calls with calls that take the base
and size arguments as-is, without dividing by KiB (or >> 10).
With replacement of the allocator/constructor function
caller can use log_resource() instead.
Change-Id: I7e4e1e5a779c418f369dd2dab8c811f67ad1399f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55477
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These should help to make the reviews as platforms
remove KiB scaling.
Change-Id: I40644f873c0ea993353753c0ef40df4c83233355
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Function fixed_io_resource() and alias io_resource() were
previously unused. Unlike previously, IORESOURCE_STORED flag
needs to be set by the caller, when necessary.
For fixed resources, fields alignment, granularity and
limit need not be initialised, as the resource cannot
be moved. It is assumed the caller provides valid base
and size parameters.
Change-Id: I8fb4cf2dee4f5193e5652648b63c0ecba7b8bab2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Unlike fixed_mem_resource_kb() the arguments are not in KiB.
This allows coccinelle script to assign the base and size
without applying the KiB division or 10 bit right-shift.
Unlike with fixed_mem_resource_kb() the IORESOURCE_STORED flag is
passed in the flags parameter until some inconsistencies in the tree
get resolved.
Change-Id: I2cc9ef94b60d62aaf4374f400b7e05b86e4664d2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch changes the serial message type to BIOS_WARNING as sometimes
it may raise a wrong signal when microcode resides inside other part
of the IFWI instead /CBFS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I714bf74a91c2d783982c5e5ca76a70deed872473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65316
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch drops FSP Debug interface selection as coreboot now decides
the UART inerface to redirect the debug msg.
BUG=none
TEST=Able to see all coreboot and FSP debug log with and without this
patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If8c07d7e63c5d445fdb77ac38b99217bf015e15f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Enable caching of memory training data for recovery as well as normal
mode. We had HAS_RECOVERY_MRC_CACHE selected in the sc7280 Kconfig,
but never allocated a RECOVERY_MRC_CACHE in the herobrine fmap so it
never worked. Adding RECOVERY_MRC_CACHE and also removing
RO_DDR_TRAINING, RO_LIMITS_CFG, RW_LIMITS_CFG entries which have been
deprecated.
BUG=b:236995289
BRANCH=None
TEST=run dut-control power_state:rec twice and make sure that
DDR training doesn't run on the second boot.
Change-Id: I39ac7eca4ae94075874324b13c69eef59522e3c5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Having PTT means mocking secdata, so saving/reading the hash always
succeeds, but there is no data stored/read from/to TPM. The code
comparing MRC hashes did not care if secdata mocking was enabled
and failed during hash comparison with invalid data. This broke the
fastboot even if the MRC cache data was filled and correctly
checksummed. If mocking is enabled simply fallback to checksum
computing to proceed with fastboot.
TEST=Boot MSI PRO Z690-A WIFI DDR4 in fastboot mode with PTT and vboot
enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic0cf04b129fe1c5e94cd8a803bb21aa350c3f8da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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With CB:65012, google_chromeec_vbnv_context() is no longer used. Remove
it from the codebase.
BUG=b:178689388
TEST=./util/abuild/abuild -t GOOGLE_STOUT -a -x
Change-Id: I717f600f0f73c3ca932b6a442a9d5b90c35c8f3b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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We have clarified the powerdown sequence with Nvidia, and the EEs have
come up with this modified sequence which still meets the requirements
from the hardware design guide.
BUG=b:233959099
TEST=Verified by ODM and EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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These changes made my crude pattern matching work with
coccinelle simpler.
Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Commit 0cc56a2848 (nb/intel/gm45/dsdt: Fix number of PCI busses) derives
the maximum PCI bus number at runtime. However, IASL complains about the
initial 0 in the resource template, which rendered the PB00 definition
self-contradictory at build time (maximum was lower than minimum +
length - 1).
Let's return to the old default values (min: 0, max: 255, length: 256)
and adapt max and length at runtime. Also fix some surrounding whites-
pace.
NB. The issue wasn't detected before merging commit 0cc56a2848 because
of broken IASL versions that can't count errors.
Change-Id: I359d357f276feda8fe04383080d51dc492c3f2e8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64347
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Return the correct processor family code for smbios per System
Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0.
BUG=b:234409052
TEST=Boot chausie to chromeos and verify "dmidecode -t processor"
outputs the correct processor family.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for osiris board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for osiris board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia30a7b915df14c91a2526dca3e374436da286b7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2986ae6fd1f51efc6b9bb18ff2b7186357e55fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Configure GPIOs according to schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8c4347fcc975ed994261c7738e5ef811a12e4b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Base on bernadino 14 adl-p 20220531.pdf, configure GPIOs
according to schematics.
GPP_B2 => BYPASS_DET
GPP_F19 => FP_USER_PRES_FP_L
BUG=b:234384954
TEST= USE="project_crota" emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ic2e7ecc34912f07463e0025787fdf59c7602e40b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Added missing set_resources function to avoid error messages in boot up
logs.
BUG=b:230576402
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com>
Change-Id: Ie0a5bd345486293ce07e586a423d53740ad377f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This patch ensures google/volmar eMMC SKU has advanced PM support
enabled.
BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e2883d894d2ca7f810f4b72af1c12037c8fdabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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The previous two patches removed all of the soc/Kconfig files, so there
is nothing to include anymore. Get rid of the 'source' command that
includes them.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I95067c4702ef25a8a6db4d480c089f06986ce9b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65329
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the Intel top_swap feature into the intel/common Kconfig file.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3ed649aaeb51c2250be9473114c17d3f191d2c38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Most of the src/soc/Kconfig files are only there for AMD and Intel to
load the main SoC Kconfig files before any common files. That can be
done in src/Kconfig instead. Moving the loads to the lower level allows
the removal of all but the Intel soc/Kconfig file, which can be removed
in a follow-on patch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Clean up Makefile.inc by sorting entries and moving common entries to
all-y. In this way it is more clear to know what drivers have been
involved in each stage and the hardware differences between each SoC.
BUG=none
TEST=emerge-corsola coreboot
TEST=emerge-asurada coreboot
TEST=emerge-cherry coreboot
Change-Id: Idfc7de36ebf36650f7c6bd1584ef77e2a540cde9
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65315
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `send` and `recv` API functions currently print error messages
if a timeout occurs while polling the EC, but they perform the I/O
transaction regardless. This can put the EC in a bad state or
otherwise invoke undefined hardware behavior.
Most callers ignore the return value currently, but for callers
which do not, we should make sure our behavior is correct.
Signed-off-by: Abel Briggs <abelbriggs1@hotmail.com>
Change-Id: Ifb87dd1ac869807fd08463bd8fef36d0389b325e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033682
TEST=Built and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I8135684d471fdcfdbbe2f1bc5455902d56bb71de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for volmar board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I4d12f7214a306ded54b4536a27fe0fb7f3c33b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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This CL fixes my previous CL (commit ca741055e)
which introduced a couple of issues found by Coverity (see below).
The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)."
*** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size()
*** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size()
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add the desktop board types as per DOC #573387.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
|
|
This patch fixes an issue introduced with commit ca741055e
(soc/intel/adl: Add missing claimed memory regions) where PRMRR base
should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead
System Agent PCI configuration space.
With this change, coreboot is able to read PRMRR base when the
PRMRR size > 0.
TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
|
|
This patch adds a new mainboard variant called mc_apl7 which is based
on mc_apl4. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.
Test: build mc_apl7, flash to mc_apl4 and compare log level 8 output
Change-Id: Ie9f2f5c29d071de442f8f3e3eaf4b3c2a6b8920f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65283
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The common AMD ACPI GPIO access code is verified to be correct for
Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I834076c0a1d1784a272896f2d8f082ebfb86a383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The MCA banks were updated in commit 736d68c0b36e ("soc/amd/sabrina/mca:
update MCA bank names to match the hardware"), but seems that I forgot
to remove the TODO about checking if this is still correct for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd86113ccb9eeab704679afab0b985f9febed13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The common microcode update mechanism is verified to be correct and work
on Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5c41674299a829507438beb3ea597a71a0c5a972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The bits are documented in NDA document #55758.
BUG=b:228458221
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibc27f617ca9c9620b3b2cb0837b661fa0cd36c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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There is an existing issue for nissa boards where wake up from
RTC wake is not working during suspend_stress_test.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Reference: https://review.coreboot.org/c/coreboot/+/64089
Later issue was found to be with GPP_F14 configuration for nissa
boards. When coreboot skips setting GPE_EN bit for GPP_F14, RTC
wake works properly. Another way to make it work is to skip locking
GPP_F14 GPIO to allow kernel to configure it properly.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later. This fixes the issue of RTC wake not working.
Note: This patch provides workaround for the existing issue and
BUG will be closed once actual reason is identified and proper
fix is available.
BUG=b:234097956
BRANCH=None
TEST=RTC wake works on Nivviks board with the patch.
Change-Id: Ie8091ab8acf2b3f064cb79bdf4700f6b4c1674a5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
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Add the support RAM parts for Xivu.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576117
BRANCH=None
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I02866f7dcdc70d1051d187fdda30e04bb654ece3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65252
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the xivu variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:235025984
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_XIVU
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I12341a2414e58ebc1c22429d35a03afef27adace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65235
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
AMD SDLE testing had been done.
Apply the following telemetry settings for dewatt DVT:
vdd scale: 91573
vdd offset: 620
soc scale: 30829
soc offset: 235
BUG=b:234417498
TEST=1. emerge-guybrush coreboot
2. pass AMD SDLE test
Change-Id: I46650ca12ccfec90f15ee562d30c62c389d14d39
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
Enable PwrOptEnable FSP S UPD and hook it to the inverted value of
SataPwrOptimizeDisable to allow it to be disabled from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Add support for MT62F512M32D2DR-031 WT:B and K3LKLKL0EM-MGCN.
These will be used as backup parts if there is issues getting the
Hynix parts.
BUG=b:233822880,b:236423310
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6ace8788ffb2ec40d01b91d0a4d751e0a95883f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Arbitrage is an internal tool at Google to work with schematics
programatically. In particular, it features an "export-coreboot-gpio"
command, which, does it's best to try and make a gpio.c from the
schematics to avoid human errors when translating to C code.
This commit adds a gpio.c generated by running:
"arb export-coreboot-gpio ghost4adl:P0_2022_06_17"
This GPIO config will require hand modification. This is done in a
follow-up CL. (i.e., this CL intentionally leaves the config exactly
how it was generated by Arbitrage so we get a good diff on the changes
we needed to make)
BUG=b:234626939,b:231719130
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I35a85202768a366357073d3ebc177d0e0da661f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65210
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Initial boards will not have an internal panel. Enable TCSS display
detection so we can boot on an external panel over Type-C.
BUG=b:235294840
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6f65ddc24701d6f6ad0250560cc05b5e1d32370f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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|
The TPM PPI code was only generated for memory mapped non-CRB TPMs.
There is no reason why CRB TPM should not have the PPI, e.g. PTT.
Call the relevant method to add the PPI to SSDT.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3d3f08ea686c95ef75ae8fe7a5dcf16f7492ce68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00.
FSPM:
Includes below 2 UPDs
1. TdcEnable
2. TdcTimeWindow
FSPS:
Address Offset changes.
BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Based on 'commit 0b917bde36a7 ("mb/google/brya/var/kinox: Set power
limit based on charger type")' to refactoring update_power_limits
function for kinox.
BUG=b:231911918
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1fcb593090f95bf23808e577dd11b8a836f47494
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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|
Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all
ChromeOS devices and they've reached the end of life since Feb 2022.
Therefore, remove VBOOT_VBNV_EC for them, each with different
replacement.
- nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by
reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with
VBOOT_VBNV_FLASH.
- veyron: Add RW_NVRAM to their FMAP (by reducing the size of
SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also
enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing
the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its
allotted size.
- daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for
VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs.
- peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC
option.
Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving
VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for
vboot nvdata (VBNV).
Also add a check in read_vbnv() and save_vbnv() for VBNV options.
BUG=b:178689388
TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a
TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a
TEST=util/abuild/abuild -t GOOGLE_DAISY -a
TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a
BRANCH=none
Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033683
TEST=Built and tested on tarlo board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib543cee82f6940ab35a1a40af1d41bb2b8bf8521
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles
the split.
Based on:
- Intel PCH-S EDS Vol2 (#621483)
- Alderlake-S FSP
- slimbootloader sources
- Linux alderlake-pinctrl driver
Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Both UART and DMA MMIO regions for each UART are mapped by the
UEFI reference code, so do the same here.
Without these defined, UART-attached devices fail to correctly
initialize under Windows.
Change-Id: I0e1af9028c7c1746407e923cebe824a15aeb565e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65233
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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MAX_PCIE_CLOCK_SRC is not an user-configurable option.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Meteor Lake SA device ID 0x7d14 (4+8, 15W).
BUG=b:224325352
TEST=Able to build MTL SoC and verified SA DID is now shown proper.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable 1d.0 UFS as it is not used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib392bc64db440ea3d98ee62536d5395587a3f6aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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With IOMMU disabled, kernel complains that 'IOMMUv2 functionality not
available on this system'. Enable iommu in devicetree for skyrim proto
board in order to allow kernel to load and initialize IOMMUv2.
BUG=b:232750390
TEST=Boot to Chrome OS on skyrim board, and
grep dmesg for "AMD IOMMUv2 loaded and initialized"
Change-Id: I2f10f5eda8083335619a34c44df253b8e5a8572c
Signed-off-by: Jason Glenesk <Jason.Glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The file is already present in the microcode submodule repository.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib284908db165dc95a5895979174512818f2aceff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable VBOOT_EARLY_EC_SYNC in coreboot.
EC Sync was failing on ADL-N RVP since the ec image was not getting
stitched into coreboot during emerge build. This is now fixed with https://crrev.com/c/3705002 and hence enabling the EC sync for ADL-N RVP
BUG=b:232875824
TEST=Build and boot adlrvp-n. Ensure EC Software sync is complete.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ibea37825abd0f13a5184cbbe96c38d44474782f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
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This patch ensures all APs finish the task and continue
before_post_cpus_init() if coreboot decides to perform multiprocessor
initialization using native coreboot drivers instead of using
FSP MP PPI implementation.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3b76974ab19323201bf1dca9af423481a40f65c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates choice that lists all possible options to perform
MP Init as below:
1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP
runs feature programming based and selects MP_SERVICES_PPI_V2 config.
2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP
init and feature programming) using native implementation.
Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot
is expected to run MP Init.
Refactor SoC code to allow required FSP UPD override based on
selected MP Init option.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds an error msg if intel_microcode_find() is unable to
find a microcode for the CPU SKU.
TEST=Able to see the error msg in coreboot serial log in case packed
with wrong microcode binary.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib4865575a44d2c8c6c3a20c2823a546d8f261e52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65285
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch refactors the microcode loading and reloading API with a
helper function that perform the actual MSR write operation after
taking the microcode pointer from the caller function.
Also, convert the microcode loading failure msg type from `BIOS_INFO`
to `BIOS_ERR` to catch the error in proper.
TEST=Able to perform microcode loading on google/kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9a7cdc2d2c9211f1e0c7921015126f7a1be87761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65249
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to perform core PRMRR sync if SoC decides to
perform MP Init using coreboot native implementation.
Also, implement a function to allow calling `init_core_prmrr()`
for all CPUs from `before_post_cpus_init()`.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9b6222c98ff278419fa8411054c0954689e1271e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64978
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls into `intel_reload_microcode() function to load
second microcode patch after BIOS Done bit is set and before
setting the BIOS Reset CPL bit.
Also, remove redundant microcode reloading debug print.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icb3fcfd7ef5478be0a40f8f1358f55c0247b4914
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65157
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch introduces a newer API to reload the microcode patch when
SoC selects RELOAD_MICROCODE_PATCH config.
Expected to call this API being independent of CPU MP Init regular
flow hence, doesn't regress the boot time.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If480e44b88d04e5cb25d7104961b70f7be041a23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable PCIe WLAN for Kinox
1. Enable PCI port 5 for PCIe WLAN
2. Enable CLKREQ, CLK SRC 2 for PCI port 5
BUG=b:236175551
TEST=Build and boot to OS in Kinox. Ensure that the WLAN module is
enumerated in the output of lspci.
localhost ~ # lspci
02:00.0 Network controller: Realtek Semiconductor Co., Ltd.Device
c852 (rev 01)
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3fbeadc85c9c88f5d178326dbbc83762083fe59a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65168
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Let's not rely on the type to get the correct result,
casting 0 to 0ull made the result wrong.
Change-Id: I6dfba3800170fdd4267e3bb74c55b05533c101fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This makes coccinelle script happy, everyone else sets flags last.
Change-Id: I80f421aeacb6e72fea2265c69cafb2a0d89e5616
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The IRQ was incorrecly allocated as IO resource.
It's not possible for new_resource() to return NULL.
Change-Id: I66811b36b44f06cb39df8e9cdab87be0e2ef8eb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add Makefile.inc to include five generic LPDDR5 SPDs for the following
parts for Joxer:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576115
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I90acb436bccd5dae8585436316246c50fc256842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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CL 64619 adds the required initial code for raptorlake.
Select BOARD_INTEL_ADLRVP_RPL_EXT_EC for VBOOT_MOCK_SECDATA which is
mistakenly not selected.
BUG=None
BRANCH=firmware-brya-14505.B
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I5da561cb31b0cb0d574a8091cc346d6b321ac6fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Commit 96f7b96866b0bce7a1323c4da478f838f884383f (soc/amd/common/block/
cpu/: Make ucode update more generic) removed the code that used the
SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused
Kconfig option.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by
default for TPM_GOOGLE_TI50 devices. It makes the build system run the
`futility gscvd` command to create a GSCVD (GSC verification data) which
signs the CBFS trust anchor (bootblock and GBB). In order for this to
work, boards will need to have an RO_GSCVD section in their FMAP, and
production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option
with the correct ID for each variant.
BUG=b:229015103
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Disable Sata Port 1 as it is not used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I93ecdaba5d1ce96ddcf3695edd7fb109054743e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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These are configured by the TXE, so they do not need to be configured.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I13957992d637a53203b4328e39c0e6607e017891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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