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2024-09-05soc/intel/common/systemagent: Fix grammer in commentsYuchi Chen
Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84199 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-05mb/google/brox/var/jubilant: Remove STORAGE_UNKNOWN fw_config optionKarthikeyan Ramasubramanian
With `probe unprovisioned` fw_config rule, there is no need to define an explicit STORAGE_UNKNOWN option. Hence remove it. BUG=None TEST=Build Jubilant FW image. Change-Id: I4f6ace4b39a1ee0b63486d3872b20c8da719ae4a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84095 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-05soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-04src/include: Introduce a new BIT_FLAG_32(x) macroSaurabh Mishra
Introduces the BIT_FLAG_32(x) macro to create a 32-bit mask with the designated bit set. This ensures compatibility with the 32-bit 'GEN_PMCON_A' register on 64-bit systems, where 1ul is 64 bits wide and could potentially cause an overflow when shifted beyond 31 bits. Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04soc/intel: Refactor ITSS macrosSubrata Banik
This patch refactors ITSS related SoC specific macros by consolidating them into a common itss.h file. This improves code maintainability and reduces redundancy as each SoC previously defined the same macros. Specific changes include: - Move SoC specific ITSS macros into intelblocks/itss.h. - SoC code now includes intelblocks/itss.h instead of the SoC-local soc/itss.h. - Drop soc/itss.h from static ASL files. - Delete soc/itss.h from all SoC locals except Apollo Lake and Sky Lake. TEST=Able to build and boot google/hatch, google/xol and google/karis. Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-09-04mb/google/brox/jubilant: Tune I2C timingRen Kuo
Tune I2C2 timing: Set falling time to 250ns from 400ns to meet spec: "THIGH>0.6us" BUG=b:362685374 TEST= Build jubilant firmware Measure the i2c signal on jubilant to meet spec: I2C2 THIGH from 0.494 us to 0.76 us Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84143 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-04soc/intel/common/block: Include register offsets for POWER_CTLSaurabh Mishra
Details: - Add (POWER_CTL) – Offset 0x1fc required bits. Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04include/cpu/x86: Add Misc Enable and Thermal Interrupt Register MacroSaurabh Mishra
Details: - Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits - Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84174 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04soc/intel: Remove unused `GPIO_IRQ_xxx` definitionsSubrata Banik
This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake, Meteor Lake and Tiger Lake. These definitions are no longer needed. TEST=Able to build and boot google/xol and google/karis. Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-04soc/intel/meteorlake: Remove unused pch_handle_sideband() functionSubrata Banik
This change removes the unused pch_handle_sideband() function from the Meteor Lake platform code. TEST=Able to build and boot google/rex. Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04tree: Use boolean for emmc_enable_hs400_modeElyes Haouas
Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_package_c_state_demotionElyes Haouas
Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_c1_state_auto_demotionElyes Haouas
Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for skip_ext_gfx_scanElyes Haouas
Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-09-04tree: Drop unnecessary "true/false" commentsElyes Haouas
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-03mb/google/brox/jubilant: Generate RAM IDsRen Kuo
Generate RAM IDs of lp5 memory: 1)Hyinx 4GB*4 H58G56BK8BX068 2)SAMSUNG 4GB*4 K3KL8L80CM-MGCT BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-09-03mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13Ren Kuo
Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT. The design change to follow the brox's GPE0 routing, and the FP wake source can be routed. BUG=b:363166664 TEST= Build jubilant firmware Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/lattepanda: Add support for LattePanda MuKunYi Chen
Add initial support for the LattePanda Mu board, which features: - Intel Alder Lake-N N100 processor - Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory - Samsung KLMCG2UCTA-B041, 64GB eMMC storage - SO-DIMM 260-pin connector for function expansion This commit includes: - Basic board configuration - Memory initialization - Essential I/O setup - Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file from original BIOS - BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu located at "./Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip" Test Environment: - Carrier Board: Lite - Payload: mrchromebox/edk2 - EDK2 Version: uefipayload_202309 Test result Passed: - Windows 11 boot from eMMC - Install Ubuntu 24.04 on NVMe SSD - Ubuntu 24.04 boot from NVMe SSD - USB 3.0/2.0 functionality - Realtek RTL8111H-CG-RH Ethernet - HDMI Display - Audio over HDMI work in Ubuntu 24.04 Known Issues: - S3 sleep mode non-functional - Power-on after shutdown requires power removal - SuperIO UART not detected in Windows 11 - Audio over HDMI not work in Windows 11 - Windows 11 BSOD occurs with NVMe SSD installed: - Stop code: Machine Check Exception - NVMe SSD not working on Windows 11, except when: - KDNet Debugging enabled on NIC during boot - SSD becomes functional in this scenario Change-Id: I79696bdd837a221860b32f54629212c3346dca66 Signed-off-by: KunYi Chen <kunyi.chen@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-02drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_infoArthur Heymans
GCC LTO found this. Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84056 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/cherry: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118 Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-02soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe resetYidi Lin
Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2024-09-02drivers/usb/acpi: Add DSM for Intel BluetoothSean Rhodes
Add support for creating a DSM Method for Intel Bluetooth that is outlined in Intel's connectivity integrated guide (which has no document number). It supports two GUIDs: Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Tile Activation Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Bluetooth reset timing Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/zork: Ensure eSPI GPIOs programmed w/o vbootMatt DeVillier
On the non-vboot boot path, eSPI is configured as part of fch_pre_init(), and we need to ensure that the mainboard sets the eSPI GPIOs properly before the common SoC code performs eSPI init. Use the mb_set_up_early_espi() function to set the eSPI GPIOs at the correct time. TEST=build/boot google/zork (morphius), verify keyboard functional. Change-Id: I03efe6def37a018c3de410523be21bf008174e94 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84148 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/zork: Ensure early GPIOs programmed w/o vbootMatt DeVillier
Now that zork can boot without vboot, ensure that the GPIOs set in verstage are programmed in bootblock on the non-vboot path. The eSPI GPIOs will be set in a subsequent patch using mb_set_up_early_espi() since setting them in bootblock_mainboard_early_init() would be too late given when the SoC eSPI init takes place. TEST=build/boot google/zork (morphius) w/o vboot Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-02mb/google/nissa/var/teliks: Add fw_config fields for rtl8852becengjianeng
Add a new fw config field for wifi category as WIFI_6_8852, which is PCIe based. Also, enable WIFI_6_8852 for existing PCIe based wifi port as well as bluetooth port. BUG=b:356434907 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84138 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/nissa/var/teliks: Force audio mute to avoid screen flickcengjianeng
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG=b:360243615 BRANCH=firmware-nissa-15217.B TEST:Verfied on Teliks and cannot reproduce the issue Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84137 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
2024-09-02soc/intel/common/systemagent: read sa resources only from domain 0Yuchi Chen
Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-02soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by KconfigYuchi Chen
CAPID_A, BDSM and BGSM registers may not exist on specific platform, this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER` to select them. Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-02soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_typeYidi Lin
Add EARLY_INIT_PCIE_RESET for early PERST# de-assertion. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2024-09-02soc/mediatek/common: Move mtk_pcie_reset to common/pcie.cYidi Lin
mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-02soc/mediatek/common/pcie: Use clr/setbits32pYidi Lin
Use clr/setbits32p to make code cleaner. BUG=none TEST=emerge-cherry coreboot Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2024-09-02soc/mediatek/common/pcie: Add DEVTREE_CONST qualifierYidi Lin
Currently pcie.c is built into ramstage only, where DEVTREE_CONST is an empty macro, so there's no problem with that. However, if we would like to include that file in pre-ramstage, then DEVTREE_CONST would be 'const', leading to the following build error: ``` src/soc/mediatek/common/pcie.c:104:26: error: assignment discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] 104 | root_dev = pcidev_path_on_root(devfn); | ^ ``` BUG=none TEST=emerge-cherry coreboot Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84113 Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-02mb/google/brox: Remove ACPI Power Resource for Bluetooth deviceKarthikeyan Ramasubramanian
Bluetooth driver in kernel requires reset-gpio in current resource settings (_CRS) and device specific data (_DSD) ACPI objects. Hence remove ACPI Power Resource for Bluetooth device so that the concerned ACPI objects get populated. BUG=b:362817900 TEST=Build Brox Firmware image and boot to OS. Ensure that the _CRS and _DSP ACPI objects are filled in the SSDT with the required data. Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x004D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "reset-gpio", Package (0x04) { \_SB.PCI0.XHCI.RHUB.HS10, Zero, Zero, One } } } }) Change-Id: If6e679aa3f4181e7963ac53d0847b1512959b3a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84135 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-09-02mb/google/brox/jubilant: Update dptf settingsRen Kuo
Update dptf settings from thermal design: 1) Remove fan control and active policy, since fan is controlled by EC. 2) Modify TSRs to 0:DRAM, 1:SOC, 2:Charger 3) Update Pl2 min&max values BUG=None TEST= Build jubilant firmware Generate and check ACPI SSDT.dsl $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2024-09-02soc/intel/meteorlake: Hook up microcode from repositoryFelix Singer
Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-02mb/cwwk/adl/devicetree: enable all USB portsFelix Held
The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on the mainboard and likely also routes one USB2 port to the m.2 E key slot which is typically used for Bluetooth support when an E key m.2 WIFI + Bluetooth card is installed. This is untested, since I only have the cw-al-4l-v2.0 mainboard, but from looking at the documentation of the version 1 and looking at how things are done on the version 2 this should be correct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-02soc/intel/common/gpio: support 16-bit CPU Port IDCliff Huang
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID. - Change cpu_port field to 16-bit width if the Kconfig is set. BUG=none TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. The bit 15:8 of the returned port ID value should be 0xF2 instead of zero. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/brya: Add romstage early graphics for trulo baseboardSubrata Banik
1) Add all required changes for eSOL support. 2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo. The CSOT (MNC207QS1-1) panel is used for the devicetree. BUG=b:362895813 TEST=On-screen text message seen during MRC training on Trulo SKU1. MRC: no data in 'RW_MRC_CACHE' bootmode is set to: 0 DP PHY mode status not complete DP PHY mode status not complete DP PHY mode status not complete ... Informing user on-display of memory training Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2024-09-02soc/intel/alderlake: Prevent overlapping boot screensSubrata Banik
Previously, `early_graphics_stop()` was skipped unconditionally if `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` was enabled. This led to overlapping screens when CSE sync was not triggered in ramstage, as both the eSOL message and the firmware splash screen would be displayed. This change refactors the condition for calling `early_graphics_stop()` to ensure it is only skipped if a CSE firmware update is actually required *and* `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` is set. This allows eSOL to display its message during CSE sync, but tears down early graphics programming in other cases to prevent overlapping screens. Additionally, this change ensures that `early_graphics_stop()` is the last function called by the romstage to guarantee proper cleanup. BUG=b:362895813 TEST=Able to boot google/tivviks_ufs without overlapping screens. Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-09-02mb/google/brox/var/lotso: Update verb tableJian Tong
Update verb table provided by Realtek on 20240710. Restults: SNR > 90 (spec>=90). BUG=b:349996984 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: Ic4f03d09010efa7e32713b2697d5832255f64317 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83920 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-01acpi/sata.c: Fix Wunterminated-string-initialization error on port_nameElyes Haouas
src/acpi/sata.c: In function 'generate_sata_ssdt_ports': src/acpi/sata.c:27:29: error: initializer-string for array of 'char' is too long [-Werror=unterminated-string-initialization] 27 | char port_name[4] = "PR00"; | ^~~~~~ Change-Id: Ie80c2329c4a2698bd9e72ba1b36c1c05e37b214b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Sumeet Pawnikar <sumeet4linux@gmail.com>
2024-09-01tree: Use boolean for s0ix_enableElyes Haouas
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-01tree: Use eist_enable as bool for newly merged filesElyes Haouas
Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30drivers/efi/uefi_capsules.c: coalesce and store UEFI capsulesSergii Dmytruk
How it approximately works: (During a normal system run): 1. OS puts a capsule into RAM and calls UpdateCapsule() function of EFI runtime 2. If applying the update requires a reboot, EFI implementation creates a new CapsuleUpdateData* EFI variable pointing at the beginning of capsules description (not data, but description of the data) and does a warm reboot leaving capsule data and its description in RAM to be picked by firmware on the next boot process (After DEV_INIT:) 3. Capsules are discovered by checking for CapsuleUpdateData* variables 4. Capsule description in memory and capsule data is validated for sanity 5. Capsule data is coalesced into a continuous piece of memory (On BS_WRITE_TABLES via dasharo_add_capsules_to_bootmem() hook:) 6. Buffer with coalesced capsules is marked as reserved (On BS_WRITE_TABLES via lb_uefi_capsules() hook:) 7. coreboot table entry is added for each of the discovered capsules (In UEFI payload:) 8. CapsuleUpdateData* get removed 9. coreboot table is checked for any update capsules which are then applied Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-08-30mb/qemu-{i440fx,q35}: reduce default ROM size to 8 MiBKrystian Hebel
By default, QEMU bails when trying to use bigger images mounted with '-drive if=pflash', which is required to make use of writable flash introduced in CB:82555. This changes both default size in Kconfig as well as FMAP layouts. Since QEMU 5.0.0 it is possible to change the limit of firmware size with `max-fw-size` machine configuration option, up to 16 MiB, as bigger sizes would overlap with IO APIC memory range. Default is still 8 MiB, so it makes sense to have identical default in coreboot. Error thrown by QEMU when trying to use too big ROM: qemu-system-x86_64: combined size of system firmware exceeds 8388608 bytes Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82639 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-30mb/qemu-q35/smihandler.c: add support for SMIs on QEMUKrystian Hebel
qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating Intel chipset. In addition, even though it implements SMI_STS register, QEMU never sets any bits in it. As there is little emulated hardware that can be generating SMI, assume that all SMIs come from APM. This source is used e.g. to disable ACPI (which wasn't working until now on QEMU) and SMMSTORE. Tested by invoking SMMSTORE commands from the payload with SMM logging. Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82558 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30soc/mediatek/mt8196: Enable VBOOT_DEFINE_WIDEVINE_COUNTERSYu-Ping Wu
To support Widevine DRM, enable VBOOT_DEFINE_WIDEVINE_COUNTERS. BUG=b:357976379 TEST=emerge-rauru coreboot BRANCH=none Change-Id: I3760c30b175338165f8e11b59c7cfa830070a19e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-30nb/intel/sandybridge: Fix uninitialised variableArthur Heymans
GCC with LTO caught this. Change-Id: I9f78b9973729bdedb40bd63b8989e94c9c498814 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-30arch/x86/car.ld: Fix overlapping regionsArthur Heymans
The fspm_rc_heap is already accounted for inside .car.data. Some linkers like LLD do not like overlapping regions so remove this. Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84048 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-30soc/intel/apl: Fix building with clang & LTOArthur Heymans
LTO does not like that assert on a constant, so use the more appropriate static assertion. Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-30soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overreadArthur Heymans
On xeon-sp this is a zero length array. With GCC LTO this triggers the stringop-overread warning. To work around this change the signature of the function from an array to a pointer. Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-30soc/intel/meteorlake: Configure DDR5 Physical channel width to 64Arthur Heymans
A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5 Physical channel width to 64" Building with GCC LTO cought this buffer overflow when assigning SPD addresses to a buffer. Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-30ext_stage_cache: Make sure variables are initializedArthur Heymans
GCC LTO incorrectly warns about this it seems. This also exits gracefully from stage-cache code if no smm region is found. Change-Id: Ib1851295646258e97c489dc7402b9df3fcf092c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30soc/cavium: Fix non matching typesArthur Heymans
There is no struct device *dev equivalent of this function. Clang LTO warns about mismatching types. Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-29soc/intel/xeon_sp: Add PCIe root port driverShuo Liu
The driver sets ACPI names for PCIe root ports and its subordinate devices, and fill SSDT for them accordingly. SPR PCIe root port devices are initially supported. TEST=Build and boot on intel/archercity CRB Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-08-29soc/intel/raptorlake: Use updated microcode from blobs repoFelix Singer
This updated microcode fixes the recent voltage issues on the Raptor Lake S platform. Intel provided this specific microcode just as an attachment [1]. Thus, we've uploaded it to our own blobs repository, which is why the path is changed. Microcode signature: sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129 [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/81 Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84132 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29cbmem.h: Change return type of cbmem_get_regionArthur Heymans
The underlying IMD function already returns an integer which indicates success or failure. This removes the need to have initialized variables that need to be checked for NULL later. In some cases this actually adds the appropriate check for returned values. Dying is appropriate if cbmem is not found as it is essential to the bootflow. Change-Id: Ib3e09a75380faf9f533601368993261f042422ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-29lib/rmodules: Add support for LTOArthur Heymans
Change-Id: I9cdda036f330486370e8c4120be5b6a0fd982e99 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84038 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29cpu/x86/smm: Don't do partial linkingArthur Heymans
For LTO we want to link everything in one go. Change-Id: If2c186eb87072e0b80c7e8998b2a0d9bdfddf740 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84037 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29cpu/x86/64bit: Specify linker to be used for cbfs PTArthur Heymans
When clang supports linking bare metal targets it defaults to LLD for linking which linking those raw data structures used to generate CBFS page tables does not fare well. Change-Id: I66fb374a456ea752a97a41426c5a98e6747f3a92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-29mb/google/rauru: Reset USB hub in bootblockYidi Lin
We have to reset the USB hub as early as possible. Otherwise the USB3 hub may not be usable in the payload. This design has been introduced since Cherry. TEST=build pass. BUG=b:317009620 Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29mb/google/rauru: Setup USB host in ramstageMingjin Ge
Add usb host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com> Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-29soc/mediatek/mt8196: Add USB host supportMingjin Ge
Add USB host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com> Change-Id: Ia4efcddac9bf5e04e688648a5c22384075a0b026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-29mb/google/brya/var/nova: Configure scaler I2C GPIOsKenneth Chan
According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL). BUG=b:358439747 TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C. Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-29soc/intel/alderlake: Add Vccin Aux Imon Iccmax settingSimon Yang
According to RDC#646929 Power Map, there are two expected values of VccInAuxImonIccImax and the value has to align with HW design. But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A), hence, provide a config for projects modification. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Modify the register and add a printk to output a debug message to observe whether the value is changing as expected. Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-08-28mb/google/brox/var/lotso: Remove STORAGE_UNKNOWN fw_config optionKarthikeyan Ramasubramanian
With `probe unprovisioned` fw_config rule, there is no need to define an explicit STORAGE_UNKNOWN option. Hence remove it. BUG=None TEST=Build Lotso FW image. Change-Id: Ia170a6e006cb51e95fbaf3efe1106ca907165eca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84094 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28mb/google/brox: Disable Thunderbolt deviceKarthikeyan Ramasubramanian
This feature is not required in Brox devices. Hence disable the concerned device. BUG=None TEST=Build Brox firmware and boot to OS. Ensure that the concerned device is disabled in the OS. Change-Id: I355852c780c552e6f9b2c28508f53580f392c1b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84093 Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
2024-08-28mb/qemu-i440fx/rom_media: Use MEM_REGION_DEV_INIT() for boot_devNico Huber
`boot_dev` can be const, and we can use MEM_REGION_DEV_INIT() as all the values are known at compile time. Change-Id: Icd3757ba4b5e8bfbee9e9c9d18bf0ee71520a8ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84089 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28mb/google/nissa/var/anraggar: Force audio mute to avoid screen flickSimon Yang
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG:b=357764688 BRANCH=firmware-nissa-15217.B TEST:Verfied on Anraggar and cannot reproduce the issue Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-28mb/google/nissa/var/nivviks: Prevent camera LED blinking during bootSowmya V
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. TEST=Build and boot nivviks. Monitor the camera LED blinking during boot. Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-28soc/intel/adl: Prevent unconditional legacy COM ports initializationSubrata Banik
This patch eliminates the LPC_IOE_COMA_EN and LPC_IOE_COMB_EN IO enables from the io_enables variable in the pch_early_iorange_init() function because lpc_io_setup_comm_a_b() is intended to activate legacy COM ports like COM-A (0x3F8 - 0x3FF) and COM_B (0x2F8 - 0x2FF). These COM ports are being activated unconditionally, which is undesirable for the Intel Alder Lake platform and causes traffic over the IO bus. As a result, this code is being removed and platforms that select DRIVERS_UART_8250IO can activate legacy COM ports. BUG=b:354066052 TEST=Able to boot google/redrix to the operating system and confirm that there was no traffic over legacy COMs while being monitored using the eSPI analyzer. Change-Id: I7a6e38bd151f823d37c07ee89a800489122cc209 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84080 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28soc/intel/alderlake: Remove SOC_INTEL_GFX_MBUS_JOIN configSubrata Banik
This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option. Support for fast modeset joining has been added to the mainline i915 kernel driver (https://patchwork.freedesktop.org/series/130480/), making this coreboot-specific workaround unnecessary. BUG=b:291885733 TEST=Successful build and boot of google/marasov with single and dual displays, no redundant boot splash. Change-Id: I53c08a0e7a40b24db7cc910c5b9adc2376a9bb17 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-28tree: Use boolean for "eist_enable"Elyes Haouas
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-08-27soc/amd/stoneyridge/smihandler: add PSP SMI handlerFelix Held
Now that the PSP SMI handler for flash access is also implemented for the PSP generation 1, the PSP SMI handler can be added to the Stoneyridge code too. The actual PSP SMI handler code will only be added to the build when SOC_AMD_COMMON_BLOCK_PSP_SMI is selected which isn't the default case, so this patch doesn't change the current behavior unless that option is also selected. This SMI handler mainly added for completeness since the PSP firmware blobs released for Stoneyridge are probably lacking the corresponding PSP-side code to send the PSP SMI to the host. At least if I remember correctly the PSP bootloader release for Stoneyridge has the ability to load the secure OS removed and since the secure OS is the runtime component, some part of that is probably what's sending those SMIs to the host. If there are some other PSP bootloader builds that support loading the secure OS, this patch might still be useful for those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78944e2de86bc1e8e277d22a7a8da517622f49a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84077 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27soc/amd/common/psp: move PSP SMI SPI access function prototypesFelix Held
Now that we have the local psp_smi_flash.h header, move the psp_smi_spi_* function prototypes there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12cbbabf6a960836fe0c5dc1424c08550cb66a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84068 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-27soc/amd/common/psp: consistently use uint[8,16,32,64]_t data typesFelix Held
Use the uint[8,16,32,64]_t data types everywhere instead of a mixture of uint[8,16,32,64]_t and u[8,16,32,64] data types for consistency. Suggested-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I36151ecf94619afaf690dbb73834fcff3c51fdac Reviewed-on: https://review.coreboot.org/c/coreboot/+/84067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp: add helper functions to retrieve capability bitsFelix Held
Add helper functions to send the PSP commands to query the fTPM and PSP capability bits as well as the HSTI state. All SoCs using any PSP generation support the MBOX_BIOS_CMD_PSP_FTPM_QUERY command and some generation 1 and all generation 2 PSP SoCs support the MBOX_BIOS_CMD_HSTI_QUERY command, so implement those two in the common psp.c. Only PSP generation 2 supports the MBOX_BIOS_CMD_PSP_CAPS_QUERY command, so implement that one in psp_gen2.c. This code is ported and modified from github.com/teslamotors/coreboot/tree/tesla-4.12-amd Document #54267 revision 1.06 was used as reference for the 1st PSP generation and document #55758 revision 2.04 was used for the 2nd PSP generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e17f994fb332690828c55742262da793e297d99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_def: rename MBOX_BIOS_CMD_PSP_QUERYFelix Held
Rename MBOX_BIOS_CMD_PSP_QUERY to MBOX_BIOS_CMD_PSP_FTPM_QUERY to bring it a bit more in line with document #55758 revision 2.04 and to avoid confusion when another command is added in a follow-up patch. In document #54267 revision 1.06 this command is called MBOX_BIOS_CMD_PSP_QUERY and in document #55758 revision 2.04 it's called MBOX_BIOS_CMD_FTPM_QUERY, so just name it MBOX_BIOS_CMD_PSP_FTPM_QUERY in coreboot which should be the least confusing name for it that still somewhat aligns with the documentation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id085b34363d39528bd125dfb77596d3ed13b6fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84065 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_smi_flash: implement generation 1 supportFelix Held
Implement the request buffer access functions for the PSP generation 1 case. In this case, only the SMI_TARGET_NVRAM is supported, so always return this target NV ID and always return true in the validity checks which in the PSP generation 2 case check if the target NV ID is valid. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e141f846e930bab6972a281745c0180ac52c291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84064 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-27soc/amd/common/psp/psp_smi_flash: introduce common data structuresFelix Held
The request buffer data structures differ between the PSP generation 1 and 2 in the way that the generation 2 added the 64 bit target NV ID field right at the beginning of the request buffer data structures. In order to make the data structure definitions common, remove the target_nv_id struct element via the preprocessor in case the SOC_AMD_COMMON_BLOCK_PSP_GEN2 option isn't selected. Since the request buffer data structures are now common for both generations, also remove the 'v2' from the struct names. Document #54267 revision 1.06 was used as reference for the 1st PSP generation and document #55758 revision 2.04 was used for the 2nd PSP generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe0bd2d8e6a5c39cc67a49e7bb3a51ce0900a39a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_smi_flash: factor out generation-specific codeFelix Held
Factor out the code to access the request buffer into PSP generation specific file. This is a preparation for adding PSP SMI flash access support for the PSP generation 1 which has a slightly different request buffer layout. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e18f7ea53592d9fd413ad56e8d137cfc13ad5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_def: rework command buffer documentationFelix Held
The existing comment on the mbox_default_buffer struct was outdated and didn't reflect the current state, so rework it to keep it a bit more generic and also add the document number for the newer generations of CPUs. To better document which commands use non-default buffers, add the names of the commands using the non-default buffers to those buffer struct definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I510d953217240243392e8a415358524257bd28b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27arch/arm: Fix building with LTOArthur Heymans
With LTO clang cannot find the aliased symbols. Change-Id: I3d89c093cee2636e648987a06afb0d325b1d96ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-27mainboard/google/rex: Remove HAVE_ACPI_RESUME for Intel Meteor LakeSubrata Banik
This patch removes the HAVE_ACPI_RESUME config option from the Google Rex mainboard configuration. The Intel Meteor Lake SoC does not support S3 (ACPI sleep state) entry/exit, and attempting S3 validation could lead to abnormal platform behavior. This change ensures that `_S3` is not listed as a valid wake source in the DSDT (Differentiated System Description Table) after booting to the OS. BUG=b:351025543 TEST=Booted google/rex successfully and verified that the `_S3` name variable is not present in the DSDT. Change-Id: I730ade628eea84c60ba003a0c871e729b0ee0a9f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84081 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-27mb/dell: Add Latitude E6230 (Ivy Bridge)Nicholas Chin
This was adapted from CB:22693 from Iru Cai, which was based on autoport. I do not physically have this system. Someone with physical access to an E6230 running version A11 of the vendor firmware sent me the VBT after running the command `intelvbttool --inlegacy --outvbt data.vbt`. This new version of the port has not yet been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Original-Change-Id: I8cdc01e902e670310628809416290045c2102340 Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82153 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/dell: Add Latitude E6330 (Ivy Bridge)Nicholas Chin
Mainboard is QAL70/LA-7741P. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A21 of the vendor firmware. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I827826e9ff8a9a534c50250458b399104478e06c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/dell: Add Latitude E6220 (Sandy Bridge)Nicholas Chin
Mainboard is codenamed Vida. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. The VBT was obtained using intelvbttool while running version A14 (latest available version) of the vendor firmware. Tested and found to boot as part of a libreboot build based on upstream coreboot commit b7341da191 with additional patches, though these do not appear to affect SNB/IVB. The base E6430 patch was tested against coreboot main. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82131 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/dell: Add Latitude E6320 (Sandy Bridge)Nicholas Chin
Mainboard is PAL70/LA-6611P. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A22 of the vendor firmware. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82130 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27drivers/intel/opregion.c: Also set vbt_size if size is 0Arthur Heymans
Make sure size vbt_size is initialized. GCC LTO warns about this. Change-Id: I4fcc6c02f898640e9b40d769e1165a4a0fb0fdf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84041 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-08-27mb/dell: Add Latitude E5420 (Sandy Bridge)Nicholas Chin
Mainboard is Krug 14". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A02 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I0283653156083768e1fd451bcf539b4e028589f4 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/dell: Add Latitude E6520 (Sandy Bridge)Nicholas Chin
Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/hp/snb_ivb_desktops: Add 8200 USDT variantRiku Viitanen
Based on autoport. data.vbt extracted from a running system using "intelvbttool --inlegacy" Like with 8200 SFF, OEM firmware write-protects itself, but not the IFD, GBE or ME regions when FDO jumper is applied. Therefore, ME can be shrunken with me_cleaner and BIOS region moved there. Tested: - Internal flashing from the latest endor BIOS (v2.33) - Sandy Bridge Pentium G630 CPU - RAM: 8+0, 8+4, 8+8 1866MHz DDR3 - SeaBIOS 1.16.2, metest86+ v6, coreinfo, nvramcui & tint payloads - libgfxinit txtmode & corebootfb - VGA, DisplayPort (DVI monitor through an adapter) - Gigabit Ethernet - All front and back USB ports - Booting Void Linux - Rebooting - Mini-PCIe WLAN (PCIe) - Both SATA ports: 2.5" & DVD - PS/2 keyboard and mouse - Fan control - TPM settings in SeaBIOS Untested: - Second Mini-PCIe slot (or is it mSATA): connector not present on my unit - MXM graphics Not working: S3: it sleeps for a few seconds and wakes up on its own Change-Id: I1cba7a5e664758eba7ea2ab8a55658b307d1d173 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79583 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/hp: Move compaq_8200_elite_sff_pc into snb_ivb_desktops variantsRiku Viitanen
Tested to still boot, SeaBIOS -> Void Linux Change-Id: I03d57c7e76ccdfccd58b2a6deab4dee87b02503a Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79545 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-26mb/dell: Add Latitude E5520 (Sandy Bridge)Nicholas Chin
Mainboard is Krug 15". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A14 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26mb/dell: Add Latitude E6420 (Sandy Bridge)Nicholas Chin
Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82126 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-26mb/dell: Add Latitude E5530 (Ivy Bridge)Nicholas Chin
Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A21 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26mb/dell: Add Latitude E6530 (Ivy Bridge)Nicholas Chin
Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the vbios obtained using intel_bios_dumper while running version A22 of the vendor firmware, which I then processed using `intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt. This was originally tested and found to be working as a standalone board port in Libreboot, though this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26ec/dell/mec5035: Replace defines with enumsNicholas Chin
Instead of using defines for command IDs and argument values, use enums to provide more type safety. This also has the effect of moving the command IDs to a more central location instead of defines spread out throughout the header. Change-Id: I788531e8b70e79541213853f177326d217235ef2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26nb/intel/haswell: Move SPD addresses to devicetreeKeith Hui
Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy. Patch also covers recently added Z97 boards using Broadwell MRC. Also update util/autoport to match. abuild passes for all affected boards. autoport builds, but otherwise untested. Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-26vc/intel/fsp: Update ADL N FSP headers from v5021.00 to v5132.00KunYi Chen
Update generated FSP headers for ADL-N to MR5(5132_00) Change-Id: I96fccbb92866fbc18c57187628612fda655cd7a7 Signed-off-by: KunYi Chen <kunyi.chen@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 10:04:56 +0000