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2022-01-08sc7180: Increase bootblock size and add pre-RAM TCPA bufferJulius Werner
In order to make SC7180 boards compatbile with some optional Kconfigs, increase the bootblock size a bit and add room for a TCPA log buffer to memlayout. The large pre-RAM CBFS cache wasn't really needed anymore anyway since we switched QcLib to use LZ4 compression. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7321cca9d7b79368115c57f156b8e71657802a41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-08mb/google/herobrine: Add support for audioSrinivasa Rao Mandadapu
Add GPIO configuration for target specific i2s ports. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Boot on herobrine board (no speakers to test yet) Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-07mb/google/herobrine: Initialize EC and TPM devicesShelley Chen
Initialize EC and H1/TPM instances on herobrine devices. BUG=b:182963902 BRANCH=None TEST=Validated on qualcomm sc7280 development board and verified booting on herobrine. Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-07mb/google/brya/var/vell: Add MIPI camera infoShon Wang
Add OVTI8856 information for vell: BUG=b:210801553 TEST=Build and boot on vell Change-Id: I43de859cd0cdd9fe21c16cabfad511ed0b368ee3 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-07mb/google/brya/var/vell: Swap TPM I2C with touchscreen I2CShon Wang
According to the latest schematic for the next build phase, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:210572663 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: If72717a2c073f5b871c3109399f466a04a9d2484 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07mb/google/brya/var/taniks: Change probe for audio 4 channel speakerJoey Peng
Taniks only uses 4 channel speakers. Change the probe name to match SOF topology settings. BUG=b:207808510 TEST=dmidecode -t 11 shows correct audio fw_config. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2986bd212cef47f70dfeedc642a8db3314c947f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPsTim Wawrzynczak
The PMC IPC method that is used for RTD3 support expects to be provided the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore, use the prior patches to update pcie_rp for CPU RPs. Note that an unused argument to pcie_rtd3_acpi_method_status() was also dropped. BUG=b:197983574 TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and inspect the SSDT to see the PMC IPC parameters are as expected for the CPU RP, and the ModPhy power gating code is not found in the AML for the PEG port. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Crawford <tcrawford@system76.com> Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDsTim Wawrzynczak
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe ports, but the UPDs are not set. This patch hooks up those config structs to the appropriate FSP-S UPDs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-07soc/intel/common/blk/memory: Make mixed topo workAngel Pons
When using a mixed memory topology with DDR4, it's not possible to boot when no DIMMs are installed, even though memory-down is available. This happens because the DIMM SPD length defaults to 256 when no DIMM SPD is available. Relax the length check when no DIMMs are present to overcome this problem. Tested on system76/lemp10. Unit boots with and without DIMM installed. Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-01-07mb/google/dedede/var/boten: Add Wifi SAR for bookemStanley Wu
Add new sku id apply for bookem wifi sar table. BUG=b:211705077 TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I1e5bac662fb44cf631ae1453068dec898b6e2607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-07soc/mediatek/mt8186: fix incorrect devapc settingsRunyang Chen
We need to protect debugsys for firmware image without serial console. Original settings for protecting debugsys is wrong which will cause some hardware modules to fail to set their registers correctly. We move the setting from MM_AO_APC to INFRA_AO_APC because the setting of debugsys is defined in INFRA_AO_APC and set the debugsys index to correct value of 94. BUG=b:213125558 TEST=all modules work normally using image without serial console. Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60833 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07soc/mediatek/mt8186: initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7b711755022b5d9767019611151fea65e71edc66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07mb/google/corsola: Enable the SD card readerRex-BC Chen
The Kingler board has an SD card reader connected via USB and can be enabled by setting GPIO EN_PP3300_SDBRDG_X to output mode and activated. BUG=b:211385131 TEST=boot kernel using SD card. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I903731ea4906328b2f0f5a7c6c06bd9c964d24ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60780 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07mb/google/brya/var/redrix: Tune I2c frequencyWisley Chen
Tune the I2c frequency I2C0 - 391 kHz I2C1 - 391 Khz I2C2 - 393 kHz I2C3 - 394.7 KHz I2C5 - 399.6 KHz BUG=b:213298209 TEST=build Change-Id: Id15c5298f8917bac404026f1ecb000fa7f925416 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07mb/google/brya/var/anahera: Fine tune I2C frequencyWisley Chen
Fine tune i2c frequency. I2C0 - 399.6 kHz I2C1 - 391.4 kHz I2C3 - 398.1 kHz I2C5 - 399.9 kHz BUG=b:213295817 TEST=build Change-Id: I9a89820a8d9ae4c9b4ee499e8467426e0670656d Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07mb/google/brya/anahera: Swap TPM I2C with touchscreen I2CWisley Chen
According to the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:212465011 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I1bb1857b4c5b06ca4ad660bf73e0c4df9c376a58 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07drivers/ipmi: Change type of custom_count from int to size_tPaul Menzel
The variable `custom_count` is the number of custom fields, so only holds non-negative values, so change the struct member type from int to size_t. Change-Id: Ic35aafefc870092298523ba2e10adf4fcb687a01 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60790 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07drivers/ipmi: Use correct unsigned int length modifierPaul Menzel
Building an image for OCP DeltaLake with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of char * differs between 32-bit and 64-bit. CC ramstage/drivers/ipmi/ipmi_fru.o src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_chassis_info_area': src/drivers/ipmi/ipmi_fru.c:192:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 192 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 193 | "chassis custom data array.\n", __func__, 194 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_board_info_area': src/drivers/ipmi/ipmi_fru.c:291:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 291 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 292 | "board custom data array.\n", __func__, 293 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_product_info_area': src/drivers/ipmi/ipmi_fru.c:398:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 398 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 399 | "product custom data array.\n", __func__, 400 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int Fix the mismatches in `read_fru_chassis_info_area()` by using the length modifier `z` for size_t as that is what `size_of` yields to. Change-Id: If0c4266b19d56fa88abc397f305154d473ae1a93 Found-by: gcc (Debian 11.2.0-10) 11.2.0 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-07soc/intel/alderlake: Check clkreq overlapKane Chen
In some cases, partner may assign same clkreq on more than one devices. This could happen when one device is in baseboard dev tree and another one is in override dev tree. This change adds a clkreq overlap check and shows a warning message TEST=On brya, assigned one clkreq to 2 devices and found the warning message Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-07mb/google/brya/anahera{4es}: Correct WWAN power sequenceWisley Chen
Correct the WWAN power sequence to meet spec BUG=b:213021172 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Iab221fd03c637c82f6ce5c8278d432decf1b30c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07mb/google/brya/anahera{4es}: Correct SSD power sequenceWisley Chen
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:213021171 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I66345d985f4db4f13b23c0a21c179835908b6574 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-07ec/starlabs/merlin: Unify EC and CMOS namesSean Rhodes
End all CMOS variable with a C and EC variables with an E. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie0fab6b9dcd805f7b8c9bf8f14b0a799d8f396c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-07soc/amd/common/block/include/lpc: add comment about RANGE_UNIT valuesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22f3485ec81f76af7e0e96b7c1271d5ccf52e701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-07soc/amd/common/lpc/espi_util: move register definitions to header fileFelix Held
Define the register offsets and bits in a separate header file instead of in the middle of the .c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-07soc/amd/common/block/espi: use lower case hex digits in definitionsFelix Held
coreboot uses lower case hex digits instead of upper case ones. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0955db7afd101ab522845d5911ff971408e520e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60769 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07soc/amd/common/lpc/espi_util: handle espi_get_configuration errorFelix Held
In espi_wait_channel_ready the return value of espi_get_configuration didn't get checked before. In the case of the espi_send_command call in espi_get_configuration returning CB_ERR, espi_get_configuration didn't write to the local config variable, so if this happens in the first pass of the do-while loop, the following espi_slave_is_channel_ready call would use the uninitialized local config variable as parameter. Fix this by checking the return value of espi_get_configuration. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-07mb/google/brya/var/brask: Change TPM I2C to I2C1Zhuohao Lee
The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch moves the TPM I2C setting from the board layer to the baseboard and fixes the TPM I2C bus assignment. BUG=b:211886429 TEST=build pass Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60439 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-06mb/google/herobrine: Fix board idShelley Chen
The board id assignment CL (CB:56642) landed after BOARD_GOOGLE_HEROBRINE has been deprecated to BOARD_GOOGLE_HEROBRINE_REV0 (CB:60284). Fix it to accomodate for the GOOGLE_HEROBRINE_REV0 board updates. BUG=b:211644878 BRANCH=None TEST=built all variants of herobrine to make sure it compiles. For reference: ============= CB:56642: commit 8b63dac06184e56ce40d82d982e983ac79163551 Author: Ravi Kumar Bokka <rbokka@codeaurora.org> Date: Tue Jul 27 19:29:18 2021 +0530 google/herobrine: configure gpio to detect board ID ============= CB:60284: commit 8bdbe23a93008597d99472747ba3415617f8c074 Author: Shelley Chen <shchen@google.com> Date: Tue Dec 21 13:17:33 2021 -0800 mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0 ============= Change-Id: I6dab994e65eadff303eb88a63b8dd81e19694678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-06mb/google/guybrush/var/dewatt: update USB3 settings for passing SIKenneth Chan
Update tx/rx term control to 3 for passing USB3 port 0/1 SI. b:199468920 TEST= emerge-guybrush coreboot; build and pass USB3 SI. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I637207d7c657f6dd71d70694f9a5fb35f8294b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-06mb/google/brya/var/anahera{4es}: Add Chrome OS privacy screen _HIDTim Wawrzynczak
Similar to commit 0167f5adb (mb/google/redrix: Add _HID for privacy screen device), add the same _HID to the privacy screen device. Change-Id: I58ad538dfaf602e3f4afb98d1a25d52753a15d93 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2022-01-06soc/intel/alderlake: Add minimal ACPI support for PEG portsTim Wawrzynczak
Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak
The PMC IPC method used to enable/disable PCIe srcclks uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak
The PMC IPC method used to enable/disable PCIe clk sources uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06mb/google/brya/var/agah: Add new memory supportTony Huang
Do initial memory support for project agah BUG=b:210970640 TEST=FW_NAME=agah emerge-brya coreboot Change-Id: Iaeea12a9dd8110a499b5df4de89dc1f74b88a580 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-06mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changedKenneth Chan
Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3354766. Update to matched id for audio work normal. 1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2. BUG=b:210542422 TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I542f886fe63205777837d7146169177b043cc5f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-06mb/google/brya: Create agah variantTony Huang
Create the agah variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:210970640 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AGAH Change-Id: I6adcf4e8010969cf185513d68bb1b76ea08194c7 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-06soc/intel/common/gpio: Skip GPP pad lock config if config is not setSubrata Banik
Don't perform GPP lock configuration if SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config is not selected. This patch fixes a compilation issue when APL/GLK boards are failing while gpio_lock_pads() function is getting called from IA common gpio block. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-06soc/intel/common/gpio: Modify pad_config.pad type from `int` to 'gpio_t'Subrata Banik
This patch modifies struct pad_config.pad type from `int` to 'gpio_t' as pad offset inside GPIO community is unsigned type and also to maintain parity with `struct gpio_lock_config.pad` type. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-06soc/intel/common/gpio: Rename struct gpio_lock_config.gpio to .padSubrata Banik
This patch renames struct gpio_lock_config variable `gpio` to `pad`, to represent the pad offset within the GPIO community. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6bed99c401435c96c9543f99406a934d7141c575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-06soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik
This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Alder Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - RSMRST for GPD/Reserved for GPP - (Value 11) Hence, created two different reset types for `GPP` and `GPD`. Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET(). BUG=b:213293047 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-06soc/mediatek/mt8186: Increase CBFS_MCACHE size to 8KiBRex-BC Chen
The current CBFS mcache size (roughly 7KiB) is insufficient for mt8186, so we need to increase it by 1KiB (and decrease the stack by 1KiB). Error logs: CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size! CBFS: mcache @0x0010e004 built for 63 files, used 0xde4 of 0xdfc bytes BUG=b:202871018 TEST=no cbfs error logs. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60529 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-06mb/google/corsola: Configure audioRex-BC Chen
According schematics, we configure audio by turning on setting of audio power and selecting I2S pin-mux. Schematics references: kingler: schematic_kingler_proto0_gerber_20211115.pdf krabby: crab_proto 0_20211112_final.pdf BUG=b:204164695 TEST=Verified by CLI command(badusbbeep/devbeep) on kingler and krabby Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Change-Id: Ia6374d0e5535b7cff4df8759312786fef8b94b6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-01-05mb/google/volteer/var/delbin: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:204523176 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ieef638f78edd3428e572a76f06fb9c8757278971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-05mb/google/brya/var/taeko:Remove duplicate DB_SD fw_config fields.Joey Peng
Since fw config fields for DB_SD can share the same driver, we will remove the duplicate fields DB_SD_GL9750 and DB_SD_RTS5232S. BUG=b:212240358 TEST=emerge-brya coreboot and can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: If7814c35f63fd6fa27195d448c4d51fc980aaa9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-05mb/google/sarien: Add VBT extracted from Chrome OSPaul Menzel
The VBT is extracted from Chromium OS in developer mode with the device running firwmare . $ sudo dmesg | grep ' DMI:' [ 0.000000] DMI: Dell Inc. Sarien/Sarien, BIOS Google_Sarien.12200.99.0 07/29/2020 $ sudo cbmem -1 coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 bootblock starting (log level: 8)... […] coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 ramstage starting (log level: 8)... […] CBFS: Locating 'vbt.bin' CBFS: Found @ offset 614c0 size 4a0 Found a VBT of 4608 bytes after decompression […] $ sudo cp /sys/kernel/debug/dri/0/i915_vbt vbt.bin Using the Chrome OS recovery image, Matt DeVillier verified, that the Sarien VBT is identical to Arcada, so add the VBT for all variants. Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05mb/google/sarien/Kconfig: Remove blank line at beginningPaul Menzel
Change-Id: I0410be48f360bdd00e4ed7599cbee405915344b9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-05mb/starlabs/labtop: Remove display from devicetreeSean Rhodes
Remove display from devicetree as Intel's brightness controls are not used on this platform. This solves the below errors appearing in dmesg: No Local Variables are initialized for Method [_BCL] No Arguments are initialized for method [_BCL] Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icf2f2fa33abd11952c888c9502d1d5ef1ad6544f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-05src/northbridge: Remove unused <delay.h>Elyes HAOUAS
Change-Id: I5449feeb65c49c79bc7657a1c3777a0f128a13b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-05src/soc/amd: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Iefb37d28c7f13563fa652cd6b2f661f462a3a32e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-05src/soc/intel: Remove unused <delay.h>Elyes HAOUAS
Change-Id: Id8e6221a9801d5198171dc9cd564000d19720a42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05src/soc/mediatek: Remove unused <delay.h>Elyes HAOUAS
Change-Id: I414ad3824819f441f316567795999ed9539cba7b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-05src/southbridge: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: If7751b0e7d222979973518f57b310f5e2fe2bc25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-05soc/mediatek: Remove unused <string.h>Elyes HAOUAS
Change-Id: I8f88541dce457e978a2cbea036d4f6eae387963f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-05soc/amd: Remove unused <string.h>Elyes HAOUAS
Change-Id: Ibd3e7a62a2e833017f550eddd915b7dfb539d019 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-05device/dram/lpddr4.c: Remove unused <string.h>Elyes HAOUAS
Change-Id: Iba3135178f2d6021702971e4d887e9b4f8afeb76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-05src/southbridge: Remove unused <string.h>Elyes HAOUAS
Change-Id: Idc0cd9d6865cd9c1b95e6c838795cce9dbc643a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-05soc/intel: Remove unused <string.h>Elyes HAOUAS
Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05src/drivers/wifi/generic/smbios.c: Remove unused <string.h>Elyes HAOUAS
Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: I2a6c5b67af1d2544159e92d4b8c06cc1f5504bd2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-05mb/google/brya/var/primus: Fix some GPIO programmingAriel Fang
After checking them against schematics, a few unused GPIOs that were inherited from the baseboard were missed, so this CL programs them as PAD_NC. GPP_B2 => non-use GPP_B15 => non-use (for FPR) GPP_D3 => non-use (Test point) GPP_E21 => non-use (for LCLW Detect) BUG=b:211721639 TEST= USE="project_primus" emerge-brya coreboot Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-05mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screenSeunghwan Kim
Touch screen IC couldn't wake up after rebind with current 120 ms delay after reset since the HID would be activated after 200 ms from reset. This change increases the reset_delay_ms for touch device to 200 ms to wait for the touch HID to be ready. BUG=b:204950000 BRANCH=dedede TEST=Verified that TSP IC could wake up after rebind Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I34cbc82e2d691266389d498e77d8389cdee23efe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05mb/google/brya/(anahera,primus): Use eNEM for CAR by defaultSubrata Banik
More Brya variants like Anahera and Primus have migrated to use Alder Lake QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR by default for these variants. BUG=b:168820083 TEST=Able to build and boot primus variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I65d12de08adf85140976e1a7659ad7b684aa75c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-05mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AA-MGCRZhi Li
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for Samsung K4U6E3S4AA-MGCR. BUG=b:211950312 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ic436db8fe3ef6fb8379ec629b128c05c691ea6fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
2022-01-05mb/google/herobrine: Initialize `pins` to fix the compilation issueSubrata Banik
Fix compilation issue introduced with commit 8b63dac0 (google/herobrine: configure gpio to detect board ID) by initialising the gpio pins. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I084fec777b56f402efb3b04a1d358cd5b0891846 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-01-05mb/starlabs/labtop: Replace leading whitespace with tabSubrata Banik
Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d7324148ba182d0317b1f64e39f04a8a55fe79b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-05google/herobrine: configure gpio to detect board IDRavi Kumar Bokka
BUG=b:182963902, b:193807794 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-04mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0Shelley Chen
Deprecating Herobrine Rev0 board. The next board is very different from the Rev0 board (ie: Most GPIOs have been remapped). Deprecating and reusing the GOOGLE_BOARD_HEROBRINE Kconfig for next board and reslotting the old GOOGLE_BOARD_HEROBRINE source under GOOGLE_BOARD_HEROBRINE_REV0 config. Want to keep the code around in case somebody needs it but we can remove this code in future after we recall all the Rev0 devices. Also updating the remapped GPIOs to match those of the current herobrine board. BUG=b:211644878 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I67a0b282710031b927ce9022c7c535bd8d4ca1aa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2022-01-04mb/google/brya/var/kano: Add stylus probeDavid Wu
Kano has non-stylus sku. Add a FW_CONFIG field to indicate stylus presence and add a probe statement to the devicetree for the corresponding device. BUG=b:208179467 TEST=non-stylus doesn't register garage driver. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24839c39280185a6d649a82dd9f025ee305c2eed Reviewed-on: https://review.coreboot.org/c/coreboot/+/60389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/brya/var/kano: Enable stylus pen powerDavid Wu
Set GPP_D16 (PEN_PWR_EN) to output high. BUG=b:195853169 TEST=build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I25b6d1a40ed0939b303a03984cb0087fb6cab4d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/brya: Add new baseboard nissa with variants nivviks and nereidReka Norman
Add a new baseboard for nissa, an Intel ADL-N based reference design. Also, add variants for the two reference boards, nivviks and nereid. This commit is a stub which only adds the minimum code needed for a successful build. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-04mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMCKevin Chang
Taeko will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:211914322 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend: chromium:3358662 Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04src/mb: Remove unused <string.h>Elyes HAOUAS
Change-Id: I5f2710b2034882a24a041d99e37ec364193d85e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-04security/memory/memory.c: Include 'stdbool' instead of 'stdint'Elyes HAOUAS
Change-Id: I4eac157c8b48c1c10178bb84822b6462c245deca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-04soc/intel/common/acpi/pep: Use correct size_t length modifierPaul Menzel
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of size_t differs between 32-bit and 64-bit. CC ramstage/soc/intel/common/block/acpi/pep.o src/soc/intel/common/block/acpi/pep.c: In function 'read_pmc_lpm_requirements': src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~ | | | size_t {aka unsigned int} src/soc/intel/common/block/acpi/pep.c:58:62: note: format string is defined here 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~~^ | | | long unsigned int | %u src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~ | | | size_t {aka unsigned int} src/soc/intel/common/block/acpi/pep.c:58:71: note: format string is defined here 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~~^ | | | long unsigned int | %u The variables `i` and `j` are of type size_t, so use the corresponding length modifier `z`. Fixes: 2eb100dd ("soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM") Change-Id: I27bce0a6c62b1c1ebbca732761de2f59b042a5d4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04soc/intel/common: irq: Use correct size_t length modifierPaul Menzel
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of size_t differs between 32-bit and 64-bit. CC ramstage/soc/intel/common/block/irq/irq.o src/soc/intel/common/block/irq/irq.c: In function 'assign_fixed_pirqs': src/soc/intel/common/block/irq/irq.c:186:90: error: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 186 | printk(BIOS_ERR, "ERROR: Slot %u, pirq %u, no pin for function %lu\n", | ~~^ | | | long unsigned int | %u 187 | constraints->slot, fixed_pirq, i); | ~ | | | size_t {aka unsigned int} CC ramstage/soc/intel/common/block/gspi/gspi.o CC ramstage/soc/intel/common/block/graphics/graphics.o CC ramstage/soc/intel/common/block/gpio/gpio.o CC ramstage/soc/intel/common/block/gpio/gpio_dev.o The variable `i` is of type size_t, so use the corresponding length modifier `z`. Fixes: b59980b54e ("soc/intel/common: Add new IRQ module") Change-Id: I09f4a8d22a2964471344f5dcf971dfa801555f4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane ParameterKevin Chiu
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level" and "Disconnect Threshold Adjustment" per port: port#0: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 port#1: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 port#4: COMPDISTUNE0: 0x1->0x6 / TXVREFTUNE0: 0x3->0xE port#5: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9 BUG=b:203049656 BRANCH=guybrush TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. pass USB eye diagram verification Change-Id: If5a6563e93bfa6beb529a5593fcc9124ce62d77f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-04mb/google/brya/var/taeko: Modify DPTF setting for taekoKevin Chang
The new settings from the thermal team improve performance mainly with respect to fan control settings. BRANCH=None BUG=b:212210824 TEST=Built and tested on taeko board Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I2d5c9b6dff87a2e8897d74f3be89c965db22fe16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next buildKevin Chang
Taeko is going to exchange i2c port for touchscreen and cr50. BUG=b:211911780 TEST=build pass Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/brya/var/kano: Set vGPIO reset typeDavid Wu
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207527331 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/brya/anahera: Add new memory supportWisley Chen
Add the new memory support: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL Hynix H54G56CYRBX247 Samsung K4UBE3D4AB-MGCL BUG=b:212328327 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ib08a1348333accdbb7551ef428d8d130b621dd9f Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/brya/var/redrix: Add new memory supportWisley Chen
Add the new memory support: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL Hynix H54G56CYRBX247 Samsung K4UBE3D4AB-MGCL BUG=b:212330664 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I32491f86813c8e6566774d4b3d7d82295f906bd3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/google/brya/var/vell: update overridetree for DPShon Wang
update override devicetree for type-c display based on schematics BUG=b:209489126 TEST=emerge-brya coreboot Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: Icd2f5de38df0eb89fb92ea2abe25851c0d6ec53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04mb/starlabs/labtop: Enable I2C4Sean Rhodes
Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from configuring anything regarding I2C4 (e.g. GPIOs). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-04starlabs: Convert EC_GPE_SCI to KconfigSean Rhodes
Convert EC_GPI_SCI to Kconfig option with default value of 0x50 that is used by most boards. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-04nb/intel/i945/raminit.c: Set "integrated_graphics" as boolElyes HAOUAS
"integrated_graphics" is already used as a "bool" at line #2128. So set it as "bool". Change-Id: Ic5286e691c312e8e44bbbd8e782fdfd4a13cb60f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-04commonlib: Add endian definitions for macOSAlex James
macOS has never defined the usual endian(3)/byteorder(9) byte-swapping functions. This change implements these byte-swapping functions using the OSSwap functions, which provide identical functionality. This was tested on macOS 10.15.7. Change-Id: I44d59869a4420030f3ce26118175304c680d57a1 Signed-off-by: Alex James <theracermaster@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-04mb/google/guybrush/var/dewatt: disable unused PCIe clock settingKenneth Chan
GPP_CLK1 is used for SD and GPP_CLK2 is for WWAN on guybrush. Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt. BUG=b:211566312 TEST=emerge-guybrush coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: If449453bc60ed41e104346429babc06a73acef64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-04sb/intel: Use `bool` for PCIe coalescing optionAngel Pons
Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-04mb/asus/p2b: list all unused Super I/O resourcesKeith Hui
Some Super I/O resources were unused and not listed, causing warnings during resource allocation. Suppress these warnings by setting them to zero. Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41459 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-03mb/google/dedede/var/bugzzy: Initialize display signals on user modeSeunghwan Kim
Bugzzy uses panel-built-in touch screen, it needs to set panel power and reset signal to high for touch screen to work. On user mode, coreboot doesn't initialize graphics since there is no screen display before OS. So we would add a WA to initialize required signals on user mode. It takes under 30 ms delay on booting time. BUG=b:205496327 BRANCH=dedede TEST=Verified touch screen worked with test coreboot and test touch screen 028D firmware Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db Reviewed-on: https://review.coreboot.org/c/coreboot/+/60190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-03mb/google/brya/var/brask: Change I2C/DDC signalsRory Liu
The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14, I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12. BUG=b:206602609 TEST=build pass Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-01-03drivers/intel/fsp: Map FSP debug level to coreboot console levelSubrata Banik
This patch maps coreboot console level to FSP debug level. This is useful to suppress MRC (FSP-M) debug logs. Callers have to select HAVE_DEBUG_RAM_SETUP config to get verbose MRC debug log, Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-03soc/intel/alderlake: Add option to make MRC log silentSubrata Banik
Typically, FSP-M aka MRC debug log level defaults to `3` meaning prints all `Load, Error, Warnings & Info` messages. Sometimes it's too much information to parse even when users aren't required to have such detailed information hence, implement `fsp_map_console_log_level()` that maps coreboot console log level to FSP-M debug log level and suppress verbose MRC debug messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and then the user can enable `DEBUG_RAM_SETUP`. TEST=FSP-M debug log suggested default `SerialDebugMrcLevel` UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP` and user to select `DEBUG_RAM_SETUP` config to override `SerialDebugMrcLevel` UPD value to '5' aka verbose. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-03console: Make get_log_level a public functionSubrata Banik
Other drivers may need to know the coreboot log level hence, export this function rather than marking it static. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-03mb/google/brya/var/gimble: Update Slow Slew RateMark Hsieh
- Set slow slew rate VCCIA and VCCGT to 8 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2022-01-02drivers/intel/fsp2_0/notify.c: Group per-phase dataAngel Pons
Group all data specific to each notify phase in a struct to avoid redundant code. Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-02drivers/intel/fsp2_0/notify.c: Clean up some cosmeticsAngel Pons
Sort includes alphabetically, drop spaces after type casts and unbreak some long lines that are less than 96 characters long. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-02drivers/intel/fsp2_0: Print return value when dyingAngel Pons
When coreboot goes to die because FSP returned an error, log the return value in the message printed by `die()` or `die_with_post_code()`. Change-Id: I6b9ea60534a20429f15132007c1f5770760481af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-02soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_modeSubrata Banik
Since TGL `spi_protection_mode` bit replaces the previous `manufacturing mode` without changing the offset and purpose of this bit. This patch renames to `manufacturing mode` aka `mfg_mode` to maintain the parity with other PCHs as part of IA-common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-02soc/intel/common/blk/crashlog: Drop some new linesSubrata Banik
Remove unnecessary new lines in crashlog code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0920f563d6fdf9414eab86796cedcac83173dba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`Felix Singer
Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 23:11:57 +0000