diff options
| author | Paul Menzel <pmenzel@molgen.mpg.de> | 2022-01-03 14:58:43 +0100 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-05 17:44:58 +0000 |
| commit | 6f1435e0a9d27cda06e694bd2d40993b0f2a116b (patch) | |
| tree | 15e9de773fbfe6a61c8b36015ddef3669efdbe6f /src | |
| parent | 1ef30cbf7580e2548e6c009f38ee9aad4108271c (diff) | |
mb/google/sarien: Add VBT extracted from Chrome OS
The VBT is extracted from Chromium OS in developer mode with the device
running firwmare .
$ sudo dmesg | grep ' DMI:'
[ 0.000000] DMI: Dell Inc. Sarien/Sarien, BIOS Google_Sarien.12200.99.0 07/29/2020
$ sudo cbmem -1
coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 bootblock starting (log level: 8)...
[…]
coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 ramstage starting (log level: 8)...
[…]
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 614c0 size 4a0
Found a VBT of 4608 bytes after decompression
[…]
$ sudo cp /sys/kernel/debug/dri/0/i915_vbt vbt.bin
Using the Chrome OS recovery image, Matt DeVillier verified, that the
Sarien VBT is identical to Arcada, so add the VBT for all variants.
Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/sarien/Kconfig | 6 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/data.vbt | bin | 0 -> 6144 bytes |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 42c3aba334..d58f64d040 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 @@ -91,4 +92,9 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH +# Override the default variant behavior, since the data.vbt is the same +# for all variants. +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" + endif # BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/google/sarien/data.vbt b/src/mainboard/google/sarien/data.vbt Binary files differnew file mode 100644 index 0000000000..f9c498e45c --- /dev/null +++ b/src/mainboard/google/sarien/data.vbt |