coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-05-01	sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-12-19	src/southbridge: Remove unused <stdlib.h>	Elyes HAOUAS
2019-10-30	src/southbridge: change "unsigned" to "unsigned int"	Martin Roth
2019-08-21	southbridge/intel: Tidy up preprocessor and headers	Kyösti Mälkki
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-01-06	device: Use pcidev_path_on_root()	Kyösti Mälkki
2019-01-06	device: Use pcidev_on_root()	Kyösti Mälkki
2018-08-16	sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5	Stefan Tauner
2018-08-14	sb/intel/i82801[ij]x: use (more) RCBA register names instead of magic numbers	Stefan Tauner
2018-05-24	sb/intel/i82801ix: Get rid of device_t	Elyes HAOUAS
2017-07-16	southbridge/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2016-12-07	PCI ops: MMCONF_SUPPORT_DEFAULT is required	Kyösti Mälkki
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-08-12	gm45: Move S3 detection to enable stage.	Vladimir Serbinenko
2013-09-10	intel/i82801ix: remove explicit pcie config accesses	Kyösti Mälkki
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-11-27	intel/i82801ix: new southbridge, ICH9	Patrick Georgi