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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-26 08:35:09 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-10 18:20:34 +0200 |
| commit | 9b143e1474f425b6d81bf6490d67baf26d03c437 (patch) | |
| tree | a741e62aab6d51d33ddc74046233948f8841c441 /src/southbridge/intel/i82801ix/i82801ix.c | |
| parent | 35a7249183d2e791eb00b41332e6277c504cdd49 (diff) | |
intel/i82801ix: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3809
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix/i82801ix.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index e35487f62e..0fe7d20f05 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -27,6 +27,10 @@ #include <console/console.h> #include "i82801ix.h" +#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#error ICH9 requires CONFIG_MMCONF_SUPPORT_DEFAULT +#endif + typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_device(device_t dev) @@ -66,13 +70,9 @@ static void i82801ix_pcie_init(const config_t *const info) printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } -#if CONFIG_MMCONF_SUPPORT - reg32 = pci_mmio_read_config32(pciePort[i], 0x300); - pci_mmio_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); - pci_mmio_write_config8(pciePort[i], 0x324, 0x40); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + reg32 = pci_read_config32(pciePort[i], 0x300); + pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_write_config8(pciePort[i], 0x324, 0x40); } if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { @@ -87,13 +87,9 @@ static void i82801ix_pcie_init(const config_t *const info) for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ -#if CONFIG_MMCONF_SUPPORT - reg32 = pci_mmio_read_config32(pciePort[i], 0x300); + reg32 = pci_read_config32(pciePort[i], 0x300); reg32 |= 0x3 << 16; - pci_mmio_write_config32(pciePort[i], 0x300, reg32); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + pci_write_config32(pciePort[i], 0x300, reg32); } /* Set slot implemented, slot number and slot power limits. */ |