| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-08-16 | sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5 | Stefan Tauner |
| 2018-08-14 | sb/intel/i82801[ij]x: use (more) RCBA register names instead of magic numbers | Stefan Tauner |
| 2018-05-24 | sb/intel/i82801ix: Get rid of device_t | Elyes HAOUAS |
| 2017-07-16 | southbridge/intel: add IS_ENABLED() around Kconfig symbol references | Martin Roth |
| 2016-12-07 | PCI ops: MMCONF_SUPPORT_DEFAULT is required | Kyösti Mälkki |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-08-12 | gm45: Move S3 detection to enable stage. | Vladimir Serbinenko |
| 2013-09-10 | intel/i82801ix: remove explicit pcie config accesses | Kyösti Mälkki |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2012-11-27 | intel/i82801ix: new southbridge, ICH9 | Patrick Georgi |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |