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2023-04-21soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of offMartin Roth
When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=b:277997811 TEST=Build Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74527 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of offMartin Roth
When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=None TEST=Don't see the "PCI: Leftover static devices:" warning for these in the boot console. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74526 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-21soc/intel/meteorlake: Add VPU into the DMAR SATC tablezhaojohn
This change adds the VPU into the DMAR SATC table in order to support the VPU IO virtualization. BUG=None TEST=Enabled the VPU, booted to kernel and verified that DMAR SATC table includeded the VPU entry. Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-21soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() functionSubrata Banik
This patch refactors cse_fw_sync() function to include timestamp associated with the CSE sync operation.This effort will ensure the SoC code just makes a call into the cse_fw_sync() without bothering about adding timestamp entries. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() functionSubrata Banik
This patch refactors sleep type check inside ramstage_cse_fw_sync() to avoid additional logic while performing cse_fw_sync() operation. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icc9e5ad8954c6203fc4762aa976bba7e8ea16159 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-04-21soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic673deb725a541c7535ae769f589cd82ea42a561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gbFelix Held
Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gbFelix Held
Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35895340f6e747e2f5e1669d40f40b201d8c1845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21Drop unused include <version.h>Kyösti Mälkki
Change-Id: I7d0718b5d2e0dd16eb90f63dd9d33329a2d808ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21soc/intel/braswell: Replace <build.h> with <version.h>Kyösti Mälkki
To use generated build.h one should have had a pre-requisite in the Makefile. Reference coreboot_build_date from lib/version.c instead. Change-Id: Icd6fa2ddf8aa584b0f51ba130592f227bbdad975 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21include/cpu/amd/mtrr: rename functions to get top of memory regionsFelix Held
Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and get_top_of_mem_above_4g to make it clearer what those functions return. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21soc/amd/phoenix: Update XHCI eventsJon Murphy
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI to allow for XHCI events to be logged. BUG=b:277273428 TEST=builds Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74280 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21soc/amd/phoenix/xhci: Correct counting of xhci_sci_sourcesFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iabba97e003d1a5140c98e3fc5a3496f66f8795c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-20soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM methodCliff Huang
srcclk_pin is 0-based and '0' is a valid clock source number. If srcclk_pin is set to -1, then the clock will not be disabled in D3. Therefore, clock source gating method should not be generated. BUG=b:271003060 BRANCH=firmware-brya-14505.B TEST=Boot to OS and check that rtd3 ACPI entries are generated as expected. For those PCI devices with RTD3 driver whose srcclk_pin to 0, the RTD3 entries should not be missing due to check error. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73889 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-20soc/intel/meteorlake: Send CSE EOP Async CMD earlySubrata Banik
This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample which causes idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/rex sku to ChromeOS and observed ~100ms of boot time savings (across warm and cold reset scenarios) Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-20soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPRFelix Held
Parts of this file were still a copy of the file from the Mendocino SoC, so update the file to match the PPR #57019 Rev 3.03 and the chipset devicetree of the Phoenix SoC. Phoenix has 4 GFX/GPP PCIe bridges/ports, the numbering scheme of the GPP PCIe bridges/ports was changed so that the numbers match the device and function numbers, and there are new device functions for the IPU and the USB4 controller and router devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74565 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/amd/phoenix/devicetree: drop i2s_ac97 deviceFelix Held
In both PPR #57019 Rev 3.03 and PPR #57396 Rev 3.04, the i2s_ac97 function on bus C isn't mentioned any more and the microarchitecture specification document for this SoC also doesn't mention it, so remove it from the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibd115953bdd60e1dfcc79797b0c2158e5d861636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74564 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_regFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e067f6fb2bab66d9b2f6965636845dfd8b7cacd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-20soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is currently unused. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I08930ef84438140a13df74900570b126088bd1cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74478 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/alderlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is currently unused. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2590e8dec0a308e0dc3d467cb3dd2bb97e877492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74477 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep stateSean Rhodes
Use D3COLD_SUPPORT Kconfig option to set the maximum support sleep state. Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it is not, it will break S3 exit. When D3COLD_SUPPORT is not enabled, return `3` (D3Hot). This fixed S3 exit on both TGL and ADL. Tested on StarBook Mk V and Mk VI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I578d4933b6144aec79fe0b2eb168338ef82c0b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74406 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-20soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20device: Move D3COLD_SUPPORT symbolSean Rhodes
Move D3COLD_SUPPORT to device, so it can be used by multiple SOCs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie92736458ab95374c51346107665dc0fd1e653a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74404 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOSSubrata Banik
The Intel FSP used on ChromeOS platform has dropped the `CpuFeaturesPei.ffs` module to opt for coreboot running this additional feature programming on BSP and APs. TEST=Able to build and boot google/rex without any boot regression. Please refer to the boot time and SPI flash savings after dropping the FSP feature programming: Boot time savings=10ms SPI Flash size savings=34KB Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Reviewed-on: https://review.coreboot.org/c/coreboot/+/74168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-19soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMAKarthikeyan Ramasubramanian
CBFS library performs memory mapped access of the files during loading, verification and de-compression. Even with MTRRs configured correctly, first few file access through memory map are taking longer times to load. Update the SPI DMA driver to load the files into CBFS cache, so that they can be verified and de-compressed with less overhead. This saves ~60 ms in boot time. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe ~60 ms improvement with the boot time. Performing additional test to confirm there are no regressions. Before: ======= 970:loading FSP-M 15:starting LZMA decompress (ignore for x86) 760,906 (60,035) 16:finished LZMA decompress (ignore for x86) 798,787 (37,881) 8:starting to load ramstage 17:starting LZ4 decompress (ignore for x86) 1,050,093 (13,790) 18:finished LZ4 decompress (ignore for x86) 1,054,086 (3,993) 971:loading FSP-S 17:starting LZ4 decompress (ignore for x86) 1,067,778 (3,313) 18:finished LZ4 decompress (ignore for x86) 1,068,022 (244) 90:starting to load payload 17:starting LZ4 decompress (ignore for x86) 1,302,155 (11,285) 18:finished LZ4 decompress (ignore for x86) 1,303,938 (1,783) After: ====== 970:loading FSP-M 15:starting LZMA decompress (ignore for x86) 709,542 (12,178) 16:finished LZMA decompress (ignore for x86) 739,379 (29,837) 8:starting to load ramstage 17:starting LZ4 decompress (ignore for x86) 1,001,316 (12,368) 18:finished LZ4 decompress (ignore for x86) 1,001,971 (655) 971:loading FSP-S 17:starting LZ4 decompress (ignore for x86) 1,016,514 (3,031) 18:finished LZ4 decompress (ignore for x86) 1,016,722 (207) 90:starting to load payload 17:starting LZ4 decompress (ignore for x86) 1,244,602 (10,313) 18:finished LZ4 decompress (ignore for x86) 1,244,831 (228) Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-04-19soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-17cpu,soc/intel: Separate single SSDT CPU entryKyösti Mälkki
Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-16soc/intel/jasperlake: Hook up GMA ACPI brightness controlsMatt DeVillier
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on google/magpie. Backlight controls work on Windows 10 and Linux 6.1. Change-Id: Iaa9872cd590c3b1298667cc80354ed3efd91c6c8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-15soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.cSubrata Banik
The patch moves API that gets the CSE FW partition information into CSE Lite specific file aka cse_lite.c because the consumer of this API is the cse_lite specific ChromeOS devices hence, it's meaningful to move the cse lite specific implementation inside cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74382 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/tigerlake: Enable early caching of RAMTOP regionLean Sheng Tan
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/alderlake: Enable early caching of RAMTOP regionLean Sheng Tan
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot Starlab ADL laptop to OS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73736 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-15soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi
This patch adds CPU ID for B0 stepping (aka ES2). DOC=#723567 TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log. Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/baytrail: Make acpi_madt_irq_overrides() staticKyösti Mälkki
Change-Id: Id362e023358054df2c4511fd108c313da868306d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74325 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPICKyösti Mälkki
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. For asus/p2b, this adds MADT LAPIC entries, even though platform has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates the MADT, including an entry for LAPIC address. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-14cpu,soc/intel: Use acpigen_write_processor_device()Elyes Haouas
Use acpigen_write_processor_device() instead of deprecated acpigen_write_processor(). Change-Id: I1448e0a8845b3a1beee0a3ed744358944faf66d8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72488 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_configLean Sheng Tan
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB that was caused by the API change in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. This patch removes the broken API function and also adds package_id log print same as previous commit mentioned above. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74436 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-14soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)Subrata Banik
This patch avoids cannonlake base config to select eNEM for CAR by default. Rather allow other SoC config to choose the applicable CAR mode between eNEM and NEM. CML and WHL select eNEM whereas CFL decided to use NEM for CAR setup. Here is some background about why CFL SoC platform decided to choose NEM over eNEM: It was found that some coffeelake CPUs like Intel i3 9100E fail to enter CAR mode because some MSR used by NEM enhanced are lacking. According to the Intel SDM CPUID.EAX=07h.ECX=0 reg EBX[12 or 15] should indicate the presence of IA32_PAR_ASSOC and CPUID.EAX=10h.ECX[1 or 2] reg ECX[2] should indicate IA32_L3_QOS_CFG and IA32_L2_QOS_CFG respectively but even on a Intel coffeelake CPU that works with the NEM_ENHANCED these CPUID bits are all 0 so there is no way of knowing whether NEM_ENHANCED will work at runtime. Instead just always use regular NEM. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/mediatek: Add assert for regulator VRF12Cong Yang
Add assert for MT6366_VRF12, define a constant macro for 1200000. BUG=none TEST=build board starmie with mt8186. Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74394 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14soc/mediatek: Add support for regulator VIO18Cong Yang
To provide power to MIPI panel STA_HIMAX83102_J02, add support for regulator VIO18. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74341 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
2023-04-14soc/intel/xeon_sp: Don't sort struct device cpus for numaArthur Heymans
Currently the xeon_sp code reassigns struct devices apic_id so that srat entries can be added in a certain order. This is not a good idea as it breaks thread local storage which contains a pointer to its struct device cpu. This moves the sorting of the lapic_ids to the srat table generation and adds the numa node id in each core init entry. Now it is done in parallel too as a bonus. Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14soc/intel/meteorlake: Replace assert with error messageKapil Porwal
Avoid asserts related to CNVi UPDs which are not boot critical. Instead, add error messages which are more helpful in identifying the issue. BUG=none TEST=Boot to the OS on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74370 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-14soc/intel/common: Fix acpigen use for processor DeviceKyösti Mälkki
Change-Id: Ib4e21732ac31076a1a97a774e03c8466d17c5f29 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/amd: Clarify ACPI _PRT entry generationKyösti Mälkki
The reference to a constant FCH IOAPIC interrupt count used with GNB IOAPIC was a bit obscure. Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-13soc/intel/cmd/block: Implement an API to get firmware partition detailsDinesh Gehlot
This patch retrieves details of a specified firmware partition table. The information retrieved includes the current firmware version and other information about the firmware partition. The patch communicates with the ME using the HECI command to acquire this information. BUG=b:273661726 Test=Verified the changes for ISH partition on nissa board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-13soc/intel/meteorlake: Hook up UPD CnviWifiCoreKapil Porwal
Hook the newly created/exposed CnviWifiCore UPD up as a chip driver. Enable this option by default to maintain the existing behavior. BUG=b:270985197 TEST=Verified by enabling/disabling the UPD on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/74306 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13soc/intel/common: Update cpu_apic_info_type structSridhar Siricilla
The patch updates total cpu count variable and total P-core count in cpu_apic_info_type structure to `unsigned short int` to address more cores. TEST=Verify the build on Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I46239cc7ad9870e7134955af56b9f6625be2b002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-13soc/intel/xeon_sp: Fix very small total memory when CXL is enabledJohnny Lin
Processor attached memory should not use reserved_ram_from_to and treat the calculation of gi_mem_size size as 64MB. By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Before the fix running command 'free -g -h' under Linux shows the total memory is only 1.4Gi, after the fix it's showing the expected total memory size 15Gi. Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. On OCP Crater Lake with CXL memory attached, CXL memory can be recognized in NUMA node 1: numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 .. 59 node 0 size: 95854 MB node 0 free: 93860 MB node 1 cpus: node 1 size: 63488 MB node 1 free: 63488 MB node distances: node 0 1 0: 10 14 1: 14 10 Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-13soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tomFelix Held
Use the common acpi_fill_root_complex_tom function instead of the SoC- level northbridge_fill_ssdt_generator function that does basically the same. TEST=Resulting coreboot SSDT remains unchanged on Careena. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0f100e0766ce0f826daceba7dbec1fb88492938 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-12Revert "soc/intel/rtd3: Hook up supported states to Kconfig"Michael Niewöhner
This reverts commit dbb97c3243e55a0fd00e692d150c9d38d09b57af. Reason for revert: dependency for revert CB:73903 Change-Id: Ibc81483239a13f456d20631725641b7219af4ef8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"Michael Niewöhner
This reverts commit fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4. Reason for revert: dependency for revert CB:73903 Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPDPatrick Rudolph
The Kconfig is only used in common code to gather the build time maximum socket number FSP support. The same information is available in FSP header as MAX_SOCKET, thus use the FSP as truth of source. Currently MAX_SOCKET is 4. Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74339 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11ACPI: Add helper for MADT LAPICsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11ACPI: Add helper for MADT LAPIC NMIsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hiddenMichał Żygowski
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration space from coreboot on Alder Lake systems. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11soc/intel/alderlake: Hook up P2SB PCI opsMichał Żygowski
P2SB device is being hidden from coreboot by FSP-S. This breaks the resource allocator which does not report P2SB BAR via intel common block P2SB driver. Hook up the common block P2SB driver ops to soc_enable function so that the resources will be reported. The P2SB device must be set as hidden in the devicetree. This fixes the silent resource allocation conflicts on machines with devices having big BARs which accidentally overlapped P2SB BAR. TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big BARs and see resource conflicts no longer occur. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7c59441268676a8aab075abbc036e651b9426057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11soc/amd/mendocino: Lower log level for TDP value to DEBUGPaul Menzel
Printing the value of a variable is not informative for a normal user, so decrease the value from BIOS_INFO to BIOS_DEBUG. Fixes: b9caac74a320 ("soc/amd/mendocino: Reinterpret smu_power_and_thm_limit") Change-Id: I22f6293fd47633dfdbdae37b7257f47a5a4bb29c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-04-11soc/intel/xeon_sp/acpi: Fix _OSC methodPatrick Rudolph
Fix a couple of bugs in the _OSC method for handling "PCI Host Bridge Device" on Xeon-SP. - Drop the Sleep. The code doesn't write to hardware at all, so there's no need to sleep here. - Make sure that the number of DWORD passed in Arg2 is at least 3. The existing check was useless as it would not create the DWordField, but then use it anyways. - Add check for CXL 2 device method calls which provide a 5 DWORD long buffer to prevent buffer overflows when invoking the "PCI Host Bridge Device" method. Test: Boot on Archer City and confirm that no ACPI errors are reported for _OSC. Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-04-11soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-SMichał Żygowski
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11drivers/fsp2_0/mp_service_ppi: Use struct device to fill in bufferArthur Heymans
Now the CPU topology is filled in struct device during mp_init. Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11soc/intel/{adl, cmn}: Send CSE EOP Async CMD earlySubrata Banik
This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample whichcauses idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/marasov EVT sku to ChromeOS and observed ~30ms of boot time savings (across warm and cold reset scenarios). Without this patch: 963:returning from FspMultiPhaseSiInit 907,326 (97,293) ... ... 115:finished elog init 967,343 (2,581) 942:before sending EOP to ME              967,821 (478) …  16:finished LZMA decompress (ignore for x86)    1,017,937 (12,135) 943:after sending EOP to ME                     1,067,799 (49,861) … … 1101:jumping to kernel                          1,144,587 (13,734) Total Time: 1,144,549 With this patch: 963:returning from FspMultiPhaseSiInit 918,291 (97,320) 942:before sending EOP to ME                    918,522 (230)   ... ... 16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483)   943:after sending EOP to ME                     1,033,456 (3,980)   ... ...   1101:jumping to kernel                          1,111,410 (14,007) Total Time: 1,111,375 Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-10soc/amd/common/blk/pcie: Program LTR max latenciesMatt DeVillier
PCIe bridges need to provide the LTR (latency tolerance reporting) maximum snoop/non-snoop values so that they are inherited by downstream PCIe devices which support and enable LTR. Without this, downstream devices cannot have LTR enabled, which is a requirement for supporting PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior, including some devices refusing to enter L1 low power modes at all. Program the max snoop/non-snoop latency values for all PCIe bridges using the same value used by AGESA/FSP, 1.049ms. BUG=b:265890321 TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure LTR is enabled, latency values are correctly set, and that device power draw at idle is in the expected range (<25 mW). Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74288 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-10soc/mediatek/mt8188: Set pin drive strength to 8mA for NORJason Chen
Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.8 and 5.19 in MT8188 Functional Specification. BUG=b:270911452 TEST=boot with following logs [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74064 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Add GPIO driving functionsJason Chen
Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74063 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Move GPIO driving-related functions to commonJason Chen
Move GPIO driving-related functions to common for code reuse. BUG=b:270911452 TEST=build pass Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74068 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Reduce GPIO code size in bootblockJason Chen
Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downsized from 1480 bytes to 24 bytes. BUG=b:270911452 TEST=build pass Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74062 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytesYidi Lin
Original lastbus configuration consumes constant memory size by allocating 16 and 8 members arrays and the utilization is bad. Refactor the lastbus structs to save memory usage. BRANCH=none BUG=none TEST=bootblock.raw.bin size is reduced from 60328 bytes to 59048 bytes. Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74061 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-07soc/intel/common: Order the different types of cores based on APIC IDsSridhar Siricilla
Currently coreboot presents the BSP core first, then efficient cores and Performance cores as indicated below: ``` /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4 /sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5 /sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6 /sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7 /sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3 ``` Existing code presents mix of different cores to OS and causes CPU load balancing and power/performance impact. So, the patch fixes this disorder by ordering the Performance cores first, compute die efficient cores next, and finally SOC efficient cores if they are present. This is done to run the media applications in a power efficient manner, please refer the ChromeOS patches for details: https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893 BUG=b:262886449 TEST=Verified the code on Rex system After the fix: ``` /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4 /sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5 /sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6 /sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7 ``` Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-04-07mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-07soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella
coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. This patch also introduces a new code logic to detect if CSE is in the right state to handle the EOP command. Otherwise, it uses the prescribed method to make the CSE function disable. The typical scenario is the ChromeOS recovery boot where CSE stays in RO partition and therefore EOP command should be avoided. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [INFO ] HECI: coreboot in recovery mode; found CSE in expected SOFT TEMP DISABLE state, skipping EOP [INFO ] Disabling Heci using PMC IPC [WARN ] HECI: CSE device 16.0 is hidden [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/meteorlake: Perform feature control lockSubrata Banik
This function calls into `set_feature_ctrl_lock()` to lock IA32_FEATURE_CONTROL MSRfeature control. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Enable VMX using coreboot CPU feature programSubrata Banik
This function calls into `set_feature_ctrl_vmx_arg()` to enable VMX for virtualization if not done by FSP (based on DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake SoC based platform. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Set AES-NI LockSubrata Banik
This function performs locking of the AES-NI enablement state. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Disable 3-strike errorSubrata Banik
This patch calls into API to disable 3-strike error on Meteor Lake SoC based platform. TEST=Able to build and boot google/rex to ChromeOS. Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled ``` localhost ~ # iotools rdmsr 0 0x1a4 0x0000000000000900 ``` Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/meteorlake: Allow to drop redundant CPU feature programmingSubrata Banik
This patch introduces a new config named `DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU feature programming on BSP and on APs using the "CpuFeaturesPei.efi" module. Most of this feature programming is getting performed today in scope of coreboot doing MP Init. Running this redundant programming in scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) results in CPU exception (for example: attempting to reprogram CPU feature lock MSR is causing CPU exception). SoC users should select this config after dropping "CpuFeaturesPei.ffs" module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional feature programming on BSP and APs. This feature is by default enabled, in case of "coreboot running MP init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected. At present, this option does not do anything unless any platform eventually decides to drop FSP feature programming module and choose coreboot CPU feature programming over it. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/cmn/cpu: Add function to disable 3-strike CATERRSubrata Banik
In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a 3-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. This patch prevents the Three Strike Counter from incrementing (as per Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-06amd/mendocino/root_complex: Restrict DPTC to 15W boardsTim Van Patten
Restrict DPTC to 15W boards, since we only have 15W values defined in the devicetree. This will revert the 6W boards back to their default values, rather than (incorrectly) configuring them with 15W values. BUG=b:253301653 TEST=Verify DPTC values are set for 15W boards TEST=Verify DPTC values are set not set for 6W boards Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74127 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06soc/amd/mendocino: Reinterpret smu_power_and_thm_limitTim Van Patten
The FSP will return the TDP in the format 0xX0000, where 'X' is the value we're interested in. For example: 0xF0000 (15W), 0x60000 (6W). Re-interpret the value so the caller just sees the TDP directly, without needing to re-interpret things themselves. BUG=b:253301653 TEST=Manually verify value is correct Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74126 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06soc/intel/xeon_sp/spr: Drop devicetree setting X2apicPatrick Rudolph
Drop devicetree setting X2apic as the same functionality is already exposed in Kconfig. To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in the "APIC operation mode". Note: Your OS must have support for X2APIC. If you are using less than 256 CPU cores select XAPIC_ONLY here. Test: - Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME was selected. - Booted to OS in XAPIC mode when XAPIC_ONLY was selected. Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-06soc/intel/xeon_sp/spr: Default to X2APIC supportPatrick Rudolph
When more than 255 CPU cores are present on a board the X2APIC must be used. Select DEFAULT_X2APIC_RUNTIME to support X2APIC by default when a mainboard enables it in the devicetree. Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-05soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systemsPatrick Rudolph
Inject ACPI code for all generated ASL templates. This fixes ACPI errors shown in linux when not all sockets are currently plugged in or some have been disabled. Test: Boot Archer City with CONFIG_MAX_SOCKET=4 Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
2023-04-05soc/intel/common/block/pcie/rtd3: Add root port mutex supportCliff Huang
When 'use_rp_mutex' (default = 0) is set in the device tree, a root port mutex will be added. This mutex is used in _ON and _OFF method, where the GPIO reset and/or enable GPIO value is changed. The companion driver, such as WWAN driver, needs to acquire this root port mutex when accessing the same GPIO pins. Using this common mutex prevents those invoked methods from being called from different thread while one is not completed. An example is that WWAN driver calling _RST method to reset the device and does remove/rescan for the device while the pm runtime work might call RTD3 _OFF. For those root port without additional driver, this mutex is not needed. BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated and _ON and _OFF should use this mutex. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ibc077528692b2d7076132384fb7bd441be502511 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-05Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"Nick Vaccaro
This reverts commit e7a1204f26fe3628de99b4ab4e3f32916565b95c. This initial change was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74207 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-05Revert "mb/google/brya: Enable asynchronous End-Of-Post"Nick Vaccaro
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32. Revert initial change as it was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04soc/amd/*/Makefile: use all_x86 targetFelix Held
Use the newly introduced 'all_x86' make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless builds for Mandolin without verstage on PSP and Guybrush with verstage on PSP result in identical images with and without this patch applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74151 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-04soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Able to see TS elapse prior to IA reset on Rex Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-03soc/amd/cezanne,glinda,mendocino,phoenix,picasso/Kconfig: use all targetFelix Held
The i2c.c compilation unit is added to all stages in all cases, so use the all target instead of adding it to all stages separately. Also order the all targets alphabetically. TEST=Timeless build on Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie90380075a3c87d226cdcb0f41f7e94275eaaa42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-03soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current valuesJeremy Compostella
The Intel Power and Performance (PnP) team requested to update the following: - TDC settings for RPL-U 15W variant should be 22A. - TDC settings for RPL-P 28W variant should be 33A. BUG=b:275694022 BRANCH=firmware-brya-14505.B TEST=PnP validated performance impact with these settings on both RPL-U 15W and RPL-P 28W Change-Id: I1141414785a990b975e32ebc03e490b83082aab7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/common: Order the CPUs based on their APIC IDsSridhar Siricilla
The patch defines acpi_set_cpu_apicid_order() which orders the APIC IDs based on APIC IDs of Performance cores and Efficient cores, calculates the total core count and total Performance cores count, populates the information in the cpu_apicid_order_info struct. The helper function useful to present the Performance and Efficient cores in order to OS through MADT table and _CPC object. TEST=Verify the build for Gimble (Alder Lake board) Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/meteorlake: Set Power Performance Platform OverrideSubrata Banik
According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set. This patch is backported from `commit 117770d32468e63df ("soc/intel/ alderlake: Enable Energy/Performance Bias control")`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/meteorlake: Add EPP override supportSubrata Banik
This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. This patch is backported from `commit 0bb2225718ef898c ("soc/intel/alderlake: Add EPP override support")`. BUG=b:266522659 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-01soc/amd/stoneyridge: factor out P-state utils to link in all stagesFelix Held
tsc_freq.c gets built into all stages, but the tsc_freq_mhz function it implements calls the get_pstate_0_reg function which was only built into ramstage. Since tsc_freq_mhz was only called in ramstage, commit 2323acab6a7a ("soc/amd/stoneyridge: implement and use get_pstate_0_reg") didn't cause the build to fail, but better factor out the P-state- related utility functions into a separate compilation unit and include it in all stages that also include tsc_freq.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3a3ee218f495be5e60a888944487704e7e8a1a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-01soc/amd/stoneyridge/Makefile: use all target for more compilation unitsFelix Held
monotonic_timer.c, tsc_freq.c and uart.c get added to all stage targets, so just add those to the all stage targets. They still need to be added to the smm stage target, since the all target doesn't add things to the smm stage. TEST=Timeless build results in identical image for Gardenia. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I16c02bc0ff54553f212b94d110abef6a7bdedbb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74144 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-01soc/intel/xeon_sp/spr: Add ACPI support for Sapphire RapidsJonathan Zhang
Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests. The code was written from scratch because there are Xeon-SP specific implementation especially Integrated Input/Output (IIO). Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967 Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-01soc/intel/meteorlake: Add BUILDING_WITH_DEBUG_FSPSubrata Banik
Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. BUG=b:262868089 TEST=Able to build and boot google/rex. Change-Id: I5555a2ab4182ad0036c42be6fea3d934ffd0db8c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 22:59:19 +0000