Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"

This reverts commit fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4.

Reason for revert: dependency for revert CB:73903

Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>

10 files changed, 47 insertions, 35 deletions

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 2887439d20..480ee0b8c4 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -331,6 +331,12 @@ config SOC_INTEL_I2C_DEV_MAX
 	int
 	default 8
 
+config SOC_INTEL_ALDERLAKE_S3
+	bool
+	default n
+	help
+	  Select if using S3 instead of S0ix to disable D3Cold.
+
 config ENABLE_SATA_TEST_MODE
 	bool "Enable test mode for SATA margining"
 	default n
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 5c95997f57..1f626fc7d3 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -583,7 +583,7 @@ Scope (\_SB.PCI0)
 		}
 	}
 
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	Method (TCON, 0)
 	{
 		/* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
 			STAT = 0
 		}
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 
 	/*
 	 * TCSS xHCI device
diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl
index ca47bd0ec9..1483c0b5ac 100644
--- a/src/soc/intel/alderlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl
@@ -28,16 +28,16 @@ Name (STAT, 0x1)  /* Variable to save power state 1 - D0, 0 - D3C */
 
 Method (_S0W, 0x0)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	Return (0x04)
 #else
 	Return (0x03)
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 }
 
 Method (_PR0)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	If (DUID == 0) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -49,12 +49,12 @@ Method (_PR0)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif // D3COLD_SUPPORT
+#endif // SOC_INTEL_ALDERLAKE_S3
 }
 
 Method (_PR3)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	If (DUID == 0) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -66,7 +66,7 @@ Method (_PR3)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 }
 
 /*
diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index 6dbde46f49..4f1eec5d2c 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
 
 Method (_S0W, 0x0, NotSerialized)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	Return (0x4)
 #else
 	Return (0x3)
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 }
 
 Method (_PR0)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	If ((TUID == 0) || (TUID == 1)) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -268,12 +268,12 @@ Method (_PR0)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 }
 
 Method (_PR3)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	If ((TUID == 0) || (TUID == 1)) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -285,7 +285,7 @@ Method (_PR3)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 }
 
 /*
diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
index ddc5a6665d..c0dc141530 100644
--- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
 
 Method (_S0W, 0x0, NotSerialized)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 	Return (0x4)
 #else
 	Return (0x3)
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 }
 
 /*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
  */
 Name (SD3C, 0)
 
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
 Method (_PR0)
 {
 	Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ Method (_PR3)
 {
 	Return (Package () { \_SB.PCI0.D3C })
 }
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_ALDERLAKE_S3
 
 /*
  * XHCI controller _DSM method
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 84425cc6e3..fca4f794f6 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -207,6 +207,12 @@ config SOC_INTEL_I2C_DEV_MAX
 	int
 	default 6
 
+config SOC_INTEL_TIGERLAKE_S3
+	bool
+	default n
+	help
+	  Select if using S3 instead of S0ix to disable D3Cold
+
 config SOC_INTEL_UART_DEV_MAX
 	int
 	default 3
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 98337a3e5e..be9d306f6e 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -676,7 +676,7 @@ Scope (\_SB.PCI0)
 		}
 	}
 
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	Method (TCON, 0)
 	{
 		/* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -787,7 +787,7 @@ Scope (\_SB.PCI0)
 			STAT = 0
 		}
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 
 	/*
 	 * TCSS xHCI device
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index bbb0b6a1ad..3c19ef621e 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -27,11 +27,11 @@ Name (STAT, 0x1)  /* Variable to save power state 1 - D0, 0 - D3C */
 
 Method (_S0W, 0x0)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	Return (0x04)
 #else
 	Return (0x03)
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 }
 
 /*
@@ -40,7 +40,7 @@ Method (_S0W, 0x0)
  */
 Method (_PR0)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	If (DUID == 0) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -52,12 +52,12 @@ Method (_PR0)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 }
 
 Method (_PR3)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	If (DUID == 0) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -69,7 +69,7 @@ Method (_PR3)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 }
 
 /*
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index a8e19edcce..fda58e70cf 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -247,7 +247,7 @@ Method (_PS3, 0, Serialized)
 
 Method (_S0W, 0x0, NotSerialized)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	Return (0x4)
 #else
 	Return (0x3)
@@ -256,7 +256,7 @@ Method (_S0W, 0x0, NotSerialized)
 
 Method (_PR0)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	If ((TUID == 0) || (TUID == 1)) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -268,12 +268,12 @@ Method (_PR0)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 }
 
 Method (_PR3)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	If ((TUID == 0) || (TUID == 1)) {
 		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 	} Else {
@@ -285,7 +285,7 @@ Method (_PR3)
 	} Else {
 		Return (Package() { \_SB.PCI0.TBT1 })
 	}
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 }
 
 /*
diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
index ddc5a6665d..a3b8c8faf7 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
 
 Method (_S0W, 0x0, NotSerialized)
 {
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 	Return (0x4)
 #else
 	Return (0x3)
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 }
 
 /*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
  */
 Name (SD3C, 0)
 
-#if CONFIG(D3COLD_SUPPORT)
+#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
 Method (_PR0)
 {
 	Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ Method (_PR3)
 {
 	Return (Package () { \_SB.PCI0.D3C })
 }
-#endif	// D3COLD_SUPPORT
+#endif	// SOC_INTEL_TIGERLAKE_S3
 
 /*
  * XHCI controller _DSM method