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2022-01-27soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util codeFelix Held
The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface any more, so there are no LPC pins that can be reconfigured as eSPI interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I02bc8d007901c71942475fe707637c5da7227230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: drop CPPC codeFelix Held
The CPPC feature isn't available on the Sabrina SoC, so drop the corresponding code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update PCI devices in devicetree.cbFelix Held
Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update pci_devs.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic0226afd9e7fffd6bf196f06ee6c34b6b9c92f30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/fsp_m_params: drop sata_enable UPD writeFelix Held
There are no SATA controllers on the Sabrina SoC. The UPD field will be removed later as a part of the initial UPD header update. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedefd9f150e5bcb78173288e5fc9f1bbd6b498cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-01-27soc/amd/sabrina/include: update smi.hFelix Held
Some of the names have slightly changed in the PPR, but I kept the current names for consistency across all AMD SoCs in coreboot. Revision 1.50 of the PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bda656015858a57e221b8d7819f944c21564a39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/include/data_fabric: update IOMS0_FABRIC_IDFelix Held
The data fabric ID table in PPR #57243 Rev 1.50 has a different IOMS0 fabric ID than Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32890b5c03219f6ebf8180929d71ef726d382483 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-01-27soc/amd/sabrina: drop graphics.cFelix Held
Since we don't need to support PCI ID remapping for finding the correct VBIOS binary for the integrated GPU, graphics.c can be dropped for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd5b678f472b3b5888353efd057203eb641be874 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/cpu: update CPUIDFelix Held
Sabrina is family 17h model A0h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01e02e3491fb90941c767058986da876bdf7ca1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: add additional UART controllersFelix Held
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of the PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-27soc/amd/sabrina/gpio: update GPIO definitions and gpio_event_tableFelix Held
The GPIO and GPIO MUX mapping as well as some GPIO to GEVENT mappings have changed compared to Cezanne. Sabrina also doesn't have a remote GPIO bank. Revision 1.50 of PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabb85a3d24c881055e94400d08d01505df44a07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-01-27soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTsFelix Held
Compared to Cezanne there are 3 more UARTs controllers. The PCI interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't contain a PIRQ mapping for UART4. The reference code has a mapping for this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5. Since the I2C5 controller isn't owned by the x86 side and I didn't see any mapping of the I2C5 controller into the x86 MMIO space, this seems very plausible. Also add the corresponding fields to the ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/intel/common/cse: Drop CSE library usage in bootblockSubrata Banik
This patch drops the CSE common code block from getting compiled in bootblock without any SoC code using heci communication so early in the boot flow. BUG=none TEST=Able to build brya, purism/librem_skl without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib4d221c6f19b60aeaf64696e64d0c4209dbf14e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-01-27soc/intel/skylake: move heci_init() from bootblock to romstageMatt DeVillier
Aligns with all other soc/intel/common platforms calling heci_init(). Test: build/boot Purism Librem 13v2 Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26src: Add missing 'void' in function definitionElyes HAOUAS
Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-26soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-MMatt DeVillier
Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master] updated the FSP binaries/headers for Comet Lake, which included a change moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing UDP in FSP-S was left in and deprecated, which allowed the change to go unnoticed until it was discovered that hotplug wasn't working. Since other related platforms (WHL, CFL) share the SoC code but use different FSP packages, add the setting of the PcieRpHotPlug UPD to romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'. Test: build/boot Purism Librem 14, verify WiFi killswitch operates as expected / WiFi is re-enabled when turning switch to on position. Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-26soc/intel/denverton_ns: Fix logging levelKyösti Mälkki
Level should match that used in print_num_status_bits(). Change-Id: I1beb65e4c141e195dd59eaa2bf55fff6e7dc910d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-26soc/intel/alderlake: Add GPIO Controller device ID for ADL-NUsha P
Add PCH ACPI Device ID for Alder Lake N SOC GPIO Controller. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6eb15751dd303b4b445cb64f25a040302e50c09d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-01-26soc/mediatek/mt8186: Use BIT() macro for arbiter enable bitRex-BC Chen
Replace (1 << x) with BIT(x) in pmic_wrap.h. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61351 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26soc/intel/alderlake: Choose non-posted write to lock GPIO PADSubrata Banik
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI config on Alder Lake to instruct Pad Configuration Lock to use non-posted sideband writes as posted write is not supported on Alder Lake while locking GPIO pads. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id8d394b97de9c328b3f75df3649d7efc782f006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-26soc/intel/alderlake: Skip FSP to unlock GPIO PadsSubrata Banik
This patch makes FSP-S skip unlocking the GPIO Pads. BUG=b:211573253, b:211950520 TEST=FSP-S debug log below: Without this change: UnlockGpioPads= 1 With this changes UnlockGpioPads= 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I236a19a67372e9668e304d0054d477daff6a0266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-26soc/intel/common/gpio: Rework PAD config macro to add lock supportSubrata Banik
This patch extends `struct pad_config` to add new variable for gpio lock action. Additionally, it creates new GPIO PAD configuration macros that perform GPIO pad configuration and pad lock configuration as well. List of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK Mainboard users can use the above macros to lock the PAD after configuration. So far on IA chipset, the default GPIO pad lock configuration reset type is POWERGOOD hence, it's recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type the same as lock configuration reset type to avoid GPP reset value misconfiguration issue. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-26soc/intel/common/gpio: Perform GPIO PAD lock outside SMMSubrata Banik
This patch performs GPIO PAD lock configuration in non-smm mode. Typically, coreboot enables SMI at latest boot phase post FSP-S, hence, FSP-S might get chance to perform GPP lock configuration. With this code changes, coreboot is able to perform GPIO PAD lock configuration early in the boot flow, prior to calling FSP-S. Also, this patch ensures to have two possible options as per GPIO BWG to lock the GPIO PAD configuration. 1. Using SBI message with opcode 0x13 2. Using Private Configuration Register (PCR) BUG=b:211573253, b:211950520 TEST=Able to build and boot brya variant with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60801 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_coreFelix Held
This code is common to at least all Zen-based APUs (Picasso, Cezanne, Sabrina) and is also useful outside of the SoC-specific dynamic ACPI table generation code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: Eric Peers <epeers@google.com>
2022-01-26soc/mediatek/mt8186: Update PWRAP arbiter enable bitRex-BC Chen
There is no wakeup source when we test function of suspend and resume. The root cause is that the monitor enable bit of PWRAP is not configured correctly. BUG=b:213255218, b:214978483 TEST=receive wakeup source from MT6366 successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I324d18fa5d3cd745c35fcf0f207e1b444b5e898b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61330 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26soc/amd/common: Don't reserve VERSTAGE region when using PSP verstageRaul E Rangel
The VERSTAGE region is only needed when running verstage in the x86. This change reduces the early ram size by 512 KiB when using PSP verstage. BUG=none TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I45ce421397807dbb1eb48aedd05209b91e89aa4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-25soc/amd/cezanne: FSP: Add UPD entry for eDP tuningZheng Bao
The FSP gets these values from the UPD and sets the internal values. The document about eDP tuning is attached in issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Cq-Depend: chrome-internal:4303901 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-25soc/intel/ehl: Add Kconfig option to disable reset on TCO expirationWerner Zeh
The TCO timer is the default watchdog of an x86 host and can reset the system once it has expired for the second time. There are applications where this reset is not acceptable while the TCO is used. In these applications the TCO expire event generates an interrupt and software takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to prevent this reset on expiration (called NO_REBOOT, see doc #636722 ). This bit can either be strapped on hardware or set in this register to avoid the reset on expiration. While the hardware strap cannot be overridden in software, the pure software solution is more flexible. Unfortunately, the location for this bit differs among the different platforms. This is why it has to be handled on soc level rather than on TCO common code level. This commit adds a Kconfig option where NO_REBOOT can be enabled. This makes it easy to reach this feature over to the mainboard where it can be selected if needed. Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25soc/intel/common: Include Alder Lake-N device IDsUsha P
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-25soc/intel/elkhartlake: Add PSE TSN supportLean Sheng Tan
Enable PSE GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Add PSE GBE ACPI devices 3. Refactor PCH GBE FSP-S code and merge it together with PSE GBE code Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-25soc/intel/elkhartlake: Introduce Intel PSELean Sheng Tan
The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-25soc/mediatek: Save dramc_param header to mrc_cacheXi Chen
Fast-k flow may need to re-init header because mrc_cache doesn't store header. Storing header together with dparam data is better for data consistancy. TEST=fast calibration pass on Corsola BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I22982923dce06c9e770aa4f20f3dcd2f33685d84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-25soc/amd/sabrina/include/aoac_defs: add additional UARTsFelix Held
Compared to Cezanne there are 3 more UARTs controllers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id98767197a21cb1a61f54fc9b256b10a9506c791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/sabrina/include/iomap: update MMIO device mappingsFelix Held
Compared to Cezanne there are 3 more UARTs with DMA controllers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a3d255bb4976a55623f3a161e791e80f1d01c69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/cezanne: Increase PRERAM_CBMEM_CONSOLE_SIZE to 0x2000Raul E Rangel
Let's increase this to avoid losing any logs. BUG=b:213828947 TEST=Boot guybrush and no longer see *** Pre-CBMEM romstage console overflowed, log truncated! Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3258145e352af3a75893c7cc96f36eb238c99abb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-25soc/amd/sabrina: use correct PCI IDsFelix Held
Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added in commit 27b02c2eee68f4b6c8520c4737224aaaf81f137d (include/device/ pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/common/block/include/psp_efs: update defines for sabrinaFelix Held
Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for The AMD Sabrina SoC which is family 17h models A0h-AFh. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/sabrina: add new SoC as copy of soc/amd/cezanneFelix Held
The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-24soc/intel/common/block/pcie/rtd3: Fix PMC IPC method for CPU PCIe RPTim Wawrzynczak
When calling get_pcie_rp_pmc_idx(), the following code checked the return value to see if it was negative or `> CONFIG_MAX_ROOT_PORTS`. However, the expected return value for CPU PCIe RPs is above MAX_ROOT_PORTS. Since the static, local function is intended to return -1 or a valid value, drop the check for `> CONFIG_MAX_ROOT_PORTS`. Change-Id: I2039273ad246884cd8736a7f0355e621a706a526 Fixes: b6a15a7 ("soc/intel/common/block/pcie/rtd3: Update ACPI Update ACPI methods for CPU PCIe RPs") Tested-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-01-24soc/amd/common: Make the function in cpu.c available in romstageZheng Bao
Change-Id: I909f74853a37a783582471e05071bc3d07e3dcf8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-24soc/mediatek: Extract dramc_param_header to a common headerXi Chen
To be shared with different SOCs, move the dramc_param_header struct as well DRAMC_PARAM_FLAG and DRAMC_PARAM_CONFIG enums to a common header file dramc_param_common.h. TEST=fast calibration pass BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I087971799803e47e34c30063b2b0bd0cfc5795ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61132 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-23soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZERaul E Rangel
This change splits the size of the console transfer region and size of the bootblock/romstage Pre-RAM console region. This allows having a larger Pre-RAM console while not impacting the size of the PSP verstage console. Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in `setup_cbmem_console`, I chose to use the offsets provided in the transfer buffer. It would be nice to eventually do this for all the fields in the transfer buffer. BUG=b:213828947 TEST=Boot guybrush and verify verstage logs are no longer truncated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-22soc/intel/alderlake: Implement get_soc_cpu_type helper functionSridhar Siricilla
The patch implements get_soc_cpu_type() helper function which determines whether the executing CPU is a small or a big core. This is the SoC-specific callback that must be implemented for SoCs that select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID. It will be called from set_cpu_type(). TEST=verified on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Icd0d7e8a42c4b20d3e1d34998bca6321509df2d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21soc/intel/common/cse: Add support to get CSME timestampsBora Guvendik
This command retrieves a set of boot performance timestamps CSME collected during the platform's last boot flow. BUG=b:182575295 TEST=Verify CSME timestamps after S3 and boot. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21soc/intel/common/gpio: Add PCH `Pad Configuration Lock` optionsSubrata Banik
This patch provides the possible options for PCH to allow `Pad Configuration Lock`. `SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake Point (TGP) and Alder Lake Point (ADP) PCH. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-21soc/intel/common/gpio: Use const variable to get gpio bitmaskSubrata Banik
This patch introduces a `const bit_mask` variable to hold the gpio PAD mask value prior to sending the lock configuration command using the sideband interface. Additionally, this patch fixes the PAD lock overridden issue as below: Without this code change every consecutive PAD lock operation resets other bits in that register as below: After Locking pad 2 , pcr_read=0x4 After Locking pad 3 , pcr_read=0x8 After Locking pad 4 , pcr_read=0x10 After Locking pad 5 , pcr_read=0x20 After Locking pad 6 , pcr_read=0x40 After Locking pad 7 , pcr_read=0x80 After Locking pad 8 , pcr_read=0x100 With this code change all previous lock bits are getting preserved as below: After Locking pad 2 , pcr_read=0x4 After Locking pad 3 , pcr_read=0xc After Locking pad 4 , pcr_read=0x1c After Locking pad 5 , pcr_read=0x3c After Locking pad 6 , pcr_read=0x7c After Locking pad 7 , pcr_read=0xfc After Locking pad 8 , pcr_read=0x1fc BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I342a666aa2d34bcc8ba33460396d1248f0c0f89f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60999 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-21soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR configCurtis Chen
ADL-P 2+8+2 (28W) would have a match PD to ADL-P 4+8+2 (28W). Group them into the same group core "ADL_P_282_482_28W_CORE". BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I3f92c0f5d717dd33ac478fbaa883f3e972e7a7de Reviewed-on: https://review.coreboot.org/c/coreboot/+/61196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
The only option to make HECI1 function disable on Elkhart Lake SoC platform is using SBI under SMM mode. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-21soc/intel/icl: Rework on HECI1 disable configsSubrata Banik
The only option to make HECI1 function disable on Ice Lake SoC platform is using SBI under SMM mode. Hence, this patch makes DISABLE_HECI1_AT_PRE_BOOT=y default and selects `HECI_DISABLE_USING_SMM` config for Ice Lake. Also, drop `HeciEnabled` from chip configuration and guard heci_disable() using DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-20soc/amd/picasso/bootblock: drop unused includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I837e1f8727adefb9227ac7df2ff715245957be2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-20soc/amd/cezanne,picasso: factor out common early non-car cache setupFelix Held
This implementation is the same for all SoC that select SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR CPU support code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-20soc/amd/cezanne/include/espi.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I393feab8550a7124ab2982ff3d256e3491d27b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-20soc/amd/common/vboot: Verify the size of the transfer bufferRaul E Rangel
This will verify that signed verstage binaries and the bootblock code executing agree on the transfer buffer struct size. BUG=b:213828947 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I597e38fe0a37416ffd3bc01fd974fa8f6610a88c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-19soc/intel/alderlake: Add method to determine the cpu typeSridahr Siricilla
set_cpu_type(): It determines the CPU type (big or small) that is executing the function, and marks the global_cpu_type's array slot which is corresponds to the executing CPU's index if the CPU type is big core. get_cpu_index(): It determines the index from LAPIC Ids. This is required to expose CPPC3 package in ascending order of CPUs' LAPIC ids. So, the function returns CPU's position from the ascending order list of LAPIC ids. TEST=Tested CPU index calculation, core type determination on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-19soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik
This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-19soc/intel/alderlake: Rework the GPIO PAD Pin numbersSubrata Banik
This patch creates a `relative increment by 1` macro to let SoC gpio pad configuration to be more flexible while adding support for newer PCH SoC. With this changes adding GPIO controller support for PCH-N would become really simple without too much of code duplication. For example: ADL-N has added `GPP_I` pins into community 1 hence, the additional code for `PCH-N` whould appear incremetal to ADL-P. > #define GPP_B 0x0 > #define GPP_T INC(GPP_B) > #define GPP_A INC(GPP_T) > #define GPP_R INC(GPP_A) > #define GPD INC(GPP_R) > #define GPP_S INC(GPD) > if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) > #define GPP_I INC(GPP_S) > #define GPP_H INC(GPP_I) > #else > #define GPP_H INC(GPP_S) > #endif > #define GPP_D INC(GPP_H) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18soc/amd/{picasso,cezanne}: Enable CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel
This will help debugging verstage failures. BUG=b:213828947 TEST=Boot guybrush and verify verstage logs are printed before bootblock messages. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia60991b3e81c19c24ceb69193840dde873ef3346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-18soc/intel/alderlake: Add eMMC device into chipset.cbKrishna Prasad Bhat
Add eMMC device into chipset.cb and keep it `off` by default. eMMC device is applicable only for Alder Lake N SOC. Change-Id: I2bc38ee5814688409feb7e4531c1daa5b54953c0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18soc/intel/common: Add Alder Lake N eMMC device IDKrishna Prasad Bhat
Add eMMC device ID for Alder Lake N SOC. Reference: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Change-Id: Id35ec2d508bec8ff7d6f1c5fbfaf209d42b25c72 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18soc/intel/{adl,common}: Support alderlake host device id 0x4619Kane Chen
Host device id 0x4619 is missed in few coreboot tables so that coreboot can't recognize and config it properly. Document Number: 690222 BUG:b:214665785, b:214680767 Change-Id: I95908bdc0a736bafedb328dda2a00b5473de3d88 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-17pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly
Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-17soc/intel/cnl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake and ensures disable_heci1() is guarded against this config. Also, makes dt CSE PCI device `on` by default. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-17src: Remove unused <cbfs.h>Elyes HAOUAS
Found using: diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<" Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-16soc/intel/common/cse: Add helper API for CSE SPI Protection ModeSubrata Banik
This patch checks if CSE's spi protection mode is protected or unprotected. Returns true if CSE's spi protection mode is protected, otherwise false. BUG=b:211954778 TEST=Able to build and boot brya with this change. Calling `cse_is_hfs1_spi_protected()` in coreboot is able to provide the SPI protection status. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca Reviewed-on: https://review.coreboot.org/c/coreboot/+/60403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-16soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-16soc/intel/common: Abstract the sideband accessJohn Zhao
The existing Sideband access is with the PCH P2SB. There will be future platforms which access the TCSS registers through SBI other than the PCH P2SB. This change abstracts the SBI with common API. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-16soc/intel/denverton_ns: Add the Primary to Sideband Bridge definitionJohn Zhao
This change adds the Primary to Sideband Bridge(B0, D31, F1) definition for the platform in order to maintain the common block API build. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-14soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner
Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner
Add TGL-H support for the recently introduced code for differentiating CPU and PCH root ports by adding the missing TGL-H port map. Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-13soc/amd/*/chip.h: add missing gpio.h includeFelix Held
Since we need the GPIO defines in the devicetree settings, include gpio.h in each SoC's chip.h file which will indirectly include the soc-specific soc/gpio.h header instead of having it indirectly included via soc/i2c.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro
The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-13soc/mediatek: Fix include guard naming for emi.hYu-Ping Wu
Fix the name of the include guard for soc/mediatek/common/include/soc/emi.h. BUG=none TEST=emerge-corsola coreboot BRANCH=none Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-01-12soc/intel/common/gpio: Fix cosmetic issue with `gpio_lock_pads`Subrata Banik
This patch replaces hardcoded `4` (next offset Tx state) with `sizeof(uint32_t)` for calculating 'Tx state offset'. Also, add checks to detect the specific GPIO lock action between `LOCK_CONFIG` or 'LOCK_TX'. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iff712b16808e0bc99c575bb2426a4f84b89fdb73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-12sc7180: Update video mode active horizontal/vertical/total calculationsVinod Polimera
Remove vbp & hbp as the names are misleading and use edid variables to simplify the video mode active and total calculations. Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12soc/intel/tigerlake: Implement function to map physical port to EC portjzhao80
Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. This change clones the implementation on Alder Lake which converts the phyiscal port mapping to EC's abstract port mapping. BUG=b:207057940 BRANCH=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12soc/intel/tgl/pcie_rp: correct root port mapMichael Niewöhner
TGL-LP only has 12 root ports, not 20. Correct the port map. Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-12soc/amd/common/block: add new PCI IDs to common codeFelix Held
The existing common AMD SoC code supports some of AMD Family 17h Model A0h SoC's PCI devices that however have different PCI IDs. Add the new PCI ID defines to the PCI ID lists of the common PCI drivers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50960e502c63a2ffcfed35178c5e7c9729ef061e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-11soc/amd/cezanne/include/i2c: add missing types.h includeFelix Held
uintptr_t is defined in stdint.h which gets included by types.h. I use types.h instead of stdint.h, since that's also what the Picasso code does. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3d0811d831b5acc9343398f4d28c73467c0a429 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-11soc/amd/cezanne/include/i2c: move include inside header guardFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a8c21c462258c8a419ccc3f2db50f74a154e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-11soc/intel/apl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake and ensures disable_heci1() is guarded against this config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-11soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons
Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-11soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik
This patch migrates common code API into SoC specific implementation to drop CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151. Also, include `soc/msr.h` in cpu.h to fix the compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-10src/soc/qualcomm: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Id1e0f4cb9f6181dc2fc45e7b6cb149646111bb3e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/soc: Remove unused <stdlib.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: I08e1a680de9bfcc7d74e88a15abe9eef327b4961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-10src/soc/qualcomm: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I9097972080499bd61981fe738be93f7b193f5813 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/soc/intel: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I2ca3a7487cbe75f9bec458f4166378a07b833bb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10src/soc/amd: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Iff7fdd679ac31a121d56746ed8efa1b3da932638 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/soc/amd: Remove unused <timer.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <timer.h>' -- src/) <(git grep -l 'NSECS_PER_SEC\|USECS_PER_SEC\|MSECS_PER_SEC\|USECS_PER_MSEC\|mono_time\|microseconds\|timeout_callback\|expiration\|timer_monotonic_get\|timers_run\|timer_sched_callback\|mono_time_set_usecs\|mono_time_set_msecs\|mono_time_add_usecs\|mono_time_add_msecs\|mono_time_cmp\|mono_time_after\|mono_time_before\|mono_time_diff_microseconds\|stopwatch\|stopwatch_init\|stopwatch_init_usecs_expire\|stopwatch_init_msecs_expire\|stopwatch_tick\|stopwatch_expired\|stopwatch_wait_until_expired\|stopwatch_duration_usecs\|stopwatch_duration_msecs\|wait_us\|wait_ms' -- src/) Change-Id: I581f446330c4e99c587938d4eab387a51e3961e0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/soc/mediatek: Remove unused <timer.h>Elyes HAOUAS
Change-Id: Ic87e41a9b317cc7d0b36ece5ffd1d32068e6a33a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-10soc/intel/common/cse: Add config to disable HECI1 at pre-bootSubrata Banik
This patch adds a config to let mainboard users choose the correct state of HECI1(CSE) device prior to handing off to payload. `DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable at pre-boot. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10src/soc/amd: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: I810f6c78a070da554a65914e94b13e354f97f995 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10soc/amd/common/pi/agesawrapper.c: Include <string.h>Elyes HAOUAS
"memcpy" needs <string.h> Change-Id: I5b7b3a94acbb7e4f9614fcf3f06d68e6ac72f4f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10soc/intel/common: Add missing space before }Paul Menzel
Fixes: 5b94cd9e9d ("soc/intel/common: Include Alder Lake-N device IDs") Change-Id: I24c2bdb9e4a9eb873b52668a41f4c0e944ed7818 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-10soc/intel/alderlake: Update the ADL-P SKU parameters for VR domainsCurtis Chen
We support all the ADL-P 15W/28W/45W SKU's and map them with the latest VR configurations. These config values are generated by iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools * Intel(R) Platform Design Studio Installer: 610905 * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345 * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261 BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-09soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entriesMichael Niewöhner
Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 04:16:37 +0000