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2020-10-12soc/intel/common/block/smm: Fix compilation without intel uart codePatrick Rudolph
Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART. Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-10-12soc/intel/common/block/i2c: Scan bridge devices behind I2C controllersKarthikeyan Ramasubramanian
Currently devices behind I2C controllers are scanned using scan_smbus. This is done under the assumption that there are no bridge devices behind I2C controllers. In order to support I2C multiplexers which act as bridge devices and have devices behind them, scan the I2C controllers using scan_static_bus. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that all the bridge devices behind I2C controller are scanned and enabled. Change-Id: I9d8159a507683d8c56dd5e59d20c30ed7e4b2cab Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12util: Add DDR4 generic SPD for H5ANAG6NCJR-XNCNick Vaccaro
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC. BUG=b:161772961 TEST=none Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12soc/intel/jasperlake: Remove GPIO community 2 from DSDTEvan Green
The kernel driver enumerates communities 0, 1, 4, and 5, and assigns these addresses based on the BARs enumerated by coreboot. Coreboot was defining communities 0, 1, 2, 4, and 5. This meant the kernel was not controlling GPIOs in communities 4 and 5, since the resources were wrong. Remove community 2 for now. We can add it back if the kernel ends up needing it. BUG=b:169444894 TEST=Test controlling GPP_E5, verify actually toggles register. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46115 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/intel/tigerlake: Add chipset devicetreeDuncan Laurie
Add aliases for devices and set most of them to off with the exception of some essential devices. Set a default register value as an example. Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/intel/xeon_sp: Use generic config_tMarc Jones
Don't use the silicon-specific struct type to get common config options. Instead, use the generic config_t typedef. This allows the function to be moved to common code in upcoming patches. Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46057 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09trogdor: Modify DDR training to use mrc_cacheShelley Chen
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table. BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots. Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-09soc/intel/xeon_sp: Set CPU_ADDR_BITS to 46 for SKX and CPXChristian Walter
According to document number 338846 and 336062 this should be set to 46 bits. Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-10-09soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stackJonathan Zhang
Without skipping of DRHD generation for non-PCIe stack, the OS kernel detects incorrect DMAR table with following messages: [ 0.561817] Your BIOS is broken; DMAR reported at address 0 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I098605daf12a264f390613581427ec722afcddaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/45887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-09soc/mediatek: Add function to measure clock frequency of MT8192Weiyi Lu
Implement mt_fmeter_get_freq_khz() in MT8192 to measure frequency of some pre-defined clocks by frequency meter. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45402 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/intel/jasperlake: Add VR Configuration settingsMeera Ravindranath
This CL fixes the CPU Throttling issue. BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-08Revert "soc/intel/jasperlake: Disable PAVP UPD"Nico Huber
This reverts commit 69589294c205b616e80cafbbfb0b33e105a75386. No reason was given why this should deviate from the other platforms and the author can't explain it. Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMXChristian Walter
Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45869 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17Johnny Lin
For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/xeon_sp/cpx: correct GSI bases for IO APICsJonathan Zhang
With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct the coreboot assignment of GSIs for IO APICs. Without this patch, there are following target OS boot messages: [    1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [    1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119] After this patch, the boot messages are: [ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127 Also without this patch, there is boot stability issue. About one in 20 reboots, the target OS fails to boot with following failure: [ 4.325795] mce: [Hardware Error]: Machine check events logged [ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d The MCE error happens in bank 9. The Model specific error code shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means something goes wrong when cache write back to mmio. It is a generic transaction type error in level 2. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/mediatek: Add function to raise the CPU frequency of MT8192Weiyi Lu
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq(). Implement mt_pll_raise_little_cpu_freq() in MT8192. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-08lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEWAngel Pons
There's no need to make so much noise when writing IOBP registers. Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-08soc/intel: Make use of common gfx.aslSubrata Banik
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/common/block/acpi: Factor out common gfx.aslSubrata Banik
This patch moves gfx.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot CML platform. 1) Dump and disassemble DSDT, verify GFX0 device present inside common gfx.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/amd/picasso: Remove xhci0_force_gen1 from soc configChris Wang
To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead. The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1. Now variant can use the usb3_port_force_gen1 to customize which port it needs to limit. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-08soc/amd/picasso: Add UPD for support force USB3 to Gen1 by portChris Wang
Add UPD usb3_port_force_gen1 for support USB3 port force to gen1. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-10-08soc/amd/picasso: Print values from PSP transfer bufferMartin Roth
The PSP will now pass us data on the PSP boot mode and the production silicon level. Print these values out to save in the log. These definitions are in a vendorcode include directory that was previously only included in verstage. Add the include directory to all stages. BUG=b:170237834 TEST=Build & Boot - See values printed. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-10-08soc/amd/picasso: Refactor transfer buffer checkMartin Roth
The transfer buffer check had gotten large enough to deserve a function of its own, so break it out. BUG=None TEST=Build Branch=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46112 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/amd/picasso: Die if the workbuf is missing two boots in a rowMartin Roth
BUG=b:169199392 TEST=Corrupt vboot signature to force an error, see that the system halts instead of rebooting forever. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45964 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07sc7180: Remove LIMITS_CFG loading in romstage.mkurumel
LIMITS_CFG is not used/required by trogdor. Supporting this requires an FMAP partition as well as code, removing this support saves space and maintenance headaches. Change-Id: I9f57f5b520599ba6d708c91df9851e0e86b4b6c0 Signed-off-by: Manideep Kurumella <mkurumel@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45704 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07amd/picasso/psp_verstage: use cbmem consoleKangheui Won
psp_verstage uses separate printk implementation, which does not include code to add console output to cbmem. Add cbmemc_init and cbmemc_tx_byte to add console output to cbmem. BUG=b:159220781 TEST=build BRANCH=zork Change-Id: I63ba5814903565c372dbeb50004565a371dad730 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46059 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07amd/picasso/psp_verstage: Add modexp svc wrapperKangheui Won
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp svc call. BUG=b:169157796 BRANCH=zork TEST=build verstage for zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-06templates: add an empty SPD to SPD_SOURCESPaul Fagerburg
Add an empty SPD in SPD_SOURCES when creating a new variant of hatch, volteer, waddledee, or waddledoo, so that coreboot can build successfully. For variants that use spd_tools, add an empty mem_parts_used.txt so that the developer can add the supported memory parts and regenerate the Makefile.inc with the correct SPD references. Add an empty SPD for LPDDR4x for waddledee and waddledoo to use. BUG=b:169422833 TEST=create a new variant of hatch, volteer, waddledee, and waddledoo. Observe that each one succeeds. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-06soc/intel/xeon_sp/skx: Move get_srat_memory_entries()Marc Jones
Prepare for common ACPI code. Move get_srat_memory_entries() from soc_util.c to soc_acpi.c where the other srat ACPI functions are located. Change-Id: If26641497e1c16d5cf493490711aa08d6e1cb640 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45846 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/cpx: Don't use SCI defineMarc Jones
Continue preparations for common ACPI code. Add code from skx and common/acpi to check the SCI register instead of using a define. Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/skx: Move soc specific ACPI functionsMarc Jones
Prepare for common ACPI code. Move skx soc ACPI functions to a separate file. Change-Id: I12526c17a0dcbc45494ae19c8abaf8bf9a1eab47 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/cpx: Move soc specific ACPI functionsMarc Jones
Prepare for common ACPI code. Move cpx soc ACPI functions to a separate file, soc_acpi.c Change-Id: I4aaca660e2f94d856676681417ae6c5d8c28a1f1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/skx/: Reorder acpi.c functionsMarc Jones
Reorder the functions to make it easier to compare with soc/intel/common/block/acpi/acpi.c and cpx/acpi.c. Move the xeon_sp specific functions to the top. Change-Id: I7bc147781261c2fc39374f5bfe3ba79047b4993a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/cpx/: Reorder acpi.c functionsMarc Jones
Reorder the functions to make it easier to compare with soc/intel/common/block/acpi/acpi.c. Move the xeon_sp specific functions to the top. Change-Id: I9034eb774a14ee1e2f9b16c7bd7673ebad69c113 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/acpi: Break out the ACPI PCH IRQ ASLMarc Jones
Continue separating the CPU from the PCH. Move the PCH IRQ ASL from the uncore_irq.asl to a new file, pch_irq.asl. Change-Id: Iaf8ae87ecc9f8365cc093516f15d9c5a31c7d1d5 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/acpi: Move ACPI macros to a header fileMarc Jones
Move ACPI macros to a header file to be used in multiple ASL files. This could be moved to intel/common in the future to reduce the amount of duplicate ASL code. Tested by checking build/dsdt.asl doesn't change. Change-Id: Id2441763fe335154048c9a584a227a18e8c5391c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/acpi: Remove ASL Package() NumElementsMarc Jones
Remove the NumElements and allow the ASL compiler to fill them in. This is safer than hard coding the NumElements. For Package (NumElements) {PackageList}, "If NumElements is absent, it is automatically set by the ASL compiler to match the number of elements in the PackageList" ACPI v6.2 sec 19.6.101. Change-Id: I73df9e31011ad0861d4755fdbcbbd93e4e0b5a51 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/alderlake/ramstage: Fix compilation issueSubrata Banik
Refer to commit 0359d9d (soc/intel: Make use of PMC low power program from common block) commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common code) commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code) commit 8971ccd (soc/intel: Move pch_misc_init() to common code) for details Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/alderlake/acpi: Add SoC ACPI directory for ADLSubrata Banik
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake up from sleep states. 3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH, LAN, HDA etc. Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/tigerlake: Update TCSS PM flowJohn Zhao
There is requirement to change PM flow for S0ix along with TBT firmware update under device attached and no device attached scenarios. This change invokes D3CE and D3CX in DMA _PS3 and _PS0 respectively. BUG=b:158777291 TEST=Validated s0ix cycles for USB4 device attached and no device attached test cases along with updated TBT firmware rev35. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-05soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()Nick Vaccaro
Consolidate all weak declarations of mainboard_get_dram_part_num() to instead use the common definition in lib/spd_bin.c. BUG=b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify build succeeds without error. Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05soc: move mainboard_get_dram_part_num prototype to memory_info.hNick Vaccaro
BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify they build successfully. Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro
Change mainboard_get_dram_part_num() to return a constant character pointer to a null-terminated C string and to take no input parameters. This also addresses the issue that different SOCs and motherboards were using different definitions for mainboard_get_dram_part_num by consolidating to a single definition. BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch coreboot" and verify build completes successfully. Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45873 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/elkhartlake: add __weak to mainboard_get_dram_part_num()Nick Vaccaro
Add missing __weak declaration to Elkhart Lake's definition of mainboard_get_dram_part_num(). BUG=b:169774482, b:168724473 TEST=none Change-Id: I883d662315a9ab91eb6183ebcdfd7e7cc8064c64 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45871 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/tigerlake/acpi: Convert 'pch_hda.asl' into ASL 2.0 syntaxSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I8deaeb29abed097d536f1c3c44606a549c6af4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common ish.aslSubrata Banik
This patch moves ish.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CML platform. 1) Dump and disassemble DSDT, verify ISHB device present inside common ish.asl is still there with correct _ADR value. 2) Verify no ACPI error seen while running 'dmesg` from console. CML platform: Device (ISHB) { Name (_ADR, 0x00130000) // _ADR: Address Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name } TGL/JSL platform: Device (ISHB) { Name (_ADR, 0x00120000) // _ADR: Address Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name } Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I33c1649d7a632c7b147e1bf307cfb5c1dfd84c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntaxSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/skylake: Align platform.asl with CNLSubrata Banik
Refer _WAK and _PTS ASL functions from common platform.asl TEST=Dump and disassemble DSDT, verify all methods present inside common platform.asl like _WAK, _PTS etc. are still there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I625e42b3c49abbb3595a4307da5fc24850a98fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/45980 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik
This patch moves smbus.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify SBUS device present inside common smbus.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05mb/{google,intel}/{volteer,tglrvp}: Refer to common IPU ASLSubrata Banik
Delete SoC local copy of ipu.asl and refer from common block ipu.asl TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device present there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/jasperlake: Delete unused ipu.aslSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I8c7363d442ed40c36fc01dc3608bab864865f29d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45977 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block: Rename IPU ACPI deviceSubrata Banik
IMGU->IPU0 to align with other SoC IPU entires. TEST=Dump and disassemble DSDT on poppy, verify IPU0 device present there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I803c01f9156a56dbd903b6ba7897cc0f96b0a26a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik
This patch moves pch_glan.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify GLAN device present inside common pch_glan.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/alderlake/ramstage: Do initial SoC commit till ramstageSubrata Banik
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp/acpi: Rename pci_irq.aslMarc Jones
Rename pci_irq.asl to pci_irqs.asl to match other intel soc file names. This makes comparing differences much easier. Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45834 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Clean up pci_devs.hMarc Jones
Prepare for merging cpx and skx pci_devs.h. Remove duplicate defines. Move defines so they match each other. Checked TiogaPass and DeltaLake BUILD_TIMELESS. Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Make use of PMC low power program from common blockSubrata Banik
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function. Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/common/block/pmc: Add PMC API for low power programmingSubrata Banik
List of changes: 1. Create Kconfig to select pmc low power program by SoC 2. Add API to make ACPI timer disable 3. Add API to ignore XTAL shutdown for SLP_S0# assertion Change-Id: I017ddc772f02ccba889d316319ab3d5626b80ba5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Move pch_misc_init() to common codeSubrata Banik
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move soc_pch_pirq_init() to common codeSubrata Banik
List of changes: 1. Rename soc_pch_pirq_init() as pch_pirq_init() and move into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move pch_enable_ioapic() to common codeSubrata Banik
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp/include: De-duplicate .h filesMarc Jones
Move duplicate .h files to top level xeon_sp/include/soc from silicon specific cpx/include/soc and skx/include/soc. Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45221 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Prepare acpi.* for mergingMarc Jones
Clean up acpi.h in preparation for merging with cpx/ acpi.* files Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45218 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Use common ASL code for xeon_spMarc Jones
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. TiogaPass coreboot.rom checked with BUILD_TIMELESS. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Fix uncore.asl \_SB namespace issueMarc Jones
The skx uncore ACPI scope was missing the \ on \_SB causing the uncore IRQs to not be in the namespace. This addresses ACPI uncore IRQ routing issues. This was found preparing skx acpi to match cpx acpi for merging in the future. Check scope in dsdt.asl in tiogapass build. Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45269 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notationMarc Jones
Prepare for merge with cpx. Use the C style operators instead of the ACPI1.x polish notation. This is much easier to read and matches the cpx code. This generates the same ASL code. Checked with BUILD_TIMELESS on TiogaPass. Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update uncore IRQ routing ACPI tablesMarc Jones
Update the skx uncore ACPI routing tables to match cpx. This adds the IRQ routing for B-D for legacy and IOAPIC modes. Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-02soc/intel/braswell: Increase dcache sizeShelley Chen
Increase the DRAM cache size for Braswell to address the compilation error Cache as RAM area too full when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-30soc/amd/picasso: Add fields for the PSP to the transfer structMartin Roth
The PSP will be adding information into these fields after verstage runs. This allows data to be passed directly to coreboot very early in the boot process. BUG=b:168895748 TEST=None Branch=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-30soc/intel/tigerlake: Set TME upd param based on configPratik Prajapati
Set TmeEnable FSP-M upd based on config. TEST: TME ENABLE and LOCK bits get set when Tme is enabled. Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30soc/intel/icelake/acpi/gpio.asl: Correct GADD methodAngel Pons
Some cases are inconsistent. Refer to the 495 series on-package PCH to confirm which GPIO pads are the first for each community and fix it. Change-Id: Ie4c4c12c6629478d754f55fa3fb75fa16eb01335 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30soc/intel/skylake: Move PMC MMIO offset macro into pmc.hSubrata Banik
This patch ensures PMC offset 0xfc resides into pmc.h rather defining into p2sb.h. Change-Id: Iae1c38beae15355a077be80112b723b8ad3d0a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45800 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/skylake: Align PMC offset 0x31C name with CNLSubrata Banik
As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename CIR31C with CPPMVRIC. Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/skylake: Align soc_pch_pirq_init() with CNLSubrata Banik
This patch replaces pch_interrupt_routing[] with PCH_IRQx macro. Change-Id: I9645b0e185bcde7b27da35863564dbcf73850e8c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45788 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/apollolake: Add PCH_IRQx into irq.hSubrata Banik
This patch is needed to make use of LPC common code. Change-Id: I5d0e8dbf8f8e52caf4ba78c0e3969efaac387204 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-29soc/intel/jasperlake: Add IGD, MCH Device IDKrishna Prasad Bhat
Add IGD Device ID and MCH Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: I00ee7950ffa378b428a76bf367a9a05ab287e7ed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29soc/intel/common: Add config option to enable TME/MKTMEPratik Prajapati
Add config option to enable TME/MKTME. The spec is available at: "https://software.intel.com/sites/ default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption- Spec.pdf" Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I181aed2bf4a79005fe42e3e133b5faee91201dad Reviewed-on: https://review.coreboot.org/c/coreboot/+/45087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-28Revert "soc/intel/xeon_sp: Improve performance efficiencies"Subrata Banik
This reverts commit d51449d017410fedb55e93f71fb322749ba888b5. Reason for revert: Causing compilation issue as below src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa': src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] &hob->PlatformData.IIO_resource[socket]; ^ Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28soc/amd/picasso: Set eMMC preset UPDsRaul E Rangel
Now that all boards have bootable driver strengths and init frequency, we can pass them to FSP. BUG=b:159823235 TEST=Boot ezkinil to kernel and print presets. SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x3ff: SdClkFreq SDHC0x8F2 Default Speed 3.3V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8F4 High Speed 3.3V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8F6 SDR12 1.8V => 0x0008 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x8: SdClkFreq SDHC0x8F8 SDR25 1.8V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8FA SDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8FC SDR104 1.8V => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq SDHC0x8FE DDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x900 HS400 => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28soc/amd/picasso: Add eMMC driver strength and init kHz settingsRaul E Rangel
This allows passing in the presets to FSP. I will set the UPD values after all the zork boards have had their presets correctly set. This way we don't override the UPD defaults with 0s. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28soc/intel/xeon_sp/cpx: add ACPI name for CSTACKJonathan Zhang
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table generated. The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment does not support multiple PCIe stacks, eg. IIO stacks. For now, assign the name to PCIe domain. In future, the name needs to be assigned to CSTACK. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I24a6f29734452426218419cdcf66702edde96f46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-28soc/intel/common/block/lpc: add acpi nameJonathan Zhang
Add ACPI name for LPC device. The name matches with what is in soc/intel/common/block/acpi/acpi/lpc.asl. Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC, remove duplicated acpi name assignments. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28soc/intel/common/../pmclib.h: Include <types.h>Angel Pons
This file uses `bool` and `size_t` types, so <stdint.h> isn't enough. Change-Id: I8099142d92cc8ca6721f76522f3d30d4b6b9ee80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28soc/intel/xeon_sp: Improve performance efficienciesJohn Zhao
Coverity detects performance inefficiencies as IIO_RESOUCE_INSTANCE structure (size 623 bytes) is PASS_BY_VALUE. Fix it with PASS_BY_REFERENCE. Found-by: Coverity CID 1432759 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/45608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28soc/intel/skl: Fix error code of send_global_reset()Nico Huber
With commit f2eb687d19 (soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_message()) the return value was changed on a single path. Update the other paths too, even though it's the discouraged 0-is-failure. Change-Id: I179a6a4b1e13565dd58c908eb2a9725052a4de9d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28util: Add new memory part for zork boardsAmanda Huang
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-27soc/intel/icelake/acpi/gpio.asl: Use ASL 2.0 syntaxAngel Pons
While we're at it, fix up cosmetics on a few comments. The GADD method seems to suffer from copy-paste symptoms. A follow-up will address this. Some methods deliberately remain untouched in this commit, so as not to collide with another patch train that already takes care of them. Tested with BUILD_TIMELESS=1, Intel Ice Lake U RVP does not change. Change-Id: I613f5f65638b92ca23f3ce15a15dd063afa52c31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-27soc/intel/skylake/acpi/gpio.asl: Use ASL 2.0 syntaxAngel Pons
While we're at it, fix up cosmetics on a few comments. Some methods deliberately remain untouched in this commit, so as not to collide with another patch train that already takes care of them. Tested with BUILD_TIMELESS=1, Purism Librem 15v4 does not change. Change-Id: Ib27c5b48459e3ea7eabc34457cb204994ee9b617 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45691 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27soc/intel/broadwell/cpu.c: Spell `CPU` in uppercaseAngel Pons
Change-Id: I54f96911b744f1737f7141c8a96329c95ace529d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-27soc/intel/*/chip.h: Use `uint32_t` for `tcc_offset`Angel Pons
Newer platforms use an unsigned type instead of an int. Follow suit. Change-Id: I316864d3aed203c7c2bc962772895774fbc0c8da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-27soc/intel/alderlake: Add GPIOs for Alder Lake SOCSubrata Banik
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following 5 GPIO communities and 13 GPIO groups: Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0 Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-27soc/intel/common/block/acpi: Factor out common gpio_op.aslSubrata Banik
This patch moves gpio_op.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify all methods present inside common gpio_op.asl like GRXS, GTXS etc. are still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-27soc/intel/skylake: Use GPIO state macros from intelblocks/gpio_defs.hSubrata Banik
TEST=Able to build and boot EVE platform. 1) Dump and disassemble DSDT, verify unified methods like GRXS, GTXS etc. are there 2) Verify no ACPI error seen while running 'dmesg' from console 3) abuild --timeless to ensure there are no other functional changes. Change-Id: I02df3ddf5ad33d42d97feefb0fa366ad8c856565 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45681 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27soc/intel/icelake: Use GPIO state macros from intelblocks/gpio_defs.hSubrata Banik
TEST=Able to build and boot ICLRVP platform. 1) Dump and disassemble DSDT to ensure GRXS function implementation remain unchanged prior and after this CL. 2) Verify no ACPI error seen while running 'dmesg' from console. 3) abuild --timeless to ensure there are no other functional changes. Change-Id: Iab4690341bc3da5d8eb249da4d407d84f7d4e706 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45680 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27soc/intel/cannonlake: Align gpio_op.asl with TGLSubrata Banik
Also drop gpio_common.h in favor of intelblocks/gpio_defs.h macros. TEST=Able to build and boot CNL and CML platform. 1) Dump and disassemble DSDT, verify unified methods like GRXS, GTXS etc. are there. 2) Verify no ACPI error seen while running 'dmesg' from console. 3) abuild --timeless to ensure there are no other functional changes. Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45654 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27soc/intel/{jsl,tgl}: Fix GRXS function to get GPIO number properSubrata Banik
This patch ensures that GRXS perform PAD_CFG0_RX_STATE mask first and then right shift PAD_CFG0_RX_STATE_BIT to get correct GPIO number. Change-Id: I96611936f70f79e9dc5ee9414ec68cef00d0d13a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45738 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-26soc/intel/apollolake: Drop select SMPKyösti Mälkki
The SOC has MAX_CPUS>1 so this is redundant. Change-Id: Icb4c7551031f4e32e01198261ee9ae9b95f18142 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 02:08:44 +0000