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2023-02-06soc/intel/apl: Hook up cpu ops in devicetreeArthur Heymans
This simplifies the code flow of the cpu init. APL can do CPU init after calling FSP-S, while GLK needs to do that before. This is now reflected directly in the cpu ops rather than using CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT as a proxy. Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-02-04soc/amd/phoenix/chipset.cb: update USB portsFelix Held
Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: add remaining PCI devicesFelix Held
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2Felix Held
Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1Felix Held
Only the PCIe ports on the functions of device 2 were present in the devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the missing PCIe ports on the functions of device 1 and assign the amd_external_pcie_gpp_ops ops to them. This SoC uses a slightly different naming scheme for its PCIe GPP ports. Previously the PCIe GPP bridge number from the PCI Device ID Assignments table from the PPR was used. Those bridge numbers are one less than the function numbers of the device. This is due to function 0 being a dummy bridge to avoid having to shuffle around the function numbers when the first bridge is unused, since the PCIe specification mandates the function 0 to be implemented if any other function on the same device is implemented. In order for the device aliases to be consistent with the PCIe device and function numbers which is way more commonly used and also what lspci shows and what goes into the DXIO descriptors, change the naming scheme of the aliases. This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72736 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/intel/meteorlake: Enable MRC Fast BootSubrata Banik
This patch requests FSP to enable the MRC fast boot feature along with FSP v2473. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4a621e55c853505f7a702181ae5a70dc56d5b5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72745 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridgesFelix Held
Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree") missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge PCIe ports, so add them. Those devices were previously covered by the PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that got removed in the referenced commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04soc/amd: Use common reset code for PCO SoCMartin Roth
This switches the Picasso SoC to use the common reset code. Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET flag. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Use common reset code for PHX & Glinda SoCsMartin Roth
This switches the Phoenix & Glinda SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Use common reset code for CZN & MDN SoCsMartin Roth
This switches the Cezanne & Mendocino SoCs to use the common reset code. This patch does not change any behavior on those chips. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Create AMD common reset codeMartin Roth
This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_AMD_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/intel/*: Fix dead bootstate codeArthur Heymans
No bootstate hook is called on exit of BS_OS_RESUME or BS_PAYLOAD_BOOT. Change-Id: I2b5b834d0663616a9523fd119f007e3bac8e7bf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-02-04soc/intel/tgl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-03soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev treeKane Chen
This commit provides a dev tree setting for partners to enable/disable TccoldHandshake for the sighting in doc:723158 BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=compile ok and FSP UPD is config properly Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68635 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/alderlake: Add a few missing definitions in iomap.hJeremy Compostella
Some reserved address range listed in Alder Lake Platform Firmware Architecture Specification document 626540 section 6.4 ADL - System Memory Map such as North TraceHub ranges were missing. Details about North TraceHub (aka. Intel TraceHub) can be found in Intel Trace Hub (Intel TH) Developer's Manual document 671536. BUG=b:264648959 TEST=Compilation successful Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-03soc/intel/alderlake: Add a missing RPL-P power limits configurationJeremy Compostella
This patch adds the {MCH:a706, TDP:28W} missing 28W configuration. BUG=b:267666609 BRANCH=firmware-brya-14505.B TEST=Power Limit are properly set on skolas 28W Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-02soc/intel/alderlake: Add entries to eventLog on invocation of early SOLTarun Tuli
If we show the user early signs of life during CSE FW sync or MRC (re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:264648959 TEST=event shows in eventlog after CSE sync and/or MRC Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Signed-off-by: Tarun Tuli <taruntuli@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71295 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-02-02soc/intel/xeon_sp: add Kconfig file for SPR-SPJonathan Zhang
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. Change-Id: I14cf115b02d8edff9b48e744b798a3b1ba18b8bf Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-02soc/intel/meteorlake: Enable V1p05-PHY supply external FET controlSubrata Banik
This patch enables S0i2.2 by letting 1.5V Phy supply to control the externa FET. BUG=b:256805904 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72709 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-02soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUSLiju-Clr Chen
USB1_DRV_VBUS is used to provide 5V power for USB on MT8188 EVB and it's not used on Geralt. Therefore, remove the GPIO setting of USB1_DRV_VBUS. TEST=read usb data successfully. BUG=b:236331724 Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72641 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/qualcomm/sc7280: Memlayout change to support new Crypto sha updateVenkat Thogaru
With New Crypto upgrade we need to have 1 block of 4Kb increase in romstage, by which we can see an improvement of Boot performance by 100 msec. BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board Boot performance improved by 100 msec observed. Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-01soc/qualcomm/common/qup: Avoid double decompress of gsi_fw blobSudheer Kumar Amrabadi
During boot, gpi_firmware_load gets called twice because there are 2 serial engines. Thus gsi_fw blob is also decompressed twice and is written to base addresses of SEs. This is redundant. Perform the decompression once on first call and save the header in static variable which can be reused in next call. BUG=b:262426214 TEST=Validated on qualcomm sc7280 development board Saving of 80ms observed while testing with 130 boot cycles. Change-Id: If98a3974f0791dffdf675c02cc28375d0485c485 Signed-off-by: Vijaya Nivarthi <vnivarth@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71927 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/amd/mendocino: Force resets to be coldMartin Roth
Like Cezanne, Mendocino does not support warm resets. Change all resets (including resets in the OS) to cold resets (like Cezanne). BUG=b:248221908 TEST=Run suspend_stress_test, then reboot Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72486 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-01soc/intel/jsk: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/skl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic42c67163fe42392952499293e91e35537cb9147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/cnl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-01soc/intel/mtl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM. DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid a potential error seen in ADL devices as mentioned in commit 3fd5b0c4cdeb ("soc/intel/adl: remove DPTF from D-states list used to enter LPM") TEST=Built and tested on Rex, saw SSDT generated properly. BUG=b:231582182 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I9192ed9a7fb59ebba14f6d5082b400534b16ca72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72603 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/amd/glinda/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iec9cf7c195fa5cb5c8d992aeab400d05cbe801c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/phoenix/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I103cdce8c23ff4adbf1057fa26bd67275f2ab0e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/mendocino/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I036dcddf89e8d865d0dc3ef0bd9e48842d8bf6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/cezanne/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77a91c0a6d937772bf25fa936cec8a710b9acf72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/picasso/acpi: use acpigen_write_processor_deviceFelix Held
In CB:71614 Kyösti pointed out that ACPI_GPE0_BLK is the wrong address to assign to proc_blk_addr; the correct one would be ACPI_CPU_CONTROL. When looking a bit closer into this, it turned out that acpigen_write_processor is generating deprecated AML opcodes, so replace the acpigen_write_processor call with a call to the newly added acpigen_write_processor_device function that also doesn't have the proc_blk_addr and proc_blk_len parameters. The information about the IO port for entering C-states is already written into an SSDT by acpigen_write_CST_package which is likely also the reason why the wrong proc_blk_addr value wasn't noticed for a very long time. TEST=Mandolin still boots Ubuntu 22.04 LTS and Windows 10 and no possibly related errors show up. Linux gets the expected C-state information from the _CST package inside the processor device scope. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie67416e19e431029dd12da66ad44ddfa8586df03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL defineFelix Held
This register isn't used in coreboot and isn't defined in the Picasso PPR #55570 Rev 3.18. To enter a lower C-state, a read request to a special IO port is done. The base address of this group of IO ports is configured in set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave the CPU. IIRC trying to put the MMIO mapping for entering the lower C-states into the _CST package didn't work as expected when it was tried on I think Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-31soc/intel/ehl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I7dfd331e70f6d03c88248ca5147dbe6785a8e69d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-31soc/intel/alderlake: Pick an unused and safer graphics address spaceJeremy Compostella
It turns out that the [0xfa000000-0xfaffffff] range conflicts with some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and [0xfacfc000-0xfacfffff]). Experiments have established that this conflicting range results in an unpected PIPE A underrun issue reported by i915 and some visible flickers on the display during boot. The [0xf0000000-0xffffffff] range is a crowded memory space with resources statically assigned to some devices but also some ranges used at various point in the boot flow by the FSP. To not run into any other potential conflicts, we want to pick a unused memory space. But at this early stage of the boot, we do not have full knowledge of what memory space is going to be used by the FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range as: 1. It does not conflicting with any coreboot memory space usage 2. It is the address the FSP uses by default for GFX MMIO BAR0 and as such should not conflict with any FSP memory space usage. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=No flickers observed on boot Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-31soc/intel/apl: Ensure CPU_CLUSTER linked_list bus existsArthur Heymans
This fixes a NULL pointer deref introduced by 69cd729 (mb/*: Remove lapic from devicetree). Change-Id: I816fddfe3efe3c3aefe1b2ee28426dc1e1f3c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72599 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31soc/intel/common/block: Add LPC BIOS decode lockTim Chu
The LPC BIOS decode lock bit is defined in EBG EDS documentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71954 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-29soc/intel/xeon_sp/Kconfig: add SOC_INTEL_SAPPHIRERAPIDS_SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) chipset belongs to Xeon-SP family. It was product launched on Jan. 10, 2023. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifece05e2fbcc454cdee8e849cb4f146c89f54333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-29soc/intel/xeon_sp/include/soc/pmc.h: move to lbg directoryJonathan Zhang
The PMC registers are quite different between LBG and EBG. Move pmc.h to lbg directory to differentiate. Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-28soc/intel/common/block/acpi/pep: use acpigen_write_processor_namestringFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43590f0f792fca1c90ee8f8b32e6be47943c59df Reviewed-on: https://review.coreboot.org/c/coreboot/+/72453 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27intelblocks/cse: Add functions to check and change PTT stateMichał Żygowski
Add functions that allow checking and changing PTT state at runtime. Can be useful for platforms that want to use dTPM instead and have no means to stitch ME firmware binary with disabled PTT. The changing function also checks for the current feature states via HECI to ensure that the feature state will not be changed if not needed. TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-01-27soc/intel/adl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid an error seen after it was added to that table: "ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.DPTF (20200925/dspkginit-438)" TEST=Built and tested on anahera and saw the error is gone BUG=b:231582182 Change-Id: I00eddd7e4cc71a0c25e77ff53025dee5bf942de1 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-27soc/intel/mtl: Add missing claimed memory regionsEran Mitrani
This CL adds claimed memory regions that were missing for the resource allocator. See commit ca741055e6b6 ("soc/intel/adl: Add missing claimed memory regions") for details. TEST=Booted rex and saw the previously missing ranges getting added from AP Log (with this CL): SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000 SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000 SA MMIO resource: LT_SECURITY -> base = 0xfed20000, size = 0x00060000 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000 SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000 SA MMIO resource: DSM -> base = 0x7c000000, size = 0x04000000 SA MMIO resource: TSEG -> base = 0x7b000000, size = 0x00800000 SA MMIO resource: GSM -> base = 0x7b800000, size = 0x00800000 dmesg: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x00000000759c9fff] usable BIOS-e820: [mem 0x00000000759ca000-0x000000007fffffff] reserved BIOS-e820: [mem 0x00000000c0000000-0x00000000e0ffffff] reserved BIOS-e820: [mem 0x00000000f8000000-0x00000000f9ffffff] reserved BIOS-e820: [mem 0x00000000fd800000-0x00000000fe7fffff] reserved BIOS-e820: [mem 0x00000000feb00000-0x00000000feb7ffff] reserved BIOS-e820: [mem 0x00000000fec00000-0x00000000fecfffff] reserved BIOS-e820: [mem 0x00000000fed20000-0x00000000fed83fff] reserved BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved BIOS-e820: [mem 0x00000000fedc0000-0x00000000feddffff] reserved BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable BIOS-e820: [mem 0x000003fff0aa0000-0x000003fff0aa1fff] reserved Change-Id: I749e7b6e969f8d6314fcd2906acd7de69d4d9f9c Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-26soc/intel/alderlake: Wait for panel power cycle to completeJeremy Compostella
The Alder Lake PEIM graphics driver executed as part of the FSP does not wait for the panel power cycle to complete before it initializes communication with the display. It can result in AUX channel communication time out and PEIM graphics driver failing to bring up graphics. If we have performed some graphics operation in romstage, it is possible that a panel power cycle is still in progress. To prevent any issue with the PEIM graphics driver it is preferable to ensure that panel power cycle is complete. This patch replaces commit ba2cef5b5493 ("soc/intel/common/block/early_graphics: Introduce a 200 ms delay") workaround patch. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible in the recovery flow Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26drivers/intel/gma: Use libgfxinit Update_Output to turn off graphicsJeremy Compostella
We were using the libgfxinit `Initialize' function with the `Clean_State' parameter because the more appropriate `Update_Output' function was not performing all the necessary clean up operations for the PEIM driver to be successful when libgfxinit was used in romstage. Thanks to a lot of experiments and some log analysis efforts, we were able to identify the missing operation and fix the `Update_Output' function (cf. https://review.coreboot.org/c/libgfxinit/+/72123). The `initialized' global variable is now unnecessary as we track the initialization in the Ada code instead. Since the `Update_Output' function does not return any value, this patch modifies the `gma_gfxstop' prototype accordingly. This does not have any impact as the return value was not used anyway. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-25soc/intel/mtl/acpi: add FSPI to DSDTEran Mitrani
Getting an error from the Kernel on Rex devices: > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI (20210730/dspkginit-438) FSPI is defined in src/soc/intel/meteorlake/chipset.cb: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. See commit feed8e4bd9dc ("soc/intel/adl/acpi: add FSPI to DSDT") for the corresponding ADL CL. TEST=Built and tested on brya by verifying the error is gone. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id8d2a1b5e074f036345e028b117d420bf36a9042 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-25soc/intel/common/gpio: Add function to read GPIO TX valueCliff Huang
This function reads out the current value set to output for a GPIO pin. Ex: GPP_E0 is set to output int e0_val; e0_val = gpio_tx_get(GPP_E0); Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-25soc/intel/alderlake: Increase premem cbmem buffer size to 16KBTarun Tuli
Current size of the cbmem premem buffer (8KB) is sometimes insufficient to contain the complete debug log causing the cbmem console buffer to indicate overflow. This patch increases the premem cbmem buffer size to 16KB so that the complete debug log can be stored in it. TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Change-Id: I60c68322c52191eabf7e06b4be06e66f90ff8751 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25soc/intel/cmn/block/pcie: Make ASPM configurableMaximilian Brune
Currently ASPM cannot be disabled by individual mainboards, if the soc Kconfig includes SOC_INTEL_COMMON_PCH_CLIENT. Other options like PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE are already configurable by individual mainboards if needed. This change makes PCIEXP_ASPM one of these configurable options. Test: build prodrive/atlas and see that build/config.h lists the option CONFIG_PCIEXP_ASPM as disabled. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic9c049f1d225bc21d8da5bd208651ad847ae0c6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72117 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-24soc/intel/alderlake: Increase cbmem buffer size for the debug imageTarun Tuli
Currently most of the FSP debug messages (when enabled) are truncated due to insufficient size of cbmem buffer. Increase premem cbmem console size to 0x16000 bytes and cbmem buffer size to 0x100000 bytes so that cbmem buffer can contain most of the debug logs when FSP debug messages are enabled. TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled but MRC debug message. Change-Id: I0273fb14916f213b686270a9dec4c1b47612af4d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/alderlake: Increase cbmem buffer size to 256KBTarun Tuli
Current size of the cbmem buffer (128KB) is insufficient to contain the complete debug log causing the cbmem console buffer to wrap. This patch increases cbmem buffer size to 256KB so that the complete debug log can be stored in it. TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Change-Id: I2099386dd87a010c3a5937bd896620270f587b1c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71288 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. The chipset includes Emmitsburg PCH. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-24soc/intel/alderlake: Implement API to disable UFS controllersSubrata Banik
This patch implements a new API to make the UFS controller function disabled. Additionally, perform a warm reset post disabling the UFS controller to let PMC know about the state of the UFS controller and disable the MPHY clock. BUG=b:264838335 TEST=Able to build and boot Google/Marasov successfully. From the AP log, I am able to confirm that UFS is function disabled using PSF. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I940a634f70f8c97ef1234866d4c5a1ff224c6e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-24soc/intel/adl: Option to create unified AP FW for UFS/Non-UFS SKUsSubrata Banik
This patch makes it easy for OEMs to keep a unified AP firmware image to boot different SKUs with UFS and non-UFS as boot media. With a unified image while booting on non-UFS SKU is exhibiting S0ix failure due to UFS remain enabled in the strap although FSP-S is making the UFS controller function disabled. The potential root cause of this behaviour is although the UFS controller is function disabled but MPHY clock is still in active state. A possible solution to this problem is to issue a warm reboot (if boot path is S5->S0 or G3->S0) after disabling the UFS and let PMC read the function disable state of the UFS for disabling the MPHY clock. Mainboard users with such board design where OEM would like to use an unified AP firmware to support both UFS and non-UFS sku booting might need to choose this config to allow disabling UFS while booting on the non-UFS SKU. Note: selection of this config would introduce an additional warm reset in cold-reset scenarios due to function disabling of the UFS controller. BUG=b:264838335 TEST=Able to build and boot Google/Marasov successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a811d8f4aad41dab6f8988329eaa1d590a4637a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-24soc/intel/cmn/pmc: Clear GEN_PMCON_x register power failure status bitsSubrata Banik
This patch calls into `pmc_clear_pmcon_pwr_failure_sts()` to clear GEN_PMCON_x register status bits after determining the `prev_sleep_state`. Having those bits being set across reboot might be misleading. For example: although the last boot was not due to power failure but the power failure bit still remains the same (unless cleared). Note: clearing `GBL_RST_STS` bit earlier than FSP-M/MRC having an adverse effect on the PMC sleep type register which results in calculating wrong `prev_sleep_state` post a global reset, hence, just clearing the power failure status bits rather than clearing the complete PMC PMCON_A register. BUG=b:265939425 TEST=Able to clear the GEN_PMCON_A register power failure bits aka BIT16 and BIT14 on google/marasov platform over next boot to avoid having its persistent effect. Without this patch: pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 ... GEN_PMCON: d0215238 00002200 With this patch: pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 ... GEN_PMCON: d1001038 00002200 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4f5dfe0251aeb85b667fbfc44fbf17b025aec090 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-24soc/intel/meteorlake: Convert chip config into snake caseSubrata Banik
This patch converts below chip configs from camel case to snake case to match with the other chip configs belongs to the chip structure. - SaGv - RMT Additionally, updated the `sagv` help text and operation as applicable based on the FSPMUPD.h file (belongs to the vendorcode). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I62e521cf3f46e888e2c995d83ac7dc666de1af82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-24soc/intel/cmn/pmc: Create API to clear PMC power failure status bitsSubrata Banik
This patch implements an API named `pmc_clear_pmcon_pwr_failure_sts()` to clear power failure status bits of PMC General PM Configuration A/B based on the underlying SoC. Based on the available PMC register definitions between Sky Lake till latest Meteor Lake platform, the SoC platform that selects SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION config has power failure bits mapped into the MMIO mapped GEN_PMCON_A register where else for the other SoCs, those power failure bits are belongs to the PCI config space mapped GEN_PMCON_B register. BUG=b:265939425 TEST=Able to build the google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icbbe47ccfd489edf9c38f52bdf7cf2de7aa9eedf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72053 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-24soc/intel/common/cse_lite: Allow specific operation prior to updateJeremy Compostella
Some boards may want to perform a specific operation before the CSE FW update final operation begins. For instance, on Brya this new callback can be used to inform the end-user that an update is in progress. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=Compilation success Change-Id: Ia4d32a71f3ae61d2e24197fee6b458512f7778a9 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72097 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/alderlake: Inform user during CSE updateJeremy Compostella
If a CSE update is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. CSE update can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=On screen text message during CSE update observed on skolas Change-Id: I28c4fef9345d577be287b76a2a767b5c852ec742 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72098 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-23soc/amd/mendocino/acpi: remove RTC wake workaroundFelix Held
Commit 78ee4889dc32 ("soc/amd/cezanne/acpi: Add support for RTC workaround") added a workaround for the Cezanne silicon. This was copied to the Mendocino code, but from both the discussion in b:209705576 and the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/ amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true Mendocino doesn't need that workaround, so remove it. TEST=Running suspend_stress_test -c 5 on Chausie shows no errors Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-23Revert "soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling"Elyes Haouas
This reverts commit 80b1fa33. Reason for revert: "Error: CONFIG() used on unknown value (ENABLE_FSP_ERROR_INFO) at src/soc/intel/xeon_sp/romstage.c:20" Change-Id: I843322fc9d7ebbc30e9209ae933313f2668bfa40 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-23soc/intel/meteorlake: provide a list of D-states to enter LPMEran Mitrani
Provide D-states to enter LPM (S0ix) for MTL Values were copied over from corresponding ADL file (as MTL data sheet is not yet available). TEST=Built and tested on Rex by verifying SSDT contents Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-23soc/intel/denverton_ns: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I3138edd8125601b6c9dff5f9252a4bba8385146d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-23soc/intel/xeon_sp: Remove NO_FSP_TEMP_RAM_EXIT from common configJohnny Lin
For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not be selected. Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-23soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu
After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I612393ffac90815606f3f2544bc1518f6912e605 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71952 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-22soc/amd/*: Enable override of MAINBOARD_BLOBS_DIRFred Reitberger
MAINBOARD_BLOBS_DIR is defined the same way by picasso/cezanne/mendocino/phoenix/glinda and unused by stoneyridge, so move it to a common area. This makefile variable is currently only used to locate APCB blobs for the different mainboards. Add a Kconfig option to point to the APCB blobs directory. This allows simple overriding to locations such as site-local. TEST=Timeless builds Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0702fdb97fbc2c73d97994ab4d5161ff0f467518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69410 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/stoneyridge,sb/amd/pi/hudson: Remove unused AHCI_ROM_IDElyes Haouas
Change-Id: I0a3a3d8b3f898dc147eff54fe4ae2611139951ac Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72143 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/intel/{adl,mtl,tgl}: change selection for ↵Matt DeVillier
DEFAULT_SOFTWARE_CONNECTION_MANAGER Needs to be selected for ChromeOS mainboards even for non-ChromeOS builds, else Thunderbolt/USB4 doesn't work under Windows (and likely Linux as well). TEST=build/boot Windows on drobit/banshee, verify TB functional Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22intel/common/block: Fix potential buffer overflowBora Guvendik
Possible Buffer Overflow - Array Index Out of Bounds. Array regions size is 256 but 'i' iterates from 0 to 256. Found-by: Klockwork BUG=None BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee45a5821b9dd3f9e6f9816599beebf34555426d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72049 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/stoneyridge: clean up global NVSFelix Held
Remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/picasso: clean up global NVSFelix Held
Remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79509146431e4584e50af4477f3f50dc3cf01bcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72138 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/intel/apollolake: Add PMC macros for common code usageSubrata Banik
This patch adds new macros (i.e. SUS Power Failure and Power Failure) from the APL EDS vol 1 (doc 569262) to be able to implement common code API to clear the power failure status bits. Note: as per the EDS those newly added power management failure bits are RO and shouldn't change any functionality of the existing APL SoC code. The reason behind adding those macro definitions is to fix the compilation issue due to code change targeted for the Intel SKL and Xeon-SP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0bbf11ada2b2f8735173be69ad157b8055021126 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72130 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/intel/denverton_ns: Add PMC macros for common code usageSubrata Banik
This patch adds new macros (i.e. SUS Power Failure and Power Failure) from the DNV EDS vol (doc 558579) to be able to implement common code API to clear the power failure status bits. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-21soc/intel/baytrail: Fix indentation for the PMC (pm.h) macrosElyes Haouas
This patch fixes the alignment of the PMC macros defined in the pm.h file. Change-Id: Ib5ff87e2f6524ca1be69027080149a3fbe2df7d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72158 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21soc/intel/braswell: Fix indentation for the PMC (pm.h) macrosElyes Haouas
This patch fixes the alignment of the PMC macros defined in the pm.h file. Change-Id: I9a55e1b099a53180e40eedcc52120d65558e7f8b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72157 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21soc/intel/apollolake: Fix indentation for the PMC (pm.h) macrosSubrata Banik
This patch fixes the alignment of the PMC macros defined in the pm.h file. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia8d35a5d104658b7900fde7f7b8c6f88530a614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72129 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/glinda,mendocino,phoenix/espi_util: add comment about registerFelix Held
Even though the register name begins with ESPI, it resides in the SPI registers and not in the eSPI registers, so add a comment to point this out to hopefully avoid some confusion. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20soc/amd/glinda/espi_util: update file to match documentationFelix Held
Checked against document #57396 revision 1.52 and removed the DIS_ESPI_MASCTL_REG_WR define, since that bit is marked as reserved. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e8b1c65118b4e85e7934e822a7a7e329746a88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-20soc/amd/phoenix/espi_util: remove TODO after checkingFelix Held
Checked against both documents #57019 revision 1.59 and #57396 revision 1.50 that the definitions and the code still apply to Phoenix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id65301ec730793f41044696f2e99356f2e899137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20soc/amd/glinda: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1c3c25591deadb27b7bf38a81dcd6fe746de55b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72096 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/phoenix: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5a9b0a24f57a81b98c7553517fe5f25ff63c5316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72095 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I884d6a7dedb73028f8942fdda86b0c9910fa996a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72094 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/cezanne: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino/acpi/pci_int_defs: remove TODO after checkingFelix Held
All field definitions in the IndexField object match both the info in the PPR #57243 revision 3.02 and also match the defines in soc/amd/ mendocino/include/soc/amd_pci_int_defs.h. The IndexFieldvonly defines the subset of the IRQ mapping registers that are used or likely needed in the future. This is handled in the same way for the other AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b0adfecc99945de69b4853f4423b4c10951d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72092 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel/*/include/soc/gpio.h: Add "IWYU pragma: export" commentElyes Haouas
Change-Id: If44a07503470f57037b59d03eea830703a3c604a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72100 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9a89751df71eb32b2c8d99c568341dd669b5f065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72073 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel: Remove unused <stddef.h>Elyes Haouas
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel/common/block/fast_spi/Makefile.inc: Remove spaces before tabsElyes Haouas
Change-Id: Id2b408e24f74367777b1b949623d6692f2f19e6d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72076 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-19soc/amd/stoneyridge/northbridge: use acpi_align_currentFelix Held
Use acpi_align_current to align the ACPI tables on a 16 byte boundary. This changes the alignment of the HEST, IVRS, SRAT and SLIT tables from 8 bytes to 16 bytes. The alignment of the ALIB and PSTATE SSDT tables was already 16 bytes before, so the alignment of those isn't changed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8933e3731b67012bcae0773db2f7f8de7cd31b56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72055 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19intel/meteorlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for ChromeOS platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19soc/intel/meteorlake: Increase cbmem buffer size for the debug imageKapil Porwal
Currently most of the FSP debug messages (when enabled) are truncated due to insufficient size of cbmem buffer. Increase premem cbmem console size to 0x16000 bytes and cbmem buffer size to 0x100000 bytes so that cbmem buffer can contain most of the debug logs when FSP debug messages are enabled. BUG=b:265683565 TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled but MRC debug message. Note: Still 350/2200 lines of premem messages are missing. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I120423e1dd2bc468cf9cec6da1246ac3c0a155e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72048 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19soc/intel/meteorlake: Increase cbmem buffer size to 256KBKapil Porwal
Current size of the cbmem buffer (128KB) is insufficient to contain the complete debug logs which is more than 166KB hence, cbmem console buffer has wound off to contain the maximum possible debug messages within the allocated buffer as results, we are seeing truncated debug message while looking into the cbmem console. This patch increases cbmem buffer size to 256KB so that the complete debug log can be stored in it. BUG=b:265683565 TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ibeabb61d60491b831252b7161c9d3181fbe09e73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72047 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19soc/mediatek/mt8188: Allow SSPM to access PWRAP interfaceSen Chu
Allow SSPM to access PWRAP interface. BUG=b:254566089 TEST=build pass and boot to OS. Change-Id: I4b134983dcde1cc293f4b798f91b997baf96d299 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-01-19tree: Drop Intel Ice Lake supportFelix Singer
Intel Ice Lake is unmaintained and the only user of this platform ever was the Intel CRB (Customer Reference Board). As it looks like, it was never ready for production as only engineering sample CPUIDs are supported. As announced in the 4.19 release notes, remove support for Intel Icelake code and move any maintenance on the 4.19 branch. This affects the following components and their related code: * Intel Ice Lake SoC * Intel Ice Lake CRB mainboard * Documentation Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/amd/common/block/acpi/cppc: drop outdated commentFelix Held
Since commit d5ab24cd4800 ("soc/amd/common/acpi/cppc: add nominal and minimum frequencies") the fields that got added in CPPC version 3 get populated, so remove the now outdated comment about the fields added in version 3 always being set to CPPC_UNSUPPORTED. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4c975b42fc4f67329170801b871d6bbdf9637d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-18soc/intel/alderlake: Add print that MRC training screen displayedTarun Tuli
Add a INFO print indicating that we did infact attempt to display the MRC training message to the user. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Print seen in cbmem -c Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1a20fb221aa2fa0eeaf9b7f8cf3d8a8ab0b91133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-01-18soc/amd/*/agesa_acpi: add TODO for adding CRAT tableFelix Held
The Picasso SoC code generates a CRAT ACPI table which is not done for Cezanne and newer. A significant part of the Picasso CRAT generation code can likely be moved to the common AMD SoC code and then used in all SoCs, but this still needs to be checked. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f1ebe74f0376c60396dbd80e64676d1374ed811 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72027 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/amd/glinda/agesa_acpi: use acpi_align_current to align IVRS & ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I965791fbbe499702e191dcbf1f5fbfcb5e1bab6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>