diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-24 01:00:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-31 16:40:13 +0000 |
| commit | a7b922fd74d754f07d95dd6bdf5afc5284b08b5f (patch) | |
| tree | 8e96125287cf348e17a8e1b45857b13655e56997 /src/soc | |
| parent | 9f3c6ad66f8f73422ef626b3dcde1bd975f7ee76 (diff) | |
soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL define
This register isn't used in coreboot and isn't defined in the Picasso
PPR #55570 Rev 3.18.
To enter a lower C-state, a read request to a special IO port is done.
The base address of this group of IO ports is configured in
set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave
the CPU. IIRC trying to put the MMIO mapping for entering the lower
C-states into the _CST package didn't work as expected when it was tried
on I think Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/acpi.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 3dd8418411..9ffcb7e746 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -15,7 +15,6 @@ /* sleep types defined in include/acpi/acpi.h */ #define ACPI_PM1_CNT_SCIEN BIT(0) #define MMIO_ACPI_PM_TMR_BLK 0x08 -#define MMIO_ACPI_CPU_CONTROL 0x0c #define MMIO_ACPI_GPE0_BLK 0x14 #define MMIO_ACPI_GPE0_STS 0x14 #define MMIO_ACPI_GPE0_EN 0x18 |