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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-19 23:00:22 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-20 22:22:55 +0000 |
| commit | b85fd1e84f45b003baae2f0f4851a06fbe662162 (patch) | |
| tree | 49255487432ecc402efcaaa1b494c0db6997b84e /src/soc | |
| parent | d7130cb1cff691b551b71047b3799f28881d4346 (diff) | |
soc/amd/glinda/espi_util: update file to match documentation
Checked against document #57396 revision 1.52 and removed the
DIS_ESPI_MASCTL_REG_WR define, since that bit is marked as reserved.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e8b1c65118b4e85e7934e822a7a7e329746a88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/glinda/espi_util.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/glinda/espi_util.c b/src/soc/amd/glinda/espi_util.c index bfd348f652..d26a29f650 100644 --- a/src/soc/amd/glinda/espi_util.c +++ b/src/soc/amd/glinda/espi_util.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - #include <amdblocks/spi.h> #include <soc/espi.h> #include <types.h> @@ -10,7 +8,6 @@ #define LOCK_SPIX10_BIT2 BIT(3) #define ESPI_MUX_SPI1 BIT(2) #define ROM_ADDR_WR_PROT BIT(1) -#define DIS_ESPI_MASCTL_REG_WR BIT(0) void espi_switch_to_spi1_pads(void) { |