From b85fd1e84f45b003baae2f0f4851a06fbe662162 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 19 Jan 2023 23:00:22 +0100
Subject: soc/amd/glinda/espi_util: update file to match documentation

Checked against document #57396 revision 1.52 and removed the
DIS_ESPI_MASCTL_REG_WR define, since that bit is marked as reserved.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e8b1c65118b4e85e7934e822a7a7e329746a88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
---
 src/soc/amd/glinda/espi_util.c | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'src/soc')

diff --git a/src/soc/amd/glinda/espi_util.c b/src/soc/amd/glinda/espi_util.c
index bfd348f652..d26a29f650 100644
--- a/src/soc/amd/glinda/espi_util.c
+++ b/src/soc/amd/glinda/espi_util.c
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Glinda */
-
 #include <amdblocks/spi.h>
 #include <soc/espi.h>
 #include <types.h>
@@ -10,7 +8,6 @@
 #define  LOCK_SPIX10_BIT2	BIT(3)
 #define  ESPI_MUX_SPI1		BIT(2)
 #define  ROM_ADDR_WR_PROT	BIT(1)
-#define  DIS_ESPI_MASCTL_REG_WR	BIT(0)
 
 void espi_switch_to_spi1_pads(void)
 {
-- 
cgit v1.2.3