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2021-10-02soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macroSubrata Banik
CSE_DELAY_BOOT_TO_RO -> CSE_DELAY_BOOT_TO_RO_MS Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01soc/tigerlake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-01soc/intel/alderlake: add power limits for Alder Lake-M 282 SKUSumeet Pawnikar
There are two different types of 282 SKU available with TDP of 15W and 12W for Alder Lake-M SoC. This patch adds support for these TDP values for 282 SKU as per document 643782. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2021-10-01mb/google/brya: move MILLIWATTS_TO_WATTS macro in header fileSumeet Pawnikar
Move MILLIWATTS_TO_WATTS macro in power_limit header file so all other files can use the same macro. BUG=None BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01soc/intel/common: Add PMC IPC commands for FIVR controlSumeet Pawnikar
Add PMC IPC commands information for FIVR control functionality BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I9d08bb71f7ea5da7614c68fc0ce4edf9aef59baa Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01drivers/gic: Remove unnecessary codeJulius Werner
On AArch64 platforms, GIC initialization is generally the job of Trusted Firmware and shouldn't be necessary in coreboot. Only the ancient T210 platform (which was started before we had decided on using Trusted Firmware) calls this code, and even there they have a comment wondering "do we still need this?". I'm just gonna assume (without testing because that board is ancient and I'm lazy) that they don't, and that the TF GIC initialization[1] is sufficient here. Remove this obsolete driver. [1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-30soc/intel/common/block/sgx: Fix typo in log messageAngel Pons
The value printed is the EPC (Enclave Page Cache) status, but the printk statement refers to it as `ECP status` instead. Fix the typo. Change-Id: Iba0a6013f2c537072dd7aa8266f2be3c5b0963ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58038 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-30soc/intel/alderlake: Add CPU ID 0x906a4Meera Ravindranath
TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4342c7343876eb40c2955f6f4dd99d6346852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2021-09-30soc/intel/common/../cse: Append the time units to the HECI macro namesSubrata Banik
Append `_MS` for miliseconds and `_US` for microseconds to HECI timeout macros to improve the code readability. Change-Id: Ic7f18f07ecaabb3e43356f372d15d18be083464b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMMSubrata Banik
Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across various warm reboots. This patch ensures late sending EOP msg when function disabling of CSE is no longer a requirement. BUG=b:200644229 TEST=Able to save ~30ms+ of boot time Without this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30soc/intel/alderlake: Perform `soc_finalize` at entry of BS_PAYLOAD_BOOTSubrata Banik
This patch ensures soc_finalize() is getting called at the entry of BS_PAYLOAD_BOOT boot state instead of BS_PAYLOAD_LOAD, BS_ON_EXIT. The purpose of this change is to accommodate more time to push out sending CSE EOP messages at post. BUG=b:200644229 TEST=coreboot serial log suggests soc_finalize() is getting called as part of the BS_PAYLOAD_BOOT entry. Finalizing chipset. apm_control: Finalizing SMM. APMC done. BS: BS_PAYLOAD_BOOT entry times (exec / console): 21 / 15 ms Change-Id: I8632eca057255d7f4a38b64fd17c1f3d84123051 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-09-30soc/intel/common/../cse: Perform D0I3 bit reset/set prior sending EOPSubrata Banik
Prior to coreboot sending EOP messages during post, it's important to ensure that CSE is not in Idle state. In case CSE is in Dev Idle state (which means D0I3 bit is set), reset this bit before sending EOP command. This patch ensures coreboot has provision to send CSE EOP messages even after the FSP Notify phase without any delays waiting for the device to respond or timeout. BUG=b:200644229 TEST=Able to send CSE EOP message even after FSP Notify phase. Attempting CSE EOP msg sending post FSP notify without this code change causes `timeout` issue as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post HECI: timed out reading answer! HECI: Failed to receive! HECI: receive Failed HECI: EOP send/receive fail ERROR: Failed to send EOP to CSE, 2 cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3: 0x20 VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc Saving nvdata board_reset() called! full_reset() called! Attempting CSE EOP msg sending post FSP notify with this code change is `successful` as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30soc/intel/common/../cse: Create APIs for CSE device state transitionSubrata Banik
This patch ensures APIs that are responsible for CSE device state transition between active to idle and vice-versa are available publically for other modules/boot stages to consume. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P. Change-Id: Ia480877822d343f2b4c9bf87b246812186d49ea3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-29soc/intel/cannonlake: Guard acpi_fill_ssdt assignment with HAVE_ACPI_TABLESTim Wawrzynczak
Change-Id: I3677b4e545599d00a4ba16464836834febc2d1a5 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58024 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29soc/intel: Drop unnecessary `select REG_SCRIPT`Angel Pons
These platforms no longer use reg-script. Drop unneeded select. Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/common/block/smbus: Drop reg-script usageAngel Pons
Using reg-script just to read-modify-write some registers makes no sense. Replace reg-script usage with regular register operations. Change-Id: I87d1278360a231cbe5b5f825ad9a448e59e63ea2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/skylake: Drop reg-script usageAngel Pons
Using reg-script just to read-modify-write some registers makes no sense. Replace reg-script usage with regular register operations. Change-Id: Ib3c83131c30fd02c579b910cfad6843eb28ba8f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacksMichael Niewöhner
The current names of the PMC init/enable callbacks are very confusing. Rename them. Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-29soc/intel: Rename GNVS struct member to match ASLAngel Pons
Rename the `ecps` GNVS struct member to `epcs` to match the name in ASL. Change-Id: I1f6b97309eea75e7dbb4e5e664660df05ec0845e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29soc/intel/alderlake: Add GFx Device ID 0x46c3Selma Bensaid
This CL adds support for new ADL-M graphics Device ID 0x46c3. TEST=boot to OS Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/alderlake: Add ADLP 242 power configurationsTracy Wu
Add ADLP 242 sku power related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=Build and check fsp log to confirm the settings are set properly. Change-Id: I829dd690c22d167a507b1910106da06b275cec09 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29soc/intel/alderlake: Add support for power cycle and SLP signal durationTim Wawrzynczak
The UPDs for PM power cycle duration and SLP_* signal durations are all identical to Tiger Lake, so add similar support, but use enums instead of comments to represent the durations symbolically. BUG=b:184799383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57891 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29{sb,soc}/intel: Drop unused globalnvs.asl methodsAngel Pons
These methods are never used in the code. Drop them. Change-Id: If5568b494f821d2647ada5ae845bcd015708520e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop PRMx from GNVSAngel Pons
These fields are never used in the code. Drop them. Change-Id: Icd07f2d704c19126bf6df4d740c21d5a1342061b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop LCKF from GNVSAngel Pons
This field is never used in the code. Drop it. Change-Id: I88207ec369ab83823ef2f3fc40f68a0980ce9663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29soc/mediatek/mt8195: initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. BUG=b:192429713 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-28soc/intel/baytrail: Always handle MRC as ELF fileAngel Pons
The current MRC binaries for Bay Trail are always ELF files. Always adjust the position in CBFS using the ELF header regardless of file names. Without adjusting the position, the system hangs right after calling into MRC. TEST: MRC position in CBFS does not change for bostentech/gbyt4. Change-Id: I74e1246a5fac3f3649be9842ff13c2fc70f72a20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57989 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27soc/qualcomm/sc7280: Enable QUP drivers to use lz4 compressionShelley Chen
BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27soc/intel/baytrail: Drop invalid `VGA_BIOS_FILE` defaultAngel Pons
This file does not exist in the coreboot tree. One should place this file in the `site-local` subdirectory and specify the paths by means of `site-local/Kconfig`. Change-Id: I86ac2a6176947f12194bec6b63bedd7db79820a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-27soc/amd/cezanne/early_fch: move mb_set_up_early_espi into if blockFelix Held
mb_set_up_early_espi should only be called when SOC_AMD_COMMON_BLOCK_USE_ESPI is selected. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8ad724a2a79c1995fbe9d97f11a0f69eed9435c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-27soc/amd/cezanne: Enable CCP DMAKarthikeyan Ramasubramanian
Enable CCP DMA use in PSP verstage. This helps to reduce the boot time. BUG=b:194990811 TEST=Build and boot to OS in Guybrush. Observed a 35 - 40 ms improvement in the boot time. Before CCP DMA: 508:finished loading body 898,286 (287,576) Total Time: 2,146,182 After CCP DMA: 508:finished loading body 853,627 (240,061) Total Time: 2,110,117 Cq-Depend: chrome-internal:4116566 Change-Id: I6e4f081622a2ec78763adf56548204efc1bccf39 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27soc/amd/common/psp_verstage: Introduce boot device driverKarthikeyan Ramasubramanian
PSP verstage can access the boot device either in Programmed I/O mode or DMA mode. Introduce a boot device driver and use the appropriate mode based on the SoC support. BUG=b:194990811 TEST=Build and boot to OS in Guybrush. Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC callKarthikeyan Ramasubramanian
Add support to access the boot device from PSP through Crypto Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs where it is supported and a stub on SoCs where it is not supported. This provides an improved performance while accessing the boot device and reduces the boot time by ~45 ms. BUG=b:194990811 TEST=Build and boot to OS in guybrush. Perform cold and warm reboot cycling for 250 iterations. Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27soc/amd/common/block/include/acpimmio_map: add AOAC acronym in commentFelix Held
The Always On Always Connected block is referenced as AOAC in the code, so add that acronym in the comment and change the "Connect" to "Connected". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-25soc/intel/alderlake: Use intel_microcode_find() to locate ucode.binSubrata Banik
`intel_microcode_find()` function uses cached ucode data hence it would avoid locating ucode.bin from CBFS while passing ucode.bin pointer to FSP. Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24soc/intel/alderlake: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias for tcss_usb3_port* devices. Change-Id: I65d9c83a9d0aab5a42f5a7cc6df98a154e79d16a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24soc/amd/common: factor out FSP-related parts of common KconfigFelix Held
TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2fb6c29b9f42c00f252994ae2a40b7ff668105a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/amd/common: move block/pi out of the block folderFelix Held
Since the binaryPI glue code is specific to a binary interface, but not for a hardware block, move it out of the common blocks directory. This also brings the binaryPI support in line with the FSP support which is used on the newer generations. This also drops the SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already existing SOC_AMD_PI Kconfig option instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I014e538f2772938031950475e456cc40dd05d74c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/amd/common/block: move binaryPI S3 block into PI blockFelix Held
The code in soc/amd/common/block/s3 is specific to the AMD binaryPI coreboot integration, so move the code to soc/amd/common/block/pi. This drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking process, we don't lose support for any working configuration by only having one Kconfig option for both parts. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/intel/alderlake: add MaxDramSpeed configCasper Chang
This change add MaxDramSpeed for variants usage to config dram speed. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd/common/blocks: rename gpio_banks folder to gpioFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd,intel/common/include/gpio: improve documentation of overridesFelix Held
Explicitly point out that gpio_configure_pads_with_override will ignore GPIOs that are only in the override configuration, but not in the base configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23soc/intel/xeon_sp/cpx: Use FSP repoArthur Heymans
Some headers in vendorcode are still needed but the UPD definitions can be taken from the FSP repo. Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPPArthur Heymans
coreboot expects different names for FSP UPDs so use some CPP to make it happy. Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/xeon_sp: correct wrong gpio register base offsetsMichael Niewöhner
Reference: Intel doc# 633935-005 and 547817 rev1.5. Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Lance Zhao Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-09-23soc/intel/tgl: correct wrong gpio GPI enable register base offsetMichael Niewöhner
Reference: Intel doc# 631120-001. Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/icelake: correct wrong gpio SMI register base offsetsMichael Niewöhner
Reference: Intel doc# 341081-002. Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-23soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registersMichael Niewöhner
Add NMI_EN and NMI_STS registers, so NMI interrupts can be used. References: - XEON-SP: Intel doc# 633935-005 and 547817 rev1.5 - ICL-LP: Intel doc# 341081-002 - TGL-LP: Intel doc# 631120-001 - TGL-H: Intel doc# 636174-002 - JSL: Intel doc# 634545-001 - EHL: Intel doc# 636722-002 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2021-09-23soc/intel/icl: add missing gpio group to fix the group indexesMichael Niewöhner
There is another gpio group, namely HVCMOS, between GPP_C and GPP_E. Add it, so the group index calculation for GPI/SMI/NMI results in the correct value. Reference: Linux linux/drivers/pinctrl/intel/pinctrl-icelake.c Change-Id: I7725191173ddc0d43bbe940cdf3b0dc2aa3e5f8d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/dedede: Migrate dedede to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all dedede variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for cret: util/spd_tools/bin/part_id_gen \ JSL \ lp4x \ src/mainboard/google/dedede/variants/cret/memory \ src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt For cappy, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/dedede -a -x --timeless Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/volteer: Migrate volteer to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all volteer variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for voema: util/spd_tools/bin/part_id_gen \ TGL \ lp4x \ src/mainboard/google/volteer/variants/voema/memory \ src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/volteer -a -x --timeless Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya: Migrate brya to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all brya variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for anahera: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/anahera/memory \ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/brya -a -x --timeless Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23soc/qualcomm/common: Move UART SC7180 driver to common sectionRajesh Patil
Move existing UART driver from sc7180 to common folder. This implements UART driver for QCOM SoC's BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-22soc/amd/common/block/gpio_banks: Rework GPIO pad configurationFelix Held
Before this patch, gpio_configure_pads_with_override called program_gpios once for each GPIO that needed to be configured which resulted in base_num_pads - 1 unneeded master_switch_set/ master_switch_clr sequences for the gpio_configure_pads_with_override call. Instead implement gpio_configure_pads_with_override as the more generic function and program_gpios as a special case of that which passes an empty override configuration and override pad number to gpio_configure_pads_with_override. TEST=GPIO configuration and multiplexer register values are the same for all GPIOs on google/guybrush right before jumping to the payload before and after the patch. Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-22soc/intel/alderlake: Drop unused HECI_DISABLE_USING_SMM KconfigSubrata Banik
Earlier generation platform used `HeciEnabled` chip config (set to 0) and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at the end of the post. `HeciEnabled` chip config remains enabled in all latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig selection from SoC Kconfig as CSE remains default enabled. BUG=b:200644229 TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device is listed with `lspci`. Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-09-21soc/amd/common/block/gpio_banks: add missing types.h includeFelix Held
In this file bool, uint8_t and uint32_t are used, so include types.h directly to have those types defined instead of relying to have those included indirectly via amdblocks/gpio_banks.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-21soc/qualcomm/common/spi: Configure SPI QUP driverRavi Kumar Bokka
This implements the SPI driver for the QUP core. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I7e5d3ad07f68255727958d53e6919944d3038260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56399 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21sc7280: Enable SPI driverRajesh Patil
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21soc/qualcomm/common/spi: Add support for SPI common driverRavi Kumar Bokka
This implements qup spi driver for qualcomm chipsets Rename header file names for trogdor to prevent breakage. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21sc7280: Enable I2C driverRajesh Patil
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21soc/qualcomm/common/i2c: Add support for I2C common driverRajesh Patil
copy existing I2C driver from /soc/qualcomm/sc7180 to common folder. This implements i2c driver for qualcomm chipsets BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21sc7280: Refactor QUP driverRajesh Patil
Enable common qup driver in sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I0e9049557ff63898037210e72333e1739ab62413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21soc/amd/picasso/fsp_m_params: use DEV_PTR to check if device is enabledFelix Held
The aliases are defined in the chipset devicetree, so the device pointers will be available for all boards using this SoC. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4c921575e978bb29e61f35e78ff2a1711acf06a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21soc/amd/cezanne/fsp_m_params: use DEV_PTR to check if device is enabledFelix Held
The aliases are defined in the chipset devicetree, so the device pointers will be available for all boards using this SoC. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id655e9eba9b8e9898fa01bf03876074e136cc7c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-20soc/intel/elkhartlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/icelake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I1a55df754c711b2afb8939b442019831c25cce29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/jasperlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/tigerlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/amd/cezanna/acpi/mmio.asl: enable ACPI AOAC for I2CJulian Schroeder
This enables runtime power management for the I2C controllers. BUG=b:182556027, b:183983959 TEST=enable dynamic debug in kernel and check i2c D3/D0 transitions during suspend_stress_test. Change-Id: Ia6b9ca95d751f32b7cd701494377f15091c22d2f Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56462 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20soc/amd/cezanne/acpi/mmio: uncomment AOAC_DEVICE macro for UARTsFelix Held
This enables runtime power management for the UART controllers. BUG=b:183983959 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-20soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC supportMichael Niewöhner
Currently, Intel TME (Total Memory Encryption) can be enabled regardless of SoC support. Add a Kconfig to guard the option depending on actual support. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia20152bb0fc56b0aec3019c592dd6d484829aefe Reviewed-on: https://review.coreboot.org/c/coreboot/+/57762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-17soc/intel/{ehl,jsl}: make use of Kconfig options for PRMRR sizeMichael Niewöhner
Migrate the last two platforms to using Kconfig through `get_valid_prmrr_size()` instead of hardcoded values in the devicetree. Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17soc/amd/common/block/pi/image: replace stdbool.h include with types.hFelix Held
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in this file, so include types.h instead of stdbool.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17soc/amd/picasso/Kconfig: increase FSP_M_SIZEFelix Held
When using a debug build of the FSP, the FSP-M binary is larger than the memory region we have allocated for it, so increase the size to make the binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so that it starts right after the the FSP-M memory region. TEST=coreboot builds now successfully when using a debug version of the FSP Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16soc/amd/common/block/pi: Add missing include stdbool.hRaul E Rangel
BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I298ce1ee436a5c8eb8375dc5fe55665bbf977463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16soc/amd/picasso/agesa_acpi: Add missing include 'arch/cpu.h'Raul E Rangel
Needed for cpuid_ext. BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib3a132bea06443ee4c1501b1c746400c541fd805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16mainboard/google: Update the TLMM registers for sdhcShaik Sajida Bhanu
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16soc/qualcomm: clock: Clean up clock driverTaniya Das
Updated return type as CB_SUCCESS and aligned indentation. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling methodSubrata Banik
FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC levelSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from specific mainboard (brya) to ensure all Alder Lake mainboards can make use of common TCSS block. BUG=b:187385592 TEST=Type-C pendrive/Gen-2 SSD detected as Super speed. Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16soc/intel/common: Make read_pmc_lpm_requirements more clearTim Wawrzynczak
Commit 2eb100dd12 added PMC LPM requirements to the the PEP ACPI objects, but it was not made clear that one of the pointer arguments to the mentioned function is not supposed to be NULL and Coverity complained. Make the intention clear by instead asserting that `info` cannot be NULL. Fixes: Coverity CID 1462119 Change-Id: I9e8862a100d92f4a7ed1826d3970a5110b47f4c4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-16soc/qualcomm/common/qup: Add support for QUP common driverRavi Kumar Bokka
copy existing QUP driver from /soc/qualcomm/sc7180 to common folder. This QUP common driver provide QUP configurations, GPI and SE firmware loading and initializations. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16soc/intel/common: Add panel_orientation field to common chip configTim Wawrzynczak
When the FSP driver fills out framebuffer information for the coreboot tables, it assumes the orientation is always normal. This patch provides a field for a mainboard to override the panel orientation from the default (LB_FB_ORIENTATION_NORMAL). Later patches will have the FSP driver use this value when filling out framebuffer information. BUG=b:194967458 BRANCH=dedede Change-Id: I559b3d6a076112a1c020ce5e296430d7ccba9ee4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16soc/intel/alderlake: Add igd deviceWisley Chen
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in ssdt. BUG=b:198188272 TEST=emerge-brya coreboot and check ssdt. Change-Id: Id0c50254a8a25b47368e932c99243f4f02250b82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15soc/broadwell/acpi.c: Fix unresolvable symbol '\DNVS'Matt DeVillier
Fixes: 27c51a0 ("Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"") which reverted the removal of device NVS, but was not boot tested on any Broadwell Chromebooks. It was recently discovered that the DNVS object was not being loaded, due to a weak function setting the size as zero not being defined for the platform/soc. Add the missing overloaded function and required headers. Test: build/boot google/auron variants LULU ans SAMUS, verify touchpad functional and no ACPI errors in kernel boot log. Change-Id: Icd317d117dbb068bb6da80fe56c06c0267c7b2ae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-15soc/intel/block/../tcss: Create enum for TCSS Port0/1/2/3Subrata Banik
Additionally, convert MAX_TYPE_C_PORTS from macro to enum value. Change-Id: I3c596d8a015adc0449b44710c6d517753904ecd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-14src/soc/intel/jasperlake/spd: Update SPDsTyler Wang
Due to CL:55000 modified MT53E1G32D2NP-046 WT:B settings and CL:56597 add new memory in global_lp4x_mem_parts.json.txt, update SPDs using gen_spd.go for JSL: Modify: 1.MT53E1G32D2NP-046 WT:B(lp4x-spd-5.hex --> lp4x-spd-3.hex) Add: 1.H54G46CYRBX267,lp4x-spd-1.hex 2.H54G56CYRBX247,lp4x-spd-3.hex 3.K4U6E3S4AB-MGCL,lp4x-spd-1.hex 4.K4UBE3D4AB-MGCL,lp4x-spd-3.hex BUG=b:199032134 TEST=emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I45b9275403fc4166fc56ae4c368c7a222141e150 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13soc/intel/tgl: Enable USB4 resources based on common KconfigFurquan Shaikh
Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section 7.2.5.1.5 recommends reserving the following resources for each PCIe USB4 root port: - 42 buses - 194 MiB Non-prefetchable memory - 448 MiB Prefetchable memory This change enables reserving of resources for USB4 when mainboard selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES. This is similar to the change for ADL in commit 8d11cdc6fa ("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources"). Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13soc/amd/common/block/cpu: Add missing includeRaul E Rangel
We use cpuid_eax to get the cpuid family. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-11mipi: Make panel init callback work directly on DSI transaction typesJulius Werner
Our MIPI panel initialization framework differentiates between DCS and GENERIC commands, but the exact interpretation of those terms is left to the platform drivers. In practice, the MIPI DSI transaction codes for these are standardized and platforms always need to do the same operation of combining the command length and transfer type into a correct DSI protocol code. This patch factors out the various platform-specific DSI protocol definitions into a single global one and moves the transaction type calculation into the common panel framework. The Qualcomm SC7180 implementation which previously only supported DCS commands is enhanced to (hopefully? untested for now...) also support GENERIC commands. While we're rewriting that whole section also fix some other issues about how exactly long and short commands need to be passed to that hardware which we identified in the meantime. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-10soc/intel/alderlake: Align board type as per FSP v2347_00Ronak Kanabar
This patch adds new board type BOARD_TYPE_ULT_ULX_T4 and changes BOARD_TYPE_SERVER value to 8. BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I48eb0785a209499ee0d90bd541376d9bbacf2390 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-10soc/intel/common: Delete pep.aslTim Wawrzynczak
After switching to runtime generation of the Intel Power Engine (PEPD) device, this file is no longer required. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2444433f08bfda6f79589a397a2ad2b5a3ecb0ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/skylake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch skylake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7c7cb424278946a9767ea329d18fb03d4e57dce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/common: Add Intel Power Engine support to discoverable PMCTim Wawrzynczak
In order to get rid of pep.asl, skylake also needs to support runtime generation of the Intel Power Engine, therefore add this support to devices that have a discoverable PMC as well. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/elkhartlake: Switch to runtime generation of Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/jasperlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method. soc/intel/jasperlake: Switch to acpigen PEPD Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 04:56:34 +0000