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2023-09-15soc/intel/xeon_sp: Add missing HDA devicePatrick Rudolph
Change-Id: Icc7974931a9b3f5b5c7a2ed4df2c668dac0cd684 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-09-15xeon_sp/spr: Fix duplicated definesPatrick Rudolph
Change-Id: Ib365a17652b8531e865fa16eae837c68cbedbca8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-09-15vc/intel/raptorlake: Add the FSP v4301.01 headersSean Rhodes
Move the existing FSP 4221.00 headers for Raptor Lake to a subdirectory called 4221.00_google, and select this if the vendor is Google. Add the standard FSP 4301.01 headers to a separate directory, from Intel download #686654, and select this for all other vendors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15soc/intel/jasperlake: Add ACPI names for missing USB3 portsReka Norman
BUG=b:264960828 TEST=On dibbi, ACPI tables contain entries for USB 3.4 and 3.5 Change-Id: If3266d356a2deaf42aa0943f85593416d80637ad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15intelblocks/{pmc,p2sb}: Add missing RPL-S PCH IDs for PMC and P2SBMichał Żygowski
The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based on doc 619362 rev 2.2. Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold bootDinesh Gehlot
This patch addresses the increased boot time issue that occurs when ISH store is enabled, such as in the "rex4es_ec_ish" variant. During a cold reboot, the CBMEM memory resets and loses the stored firmware versions. This causes the firmware versions to be fetched again from the CSE, which increases the boot time by about 200 ms. This patch stores a backup of the firmware version in CMOS and updates the CBMEM memory during a cold reboot. BUG=b:280722061 Test=Verified the changes on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75755 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15soc/intel/cmd/blk/cse: Implement APIs to access CMOS CSE FPT versionsDinesh Gehlot
This patch implements APIs to access the CSE FW partition versions in CMOS. The get API allows users to retrieve the current version from CMOS memory. The set API allows users to set the version in CMOS memory. BUG=b:280722061 TEST=APIs verified on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2023-09-15soc/intel/meteorlake: Remove the check for INFRSean Rhodes
Remove the check to follow the new flow that commit 9c348a7b7ea3 ("soc/intel/alderlake: Fix processor hang while plug unplug of TBT device") introduced. Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie822b8e1fd7592a31275db8455519c4cc6ac02ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/77456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-15soc/intel/meteorlake: Remove space after a castElyes Haouas
Change-Id: Ibf28fbdf791e7aa2faa41f3059150bf5ff5d21d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77735 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14qualcomm/common: Remove carriage returns from QcLib logJulius Werner
The memory log we get returned by QcLib contains Windows line endings ("\r\n"), while we prefer to have POSIX line endings in the CBMEM console (just "\n"). Filter the '\r' character out when copying that log into the CBMEM console to convert. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0652300c2393fbc0b3c9875bb0ca1aa921e59098 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77722 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14x86: Add .data section support for pre-memory stagesJeremy Compostella
x86 pre-memory stages do not support the `.data` section and as a result developers are required to include runtime initialization code instead of relying on C global variable definition. To illustrate the impact of this lack of `.data` section support, here are two limitations I personally ran into: 1. The inclusion of libgfxinit in romstage for Raptor Lake has required some changes in libgfxinit to ensure data is initialized at runtime. In addition, we had to manually map some `.data` symbols in the `_bss` region. 2. CBFS cache is currently not supported in pre-memory stages and enabling it would require to add an initialization function and find a generic spot to call it. Other platforms do not have that limitation. Hence, resolving it would help to align code and reduce compilation based restriction (cf. the use of `ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot code). We identified three cases to consider: 1. eXecute-In-Place pre-memory stages - code is in SPINOR - data is also stored in SPINOR but must be linked in Cache-As-RAM and copied there at runtime 2. `bootblock` stage is a bit different as it uses Cache-As-Ram but the memory mapping and its entry code different 3. pre-memory stages loaded in and executed from Cache-As-RAM (cf. `CONFIG_NO_XIP_EARLY_STAGES`). eXecute-In-Place pre-memory stages (#1) require the creation of a new ELF segment as the code segment Virtual Memory Address and Load Memory Address are identical but the data needs to be linked in cache-As-RAM (VMA) but to be stored right after the code (LMA). Here is the output `readelf --segments` on a `romstage.debug` ELF binary. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x02000000 0x02000000 0x21960 0x21960 R E 0x20 LOAD 0x0219e0 0xfefb1640 0x02021960 0x00018 0x00018 RW 0x4 Section to Segment mapping: Segment Sections... 00 .text 01 .data Segment 0 `VirtAddr` and `PhysAddr` are at the same address while they are totally different for the Segment 1 holding the `.data` section. Since we need the data section `VirtAddr` to be in the Cache-As-Ram and its `PhysAddr` right after the `.text` section, the use of a new segment is mandatory. `bootblock` (#2) also uses this new segment to store the data right after the code and load it to Cache-As-RAM at runtime. However, the code involved is different. Not eXecute-In-Place pre-memory stages (#3) do not really need any special work other than enabling a data section as the code and data VMA / LMA translation vector is the same. TEST=#1 and #2 verified on rex and qemu 32 and 64 bits: - The `bootblock.debug`, `romstage.debug` and `verstage.debug` all have data stored at the end of the `.text` section and code to copy the data content to the Cache-As-RAM. - The CBFS stages included in the final image has not improperly relocated any of the `.data` section symbol. - Test purposes global data symbols we added in bootblock, romstage and verstage are properly accessible at runtime #3: for "Intel Apollolake DDR3 RVP1" board, we verified that the generated romstage ELF includes a .data section similarly to a regular memory enabled stage. Change-Id: I030407fcc72776e59def476daa5b86ad0495debe Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-09-14soc/intel/xeon_sp/spr: Bump MAX_ACPI_TABLE_SIZE_KBPatrick Rudolph
When using Intel(R) Xeon(R) Platinum 8490H on IBM/SBP1 the platform runs with 480 cores. With 480 cores coreboot needs at least 440KiB for ACPI tables. Bump the config to 512 KiB to have some free space for future changes. Change-Id: I2c0bbc36f45aab921f3189459de4438a0cd5dd1f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-09-14soc/cavium: Use weak over attrbute__((weak))Elyes Haouas
Change-Id: Ia0a6ee85d92f43be6bdae36a13c5dd1a02af3568 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-14chromeos/cse_board_reset.c: Clear EC AP_IDLE flagDerek Huang
When CSE jumps between RO and RW, it triggers global reset so the AP goes down to S5 and back to S0. For Chromebox, when AP goes down to S5 EC set AP_IDLE flag. This cause an issue to warm reset the Chromebox device when it is in recovery mode and powered by USB-C adapter. This patch allows AP to direct EC to clear AP_IDLE flag before trigger reset. BUG=b:296173534 BRANCH=firmware-dedede-136-6.B TEST=Chromebox DUT which is powered by USB-C adapter boots up after warm reset in recovery mode Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77632 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
2023-09-13soc/intel/{alderlake,meteorlake}: Remove the dummy PS0 and PS3 methodsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8515407eb10e1a74f37ea5a80fa31533c38badec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77455 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/{tigerlake,meteorlake}: Check ITBT FW versionSean Rhodes
The ensures that ITBT is ready to operate. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If60404a88208c632cd60e8aaa6ba70494eefbed2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77454 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-13soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPISean Rhodes
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very similar, so can be moved to shared code. This commit aligns minor difference between then, such as comments and tabs/spaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-12soc/amd/*/Makefile: drop wrong EFS diagramsFelix Held
The EFS data structure diagrams in the Makefiles of Picasso and newer SoCs were wrong, since the BIOS directory table pointer is in a different location than shown in the diagram. Since the diagram also wasn't that easy to understand and amdfwtool does all of that handling, drop the wrong diagram from the Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f86fea29f956ff10746d35dbe967a4a89e11cca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-12soc/intel/common: Fix invalid MADT entries creationJeremy Compostella
commit f8ac3dda02f22ebf857efb5b845db97f00598f7d ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm walks all the `cpu_info' entries without discarding empty ones. Since `cpu_info' is not initialized, the data that is used is undefined and it generally results in the creation of invalid `Local x2APIC' entries in the MADT ("APIC") ACPI table. Depending on the X2APIC ID value the Linux kernel behavior changes (cf. arch/x86/kernel/acpi/boot.c::acpi_register_lapic()): 1. If (int)ID >= MAX_LOCAL_APIC (32768), the Linux kernel discards the entry with the "skipped apicid that is too big" INFO level message. 2. If (int)ID < MAX_LOCAL_APIC (32768) (including negative) this data is taken into account and it can lead to undesirable behavior such as core being disabled as (cf. "native_cpu_up: bad cpu" ERROR kernel message). TEST=Verified the MADT does not contain any invalid entries on rex. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77615 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2023-09-12cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella
It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11soc/intel: Remove space between function name and '('Elyes Haouas
Change-Id: I1dbfca33c437c680118eb3a92e60b5607c93e565 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77768 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11soc/cavium: Remove space between function name and '('Elyes Haouas
Change-Id: I25e3cf15a77cf61a60bd31519eae019742842389 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11soc/nvidia: Remove space between function name and '('Elyes Haouas
Change-Id: I5b0cdb7b8484080db6571d70ddef145bbaf2e87d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77769 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-09soc/amd/common: Remove __attribute__(())Elyes Haouas
Change-Id: I2866dcdd6900c98310b4b3736b40ebe4eaa77ea2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77719 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08soc/intel/alderlake_n: Hook up the FSP repositoryFelix Singer
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-07soc/intel/meteorlake: Update LidStatus UPD dynamicallySubrata Banik
This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:299137940 TEST=Able to build and boot google/rex to redirect the display using external HDMI monitor while LID is closed. Change-Id: I7d7b678227a6c8e32114de069af8455b8c1aa058 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-06soc/amd: correctly report I2C controller state in ACPIFelix Held
Instead of reporting all I2C controllers in the system as enabled in the corresponding ACPI device's _STA method, report the I2C devices that are disabled in the devicetree as disabled in the corresponding _STA method too. This is done by returning the contents of the STAT variable inside each device's scope in the DSDT that have a default value of 0 (device not present/disabled). For all enabled and hidden I2C devices i2c_acpi_fill_ssdt gets called which then writes 0xf (device enabled and visible) or 0xb (device enabled, but hidden) to the STAT name inside the same scope, but in the SSDT. This object in the SSDT will then override the default in the DSDT resulting in the _STA method returning the correct status of each device. The code was inspired by commit 7cf9c7451808 ("soc/amd/*: Fix UART ACPI device status"). TEST=On Mandolin all I2C controllers are disabled and with this patch none shows up in the Windows 10 device manager. When enabling an I2C controller in the devicetree for testing, it shows up again in the Windows device manager. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4cd9f447ded3a7f0b092218410c89767ec517417 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-06soc/intel/common/block/acpi: Change __attribute__((weak)) to __weakElyes Haouas
Change-Id: I9ecd81ffaa48dbed225a23900704b259569cb7c8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77527 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05soc/amd/common/vboot: Drop reporting of Silicon levelMatt DeVillier
Per the PSP team, this field in the transfer buffer isn't used anymore and always set to zero, causing devices to incorrectly report having pre-production silicon. Change-Id: Ida4bf4b9328ac83d905e4c3f822e6ceabe9be79d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77630 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-09-05amdfwtool: Add FW type FUSE_CHAIN in the config fileZheng Bao
We don't have file for the fuse chain, but we need to set the level for some cases. Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-04soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp imageArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I639fb1e911a7449d0db0d2bfcfbb6f4f225b0cef Reviewed-on: https://review.coreboot.org/c/coreboot/+/76496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-04soc/amd/mendocino: Specify and use FSP binaries for platformMatt DeVillier
Specify the default path to, and automatically include the FSP binaries needed to boot a board if USE_AMD_BLOBS is selected. Simplifies board configs, and matches use in previous patforms. TEST=build/boot google/skyrim Change-Id: Ic837d264327723c8dc18a60fb16e8d41fe38b44e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77625 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-04soc/amd/cezanne: select ADD_FSP_BINARIES if USE_AMD_BLOBSMatt DeVillier
Automatically include the FSP binaries needed to boot a board if USE_AMD_BLOBS is selected. Simplifies board configs, and matches use in soc/amd/picasso. TEST=build/boot google/guybrush Change-Id: I5b6e34085410a2aafe5d7876be5097f28f521ce8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77624 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-04{drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` configSubrata Banik
This patch renames `SAVE_MRC_AFTER_FSPS` config to `FSP_NVS_DATA_POST_SILICON_INIT` to highlight the violation in the Xeon SP FSP implementation, where the FSP Silicon Init API produces Non-Volatile Storage (NVS) instead of the FSP-Memory Init API. According to the FSP 2.x specification (section 11.3), the FSP populates the NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API mode. However, not all Intel SoC platforms that support the FSP 2.x specification adhere to this requirement. For example, the FSP binary for XEON SP platform produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on these platforms would result in an error. The `save_mrc_data.c` implementation provides the required hooks to locate the NVS post FSP-Silicon Init and store into Non-Volatile Storage. BUG=b:296704537 TEST=Able to build and boot Intel Xeon SP w/o any functional impact. Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-02soc/intel/meteorlake: Fix black screen after booting to OSSubrata Banik
This patch ensures that the VR configuration for IA, SA, and GFX is properly initialized, assigning zero values to VR causes a black screen (no display) issue. Problem Statement: Override CEP (Current Excursion Protection) value with zero aka set to disable results into black screen issue (no display). Solution: Keep CEP default enabled and don't override w/ zero value. w/o this patch: [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[0] : 0x0 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[1] : 0x0 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[2] : 0x0 w/ this patch: [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[0] : 0x1 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[1] : 0x1 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[2] : 0x1 Change-Id: I8908e8b6c995390b559212d456db6ddf984448a3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-02soc/intel/cannonlake/Kconfig: Deduplicate selectionsFelix Singer
All of the SoCs in the cannonlake directory select the following options. So move them to the common option SOC_INTEL_CANNONLAKE_BASE in order to deduplicate selections. * FSP_USES_CB_STACK * HAVE_INTEL_FSP_REPO * SOC_INTEL_CONFIGURE_DDI_A_4_LANES Change-Id: I6ce5edb2ba2c138b44601b32c3ecba2e761136f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77447 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-09-02soc/intel/cannonlake/Makefile.inc: Remove dead code of CNL SoCFelix Singer
Intel Cannon Lake was removed with commit d456f65056. Thus, remove this dead code. Change-Id: I53cd9d53b01e26f530684aa9c404f50b305c1f54 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-01soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA deviceMatt DeVillier
Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name resolves properly. TEST=tested with rest of patch train Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/intel/common/acpi: Add stub for GNA scoring acceleratorMatt DeVillier
Allows boards which enable the GNA device to provide an attachment point for the OS drivers. TEST=tested with rest of patch train Change-Id: I3398eefb80e4407594883dd39128cd7885105ac3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/intel/common: Rename crashlog macrosPratikkumar Prajapati
Remove MAILBOX word from CPU_CRASHLOG_MAILBOX_WAIT_STALL and CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT macros, because they can be used for other interface as well. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I62b04fa4b05c427db494a536ca6504db02dfeb68 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01soc/intel/meteorlake: Skip crashlog region with metadata tagPratikkumar Prajapati
Region with metadata tag contains information about BDF entry for SOC PMC SRAM and IOE SRAM. We don't need to parse this as we already define BDFs in soc/pci_devs.h for these SRAMs. Also we need to skip to region as it does not contain any crashlog data. BUG=b:262501347 TEST=Able to build google/rex. Able to trigger crashlog and decode correctly. Change-Id: Id8ed40b865cde8e89045f5c9e713398fcbff5890 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76834 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01soc/intel/common: Add metadata tag definition for crashlogPratikkumar Prajapati
When parsing descriptor table the record can have tag type = 7. This tag contains metadata depending on SOC. The platform may choose to parse it based on implementation of crashlog. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/intel/meteorlake: Validate CPU crashlog discovery table and recordsPratikkumar Prajapati
CPU crashlog discovery table and crashlog record is considered invalid if first 32bits of the table is either 0x0 (no crashlog) or 0xdeadbeef (invalid crashlog). Crashlog record is considered consumed if bit 31 is set. So in this case stop processing the subsequent records. BUG=b:289600699 TEST=Able to build and verified invalid records are skipped on google/rex. Change-Id: Ia81bd293a533217425e44473ae85b2115c85faf6 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76333 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01soc/intel/meteorlake: Adjust discovery table offset based on CPUIDPratikkumar Prajapati
CPUID CPUID_METEORLAKE_B0 onwards the discovery table offset needs to be left-shifted by 3. Reference: EDS Vol 1 (640228) BUG=b:289600699 TEST=Able to boot google/rex with crashlog enabled. Change-Id: I90647fb6190a52b42298398263978beaf931b035 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/amd/genoa: Add minimal viable code for compilationArthur Heymans
This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with amd linker script hooked up. Default to 64bit code as that will be a sensible default for this platform (high memory access required for RAS setup). Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-09-01soc/intel/cpu: Only show MP PPI option when meaningfulArthur Heymans
Older FSP releases don't have an option to do MP init via PPI, so it should not be visible. Change-Id: I74b4bd5dd72980b859763e89ead7d7f619321e66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63759 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01amd/soc/common: Use relative offset for AMDFWZheng Bao
The amdfw.rom is mostly in region COREBOOT. Calculate the relative address as the CBFS module address. That is for future 32M flash size support. TEST=binary identical test on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst This commit is part of a series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72961 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-31soc/amd/common/data_fabric: add support for extended MMIO addressesFelix Held
The Genoa SoC supports MMIO addresses larger than 48 bits. Since the MMIO base and limit registers in the data fabric only contain bits 16 to 47 of the MMIO address, the MMIO address extension register is introduced on some SoCs like Genoa. This additional register contains the upper bits of the MMIO base and limit. Since it's not available on all SoCs, introduce the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO Kconfig option to select the correct data_fabric_get_mmio_base_size implementation to be added to the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic304f5797bc5661c1d511c95e457c6dde169d329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77514 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-08-30soc/intel/meteorlake: Allow to override Fast VmodeJay Patel
This patch adds option to override Fast Vmode on Meteor Lake SoC. This requires CepEnable, EnableFastVmode, IccLimit FSPM UPDs in FSP header. If the hardware supports Fast Vmode, the FSPM will set the ICC limit value to the value passed from coreboot. With CepEnable and EnableFastVmode enabled, if IccLimit is not specified by coreboot, FSPM sets IccLimit as default value. If no values assigned to all the three CepEnable, EnableFastVmode and IccLimit, coreboot sets their values to 0 and Fast Vmode is disabled. BUG=b:286809233 TEST=In debug MTL FSP logs, the value of FSP parameters is as passed from coreboot including enable_fast_vmode, cep_enable, and fast_vmode_i_trip. Also, fast_vmode_i_trip value is passed to pcode using mailbox command without any error. This test done on google/rex board. Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: Id05dccac56c504523f9327babe0c6fbeff488ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75566 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-29soc/amd/common/data_fabric/Makefile: remove invalid commentFelix Held
The !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE comment was likely a copy-paste leftover, so remove it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45b12d1dc5af84be99d54fea0c9ccf610cf5dae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-29Revert "soc/intel/meteorlake: Generate new TME key on each warm boot"Subrata Banik
This reverts commit 5013c60a871af8fbce8c38a1c342c454e5b8452f. Reason for revert: consecutive reboots are causing kernel panic. BUG=b:297153853 TEST=Able to perform 50 cycles of consecutive reboot after reverting this CL and it boots to the OS every single time(w/o any kernel panic). Change-Id: If6c96dcc62c706a522b98a1cf1dd1920ad6473a1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77467 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26soc/amd: Move psp_transfer.h out of each SOC into commonMartin Roth
The psp_transfer.h file was the same under all SoCs, and is really tied to the file common/vboot/transfer.c, not the SOC. This patch makes an include directory under vboot to put the header into and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes the header file available to all platforms, so that new chips that don't use the psp_verstage don't have to make a psp_transfer.h file just to satisfy the compiler. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26soc/intel/common/block/oc_wdt: Add OC watchdog common blockMichał Żygowski
Add new block for handling overclocking watchdog. The watchdog is present since Skylake or maybe even earlier so it is safe to use with most of the microarchitectures utilizing intelblocks. The patch adds the common block for initializing and feeding the watchdog. Timeout is defined statically in Kconfig and should be set high enough by the board or SoC Kconfig to let the board boot with full memory training and avoid reset loops. Full training of 128GB DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs with newer memory technologies and higher RAM capacity may take more. The default has been set to 10 minutes. The patch also adds support for feeding watchdog in driverless mode, i.e. it utilizies periodic SMI to reload the timeout value and restart the watchdog timer. This is optional and selectable by Kconfig option as well. If the option is not enabled, payload and/or software must ensure to keep feeding the watchdog, otherwise the platform will reset. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26soc/intel/meteorlake: Add PMC GPIO GPE group mappingCliff Huang
Add two missing mapping for GPIO GPE routes Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25soc/intel/apollolake: Correct the logic for the legacy 8254 timerSean Rhodes
The `use_8254` should be flipped, the same as the other Intel SOCs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-25soc/amd/common/include/root_complex: add IOHC MISC SMN base addressesFelix Held
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile SoCs have, so add the additional 3 SMN base address definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24soc/intel/metorlake: Fix PMC GPIO group assignmentCliff Huang
Those values need to match with the ones defined in PMC PWRM GPIO CFG register. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24soc/intel/apollolake: Move the PMC definitions to pmc.h fileMichał Żygowski
Add a pmc.h file, which is needed for OC watchdog compilation. The PMC definitions from pm.h are moved to pmc.h. TEST=Build UP Squared and Intel GLKRVP sucessfully. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-08-24soc/mediatek/mt8188: Remove GPT timer initYidi Lin
GPT timer init is no longer needed after DRAM blob is switching to ARM arch timer. BUG=b:229800119 TEST=boot to kernel Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24soc/nvidia: Fix incorrect SPDX licenseMartin Roth
The SPDX license header for this file did not match the license text in the file. Update the SPDX header and remove the license text. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-24soc/intel/jasperlake: Use boolean type where applicableMichael Strosche
Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-23soc/intel/xeon/spr: Improve RMT configurationNaresh Solanki
Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed for proper functioning when EnforcePopulationPor is set to 1. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23soc/mediatek/mt8188: Simplify pmif init flowSen Chu
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx", MT8188G used in ChromeOS project does not support clock hardware monitor. Thus, we can simplify the initialization flow by removing the hardware default value check. BUG=b:292866009 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-22soc/qualcomm: Add missing newlines for logsYu-Ping Wu
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21soc: Remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-21soc/intel/alderlake: add GPIO definitions for RPL PCHTim Crawford
The RPL PCH uses a different ACPI Device ID than ADL PCH. Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835) Change-Id: I03f47a43ff985213ad617e834db7f974f687d877 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOTMichał Żygowski
Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSPMichał Żygowski
PchPcieClockGating and PchPciePowerGating UPDs are not yet available in RPL-S IOT FSP. It also looks like those UPDs are not generally available in all public RaptorLake FSP headers yet, so guard it against SOC_INTEL_RAPTORLAKE to avoid build errors. Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-08-21soc/intel/broadwell/pch/Kconfig: Remove dummy PCH_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I21db0474157ba20cdf3eaef086aaf29fde29d6c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76701 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21soc/intel/apollolake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: I6f2dc0fcc4392f77b8011221c0cf22af5da45172 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21meteorlake/include/soc/iomap: Remove unused HPET_BASE_ADDRESSElyes Haouas
Remove unused HPET_BASE_ADDRESS. It is already defined at <arch/hpet.h>. Change-Id: I8c517283e56915873b8e1798571642fd9d8a5764 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-20soc/samsung/exynos5250/clock: Remove space before semicolonElyes Haouas
Change-Id: Id0adfd0e25806aef836f75e83ff86a55a5d799d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-20soc/intel/bdw/pch: Remove SOC_INTEL_BROADWELL conditionalElyes Haouas
broadwell/pch/Kconfig is sourced if SOC_INTEL_BROADWELL is true. So remove 'if SOC_INTEL_BROADWELL' condition and duplicated 'INTEL_LYNXPOINT_LP' Change-Id: I9b5676fd232b47e9d5f89f7faffdfd5d2c76984e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76699 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20soc/intel/mtl: Enable IOE_PMC supportDinesh Gehlot
IOE_PMC support was not enabled on Meteor Lake platforms. This patch adds the bare minimum hooks to initialize and allocate a memory region for IOE operations. Additionally, this patch moves those IOE operations to a newly included IOE-specific file, Previously, PMC was responsible for these operations. BUG=b:287419766 TEST=build and verified on google/rex. Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20soc/intel/alderlake_n: Allow using the microcode repoFelix Singer
Allow users of Alderlake N processors to use the microcode repository and also add their related microcode blob to the list of microcodes which should be included in the coreboot rom. Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-08-18soc/intel/meteorlake: Implement `soc_is_ish_partition_enabled` overrideSubrata Banik
This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between ISH and non-ISH to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending a HECI command. BUG=b:285405031    TEST=Able to uniquely identify the ISH SKUs while booting     to google/rex_ec_ish to dump the ISH version. Change-Id: I48358ad9e2e582e8b2274cbf4655de01f8792e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77177 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18{driver, soc/intel/cmn/cse}: Refactor ISH FW Version implementationSubrata Banik
This patch uses the CSE firmware specific data to store Intel ISH firmware related information. Sending an ISH partition version information command on every boot cycle would impact the overall boot performance. This information is used by the auto-test framework to ensure the ISH firmware update is proper for in-field devices. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified ISH FW version is getting displayed across warm resets without impacting the boot time. Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-08-18soc/intel/cmn/cse: Display CSE RW FW version by default for LITE SKUSubrata Banik
This patch selects SOC_INTEL_STORE_CSE_FW_VERSION config by default for CSE LITE SKU. It helps to dump the CSE RW firmware version which further consumed by auto-test infrastructure to ensure CSE RW firmware update is successful. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. Change-Id: Iba5903c73c0a45b01e6473714e0d5f759c061825 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77175 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-18soc/intel/cmn/cse: Refactor CSE RW FW Version implementationSubrata Banik
This patch introduces a CSE firmware specific data in order to store Intel CSE and associated firmware related information which requires a sync between Pre-RAM and Post-RAM phase. This information will be used further to retrieve currently running CSE RW firmware instead of fetching the version information by sending a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational state). Current implementation attempts to simply the CSE RW FW version store and retrieval operations as below * CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store the CSE info data in absence of real physical memory and sync back into the CBMEM once available (after FSP-M exits). * CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW version into the CBMEM (as CBMEM is online). BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. w/o this patch: 10:start of ramstage         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) w/ this patch: 10:start of ramstage                         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2023-08-17soc/intel/alderlake: Set PchHdaSdiEnable for Alder LakeSean Rhodes
This UPD does exist for Alder Lake, so set it there also. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2f405804ab675aaf6dbf8b12d149566055b9eef Reviewed-on: https://review.coreboot.org/c/coreboot/+/77125 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-17soc/intel/alderlake: Add provision to show pre-boot splash screenSubrata Banik
This patch adds the ability to show a pre-boot splash screen on Meteor Lake systems using FSP-S. The patch calls into `fsp_convert_bmp_to_gop_blt()` when the `BMP_LOGO` config is enabled. This function converts a BMP file to a BLT buffer, which is then used by FSP-S to render the splash screen. Additionally, increase the heap size (malloc'able size) upto 512KB (when BMP_LOGO config is enabled) to accommodate high resolution logo file. BUG=b:284799726 TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9f4d1bc0aa991e784624ca19ba96a259ab8ddfa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17soc/intel/meteorlake: Enable LZ4 compression for logo CBFS fileSubrata Banik
This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/rex with 32MB (W25Q256JWEIM) SPI-Flash. w/o this patch: sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A FMAP REGION: FW_MAIN_A Name Offset Type Size Comp ... ... logo.bmp 0x167480 raw 6172 LZMA (97078 decompressed) ... 15:starting LZMA decompress (ignore for x86)  849,090 (1,022) 16:finished LZMA decompress (ignore for x86)  851,207 (2,116) w/ this patch: sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A FMAP REGION: FW_MAIN_A Name Offset Type Size Comp ... ... logo.bmp 0x167480 raw 8568 LZ4 (97078 decompressed) ... 17:starting LZ4 decompress (ignore for x86)   849,419 (1,279) 18:finished LZ4 decompress (ignore for x86)   849,559 (140) Change-Id: I856c39146a5ec0faf44c1cd37fa7c0d7296bf673 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17soc/intel: Update all references to ESE as ISSEUsha P
Intel has rebranded ESE as ISSE (Intel Silicon Security Engine),so all references to ESE is updated to ISSE in the current coreboot code. BUG=None TEST=Build all the variants based on Intel Meteor Lake SoC Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I1f8785704706d56a35e94a0f3386bc551cd1f263 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77241 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-16soc/intel/alderlake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: If26184058536590b70bbb03209913118307ff6c5 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76830 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki
Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16vendorcode/fsp: Rename GLK to Gemini Lake to match other SOCsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic559b78e6444acec36d437fe3c139b692a3f4d0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77126 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-08-15nb,soc/amd/*/northbridge: use mmio_range to add IOAPIC2 resourcesFelix Held
Instead of open coding this, use the mmio_range helper function to tell the resource allocator about the northbridge's IOAPIC's MMIO. This change sets the IORESOURCE_RESERVE and IORESOURCE_STORED bits in the resource flags that weren't set before, but mmio_range is already used elsewhere for similar purposes. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66a73cdb22fd551e4359914ba5513313dcc3193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-15soc/amd/common/lpc: use fixed_io_range_flags instead of open codingFelix Held
Instead of open coding the same functionality, use fixed_io_range_flags to tell the resource allocator about the FCH subtractively decoding the first 0x1000 bytes of I/O space. Also update the comment to match the code. TEST=On Mandolin the flags of this resource stay the same (0xc0040100). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia30a87a4e37c98248568476b74af2730a3c0e88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77170 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-15soc/amd/common/data_fabric/domain: use get_iohc_fabric_idFelix Held
Use get_iohc_fabric_id() to translate the coreboot domain's number into the destination data fabric ID of the PCI root. This allows using the coreboot domain 0 as primary domain of the SoC in all cases, so it's still possible to use config_of_soc(). This allows dropping the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT Kconfig option and do the check if the destination fabric ID in the PCI bus number, MMIO, and IO decode registers is the correct one for the domain without the need to use a non-zero number for the primary PCI root domain. TEST=Mandolin still boots and the PCI bus, IO and MMIO resources still get reported correctly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I880ee0bf5c185cfe4af7de0d39581eb951ee603a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77169 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-15soc/amd/*/root_complex: introduce get_iohc_fabric_idFelix Held
Implement get_iohc_fabric_id for each SoC that translates the coreboot domain number to the fabric ID of the corresponding PCI root. This allows the primary domain to have the number 0 even though the destination data fabric ID will be non-zero. Keeping the primary domain number 0 allows to use config_of_soc() which can be resolved at link time and not need to dynamically find the SoC device to get the config. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6538a777619eed974b449fc70d3fe3084ba447dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/77168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-15soc/nvidia/tegra210/mipi-phy: Remove space before semicolonElyes Haouas
Change-Id: I107e2952bcca864a1cacf240cca301011df44719 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-15soc/samsung/exynos5420/clock: Remove space before semicolonElyes Haouas
Change-Id: Iab1ac1609f117a1a80bc025bcbe4659189bdb676 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-14soc/mediatek/mt8173/mt6391: Remove space before semicolonElyes Haouas
Change-Id: I88668d8c69da68cc28bae287f573f650f28da32e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-13soc/amd/common/data_fabric: handle multiple PCI root domainsFelix Held
In the case of SoCs hat have more than one PCI root, we need to check to which PCI root the PCI bus number, IO and MMIO regions configured in the data fabric registers get routed to and only tell the resource allocator about the resources that get routed to the current PCI root domain. For this the numbers of the domains need to match the PCI root's destination data fabric ID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib6a6412f733d321044678d2b064c33418a53861c Reviewed-on: https://review.coreboot.org/c/coreboot/+/77113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-13soc/intel/cse: Add config to enable PSR data backup for CSE Lite SKUKrishna Prasad Bhat
Intel Platform Service Record (PSR) provides on-platform persistent and tamper resistant ledgers and counters. Key events captured within the Intel PSR Event Ledger, e.g., Chassis Intrusion Detection, can be observed over the life cycle of the platform to help assess confidence. Counters for platform S0 operational use and power state transitions can be assessed to aid in the determination of general wear or correlations of other platform events when determining platform decommission plans (repurpose, resell, recycle). PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. Add a config to support this PSR data backup flow. BRANCH=None BUG=b:273207144 Change-Id: Iad1ce2906177081c103ef4d4bcef78fa2c95026f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-08-12soc/intel/xeon_sp/*/Kconfig: Refactor out and remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific selections to {cpx,skx,spr} and remove dummy SOC_SPECIFIC_OPTIONS Change-Id: I71e41deb0478bf4d04395c88fc7b68df1ea83ac0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-12soc/amd/common/data_fabric: read PCI bus decoding from DF registersFelix Held
The data fabric also controls which PCI bus numbers get decoded to the PCI root. In order for the resource allocator to know how the hardware is configured, read the corresponding data fabric registers to get the information that then gets passed to the allocator. Picasso, Cezanne, Mendocino and Rembrandt only support one PCI segment with 256 buses while the Phoenix and Glinda data fabric hardware has support for more PCI segments. Due to this change, the register layout is different and incompatible between those two, so introduce the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT Kconfig option for a SoC to specify which implementation is needed. At the moment, coreboot doesn't have support for multiple PCI segments and the code doesn't support PCI segments other than segment 0. On Picasso the PCI bus number limit read back from the data fabric register is 255 even though CONFIG_ECAM_MMCONF_BUS_NUMBER is set to 64, so also make sure that the bus and limit returned by data_fabric_get_pci_bus_numbers is within the expected limits. TEST=PCI bus allocation still works on Mandolin (Picasso) and Birman (Phoenix). Picasso has 64 PCI buses. coreboot puts this info into the resource producer in _SB\PCI0\_CRS which the Linux kernel reads: * coreboot: PCI0 _CRS: adding busses [0-3f] * Linux: pci_bus 0000:00: root bus resource [bus 00-3f] This matches the information in the ACPI MCFG table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide5fa9b3e95cfd59232048910cc8feacb6dbdb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77080 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/amd/glinda/Kconfig: fix commentFelix Held
The SOC_AMD_REMBRANDT_BASE comment at the end of Glinda's Kconfig is probably a leftover from the Mendocino/Rembrandt SoC this file was copied from. Change it to SOC_AMD_GLINDA to match the corresponding 'if SOC_AMD_GLINDA' in the file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85132e4840c1bc713cfc2f3493f800d66edd10ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/77121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-08-11soc/intel/braswell: Adjust status of IOSF ACPI objectMatt DeVillier
Neither Windows nor mainline Linux make use of IOSF on the Braswell platform, so adjust the ACPI status return value based on CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows device manager. TEST=build/boot Win11, Linux 6.2 on google/edgar Change-Id: Ic51624ffd816d48c007c13d510601cf8cbf1edc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>