diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2023-08-25 13:46:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-13 13:13:21 +0000 |
| commit | 53048c2a541be7b483d4b916a04c32296e328f41 (patch) | |
| tree | 5f49f210f1045ca51fbf4411426196277661c656 /src/soc | |
| parent | 90e1346d510e7a8b7bd541144c545b7b9bc91b5d (diff) | |
soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPI
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very
similar, so can be moved to shared code.
This commit aligns minor difference between then, such as comments and
tabs/spaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_dma.asl | 14 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss.asl | 6 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss_dma.asl | 18 |
3 files changed, 24 insertions, 14 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index ca47bd0ec9..2586ecbbc7 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -35,6 +35,10 @@ Method (_S0W, 0x0) #endif // D3COLD_SUPPORT } +/* + * Get power resources that are dependent on this device for Operating System Power Management + * to put the device in the D0 device state + */ Method (_PR0) { #if CONFIG(D3COLD_SUPPORT) @@ -49,7 +53,7 @@ Method (_PR0) } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // D3COLD_SUPPORT } Method (_PR3) @@ -74,8 +78,8 @@ Method (_PR3) */ Method (D3CX, 0, Serialized) { - DD3E = 0 /* Disable DMA RTD3 */ - STAT = 0x1 + DD3E = 0x00 /* Disable DMA RTD3 */ + STAT = 0x01 } /* @@ -83,8 +87,8 @@ Method (D3CX, 0, Serialized) */ Method (D3CE, 0, Serialized) { - DD3E = 1 /* Enable DMA RTD3 */ - STAT = 0 + DD3E = 0x01 /* Enable DMA RTD3 */ + STAT = 0x00 } /* diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index 7b83b5ff7e..e9ef6c390a 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -392,7 +392,10 @@ Scope (\_SB.PCI0) } - /* From RegBar Base, IOM_TypeC_SW_configuration_1 is at offset 0x40 */ + /* + * From RegBar Base, IOM_TypeC_SW_configuration_1 is in offset 0xC10040, where + * 0x40 is the register offset. + */ OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100) Field (IOMR, DWordAcc, NoLock, Preserve) { @@ -604,7 +607,6 @@ Scope (\_SB.PCI0) Return } - /* Request IOM for D3 cold entry sequence. */ /* * FIXME: Remove this workaround after resolving b/244082753 diff --git a/src/soc/intel/meteorlake/acpi/tcss_dma.asl b/src/soc/intel/meteorlake/acpi/tcss_dma.asl index 94678fcd00..90824698bb 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_dma.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_dma.asl @@ -28,12 +28,16 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ Method (_S0W, 0x0) { #if CONFIG(D3COLD_SUPPORT) - Return (0x4) + Return (0x04) #else - Return (0x3) + Return (0x03) #endif // D3COLD_SUPPORT } +/* + * Get power resources that are dependent on this device for Operating System Power Management + * to put the device in the D0 device state + */ Method (_PR0) { #if CONFIG(D3COLD_SUPPORT) @@ -48,7 +52,7 @@ Method (_PR0) } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // D3COLD_SUPPORT } Method (_PR3) @@ -73,8 +77,8 @@ Method (_PR3) */ Method (D3CX, 0, Serialized) { - DD3E = 0 /* Disable DMA RTD3 */ - STAT = 0x1 + DD3E = 0x00 /* Disable DMA RTD3 */ + STAT = 0x01 } /* @@ -82,8 +86,8 @@ Method (D3CX, 0, Serialized) */ Method (D3CE, 0, Serialized) { - DD3E = 1 /* Enable DMA RTD3 */ - STAT = 0 + DD3E = 0x01 /* Enable DMA RTD3 */ + STAT = 0x00 } /* |