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2021-09-20soc/intel/icelake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I1a55df754c711b2afb8939b442019831c25cce29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/jasperlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/tigerlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/amd/cezanna/acpi/mmio.asl: enable ACPI AOAC for I2CJulian Schroeder
This enables runtime power management for the I2C controllers. BUG=b:182556027, b:183983959 TEST=enable dynamic debug in kernel and check i2c D3/D0 transitions during suspend_stress_test. Change-Id: Ia6b9ca95d751f32b7cd701494377f15091c22d2f Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56462 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20soc/amd/cezanne/acpi/mmio: uncomment AOAC_DEVICE macro for UARTsFelix Held
This enables runtime power management for the UART controllers. BUG=b:183983959 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-20soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC supportMichael Niewöhner
Currently, Intel TME (Total Memory Encryption) can be enabled regardless of SoC support. Add a Kconfig to guard the option depending on actual support. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia20152bb0fc56b0aec3019c592dd6d484829aefe Reviewed-on: https://review.coreboot.org/c/coreboot/+/57762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-17soc/intel/{ehl,jsl}: make use of Kconfig options for PRMRR sizeMichael Niewöhner
Migrate the last two platforms to using Kconfig through `get_valid_prmrr_size()` instead of hardcoded values in the devicetree. Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17soc/amd/common/block/pi/image: replace stdbool.h include with types.hFelix Held
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in this file, so include types.h instead of stdbool.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17soc/amd/picasso/Kconfig: increase FSP_M_SIZEFelix Held
When using a debug build of the FSP, the FSP-M binary is larger than the memory region we have allocated for it, so increase the size to make the binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so that it starts right after the the FSP-M memory region. TEST=coreboot builds now successfully when using a debug version of the FSP Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16soc/amd/common/block/pi: Add missing include stdbool.hRaul E Rangel
BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I298ce1ee436a5c8eb8375dc5fe55665bbf977463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16soc/amd/picasso/agesa_acpi: Add missing include 'arch/cpu.h'Raul E Rangel
Needed for cpuid_ext. BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib3a132bea06443ee4c1501b1c746400c541fd805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16mainboard/google: Update the TLMM registers for sdhcShaik Sajida Bhanu
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16soc/qualcomm: clock: Clean up clock driverTaniya Das
Updated return type as CB_SUCCESS and aligned indentation. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling methodSubrata Banik
FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC levelSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from specific mainboard (brya) to ensure all Alder Lake mainboards can make use of common TCSS block. BUG=b:187385592 TEST=Type-C pendrive/Gen-2 SSD detected as Super speed. Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16soc/intel/common: Make read_pmc_lpm_requirements more clearTim Wawrzynczak
Commit 2eb100dd12 added PMC LPM requirements to the the PEP ACPI objects, but it was not made clear that one of the pointer arguments to the mentioned function is not supposed to be NULL and Coverity complained. Make the intention clear by instead asserting that `info` cannot be NULL. Fixes: Coverity CID 1462119 Change-Id: I9e8862a100d92f4a7ed1826d3970a5110b47f4c4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-16soc/qualcomm/common/qup: Add support for QUP common driverRavi Kumar Bokka
copy existing QUP driver from /soc/qualcomm/sc7180 to common folder. This QUP common driver provide QUP configurations, GPI and SE firmware loading and initializations. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16soc/intel/common: Add panel_orientation field to common chip configTim Wawrzynczak
When the FSP driver fills out framebuffer information for the coreboot tables, it assumes the orientation is always normal. This patch provides a field for a mainboard to override the panel orientation from the default (LB_FB_ORIENTATION_NORMAL). Later patches will have the FSP driver use this value when filling out framebuffer information. BUG=b:194967458 BRANCH=dedede Change-Id: I559b3d6a076112a1c020ce5e296430d7ccba9ee4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16soc/intel/alderlake: Add igd deviceWisley Chen
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in ssdt. BUG=b:198188272 TEST=emerge-brya coreboot and check ssdt. Change-Id: Id0c50254a8a25b47368e932c99243f4f02250b82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15soc/broadwell/acpi.c: Fix unresolvable symbol '\DNVS'Matt DeVillier
Fixes: 27c51a0 ("Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"") which reverted the removal of device NVS, but was not boot tested on any Broadwell Chromebooks. It was recently discovered that the DNVS object was not being loaded, due to a weak function setting the size as zero not being defined for the platform/soc. Add the missing overloaded function and required headers. Test: build/boot google/auron variants LULU ans SAMUS, verify touchpad functional and no ACPI errors in kernel boot log. Change-Id: Icd317d117dbb068bb6da80fe56c06c0267c7b2ae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-15soc/intel/block/../tcss: Create enum for TCSS Port0/1/2/3Subrata Banik
Additionally, convert MAX_TYPE_C_PORTS from macro to enum value. Change-Id: I3c596d8a015adc0449b44710c6d517753904ecd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-14src/soc/intel/jasperlake/spd: Update SPDsTyler Wang
Due to CL:55000 modified MT53E1G32D2NP-046 WT:B settings and CL:56597 add new memory in global_lp4x_mem_parts.json.txt, update SPDs using gen_spd.go for JSL: Modify: 1.MT53E1G32D2NP-046 WT:B(lp4x-spd-5.hex --> lp4x-spd-3.hex) Add: 1.H54G46CYRBX267,lp4x-spd-1.hex 2.H54G56CYRBX247,lp4x-spd-3.hex 3.K4U6E3S4AB-MGCL,lp4x-spd-1.hex 4.K4UBE3D4AB-MGCL,lp4x-spd-3.hex BUG=b:199032134 TEST=emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I45b9275403fc4166fc56ae4c368c7a222141e150 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13soc/intel/tgl: Enable USB4 resources based on common KconfigFurquan Shaikh
Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section 7.2.5.1.5 recommends reserving the following resources for each PCIe USB4 root port: - 42 buses - 194 MiB Non-prefetchable memory - 448 MiB Prefetchable memory This change enables reserving of resources for USB4 when mainboard selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES. This is similar to the change for ADL in commit 8d11cdc6fa ("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources"). Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13soc/amd/common/block/cpu: Add missing includeRaul E Rangel
We use cpuid_eax to get the cpuid family. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-11mipi: Make panel init callback work directly on DSI transaction typesJulius Werner
Our MIPI panel initialization framework differentiates between DCS and GENERIC commands, but the exact interpretation of those terms is left to the platform drivers. In practice, the MIPI DSI transaction codes for these are standardized and platforms always need to do the same operation of combining the command length and transfer type into a correct DSI protocol code. This patch factors out the various platform-specific DSI protocol definitions into a single global one and moves the transaction type calculation into the common panel framework. The Qualcomm SC7180 implementation which previously only supported DCS commands is enhanced to (hopefully? untested for now...) also support GENERIC commands. While we're rewriting that whole section also fix some other issues about how exactly long and short commands need to be passed to that hardware which we identified in the meantime. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-10soc/intel/alderlake: Align board type as per FSP v2347_00Ronak Kanabar
This patch adds new board type BOARD_TYPE_ULT_ULX_T4 and changes BOARD_TYPE_SERVER value to 8. BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I48eb0785a209499ee0d90bd541376d9bbacf2390 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-10soc/intel/common: Delete pep.aslTim Wawrzynczak
After switching to runtime generation of the Intel Power Engine (PEPD) device, this file is no longer required. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2444433f08bfda6f79589a397a2ad2b5a3ecb0ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/skylake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch skylake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7c7cb424278946a9767ea329d18fb03d4e57dce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/common: Add Intel Power Engine support to discoverable PMCTim Wawrzynczak
In order to get rid of pep.asl, skylake also needs to support runtime generation of the Intel Power Engine, therefore add this support to devices that have a discoverable PMC as well. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/elkhartlake: Switch to runtime generation of Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/jasperlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method. soc/intel/jasperlake: Switch to acpigen PEPD Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-10soc/intel/cannonlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch cannonlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-10soc/intel/cannonlake: Switch PMC to use device callbacksTim Wawrzynczak
Now that the PMC device is marked as hidden in devicetrees, the device callbacks can be used instead of BOOT_STATE_INIT_ENTRY callbacks. Note that this moves PMC initialization from BS_DEV_INIT_CHIPS to BS_DEV_ENUMERATE, which aligns with other Intel SoCs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If292728ad975ba803fed6abea879f6f634470a11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/tigerlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch tigerlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/tigerlake: Move LPM functions to new fileTim Wawrzynczak
The LPM enable mask is useful to have in more than one place, therefore more the get_disable_mask() function and its helpers to lpm.c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibe83dc106f5f37baf9d5c64f68c47d85ea4e6dd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch alderlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSMTim Wawrzynczak
This patch adds support for the S0ix UUID in the Intel Power Engine _DSM method. This allows the ACPI tables to expose device/IP power states requirements for different system low power states BUG=b:185437326 TEST=Along with following patch on brya0 after resume from s0ix, cat /sys/kernel/debug/pmc_core/substate_requirements Element | S0i2.0 | S0i3.0 | Status | USB2PLL_OFF_STS | Required | Required | Yes | PCIe/USB3.1_Gen2PLL_OFF_STS | Required | Required | Yes | PCIe_Gen3PLL_OFF_STS | Required | Required | Yes | OPIOPLL_OFF_STS | Required | Required | Yes | OCPLL_OFF_STS | Required | Required | Yes | MainPLL_OFF_STS | | Required | | MIPIPLL_OFF_STS | Required | Required | Yes | Fast_XTAL_Osc_OFF_STS | | Required | | AC_Ring_Osc_OFF_STS | Required | Required | Yes | SATAPLL_OFF_STS | Required | Required | Yes | XTAL_USB2PLL_OFF_STS | | Required | Yes | CSME_PG_STS | Required | Required | Yes | SATA_PG_STS | Required | Required | Yes | xHCI_PG_STS | Required | Required | Yes | UFSX2_PG_STS | Required | Required | Yes | OTG_PG_STS | Required | Required | Yes | SPA_PG_STS | Required | Required | Yes | SPB_PG_STS | Required | Required | Yes | SPC_PG_STS | Required | Required | Yes | THC0_PG_STS | Required | Required | Yes | THC1_PG_STS | Required | Required | Yes | GBETSN_PG_STS | Required | Required | Yes | GBE_PG_STS | Required | Required | Yes | LPSS_PG_STS | Required | Required | Yes | ADSP_D3_STS | | Required | Yes | xHCI0_D3_STS | Required | Required | Yes | xDCI1_D3_STS | Required | Required | Yes | IS_D3_STS | Required | Required | Yes | GBE_TSN_D3_STS | Required | Required | Yes | CPU_C10_REQ_STS_0 | Required | Required | Yes | CNVI_REQ_STS_6 | | Required | Yes | ISH_REQ_STS_7 | | Required | Yes | MPHY_Core_DL_REQ_STS_16 | Required | Required | Yes | Break-even_En_REQ_STS_17 | Required | Required | Yes | Auto-demo_En_REQ_STS_18 | Required | Required | Yes | Int_Timer_SS_Wake0_Pol_STS | Required | Required | | Int_Timer_SS_Wake1_Pol_STS | Required | Required | | Int_Timer_SS_Wake2_Pol_STS | Required | Required | | Int_Timer_SS_Wake3_Pol_STS | Required | Required | | Int_Timer_SS_Wake4_Pol_STS | Required | Required | | Int_Timer_SS_Wake5_Pol_STS | Required | Required | | Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56005 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10soc/intel/common/block/acpi: Move pep.asl to acpigenTim Wawrzynczak
There is a use-case for generating the AML bytecode at runtime for the Intel Power Engine device, which comes in a followup patch. BUG=b:185437326 TEST=verified on google/brya and google/dratini by dumping SSDT and verifying the PEPD device matches what was previously in the DSDT: Scope (\_SB.PCI0) { Device (PEPD) { Name (_HID, "INT33A1") Name (_CID, EisaId ("PNP0D80") Method (_DSM, 4, Serialized) { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x63 }) } If ((Local1 == One)) { Return (Package (0x01) { Package (0x03) { \NULL, Zero, Package (0x02) { Zero, Package (0x02) { 0xFF, Zero } } } }) } If ((Local1 == 0x02)){} If ((Local1 == 0x03)){} If ((Local1 == 0x04)){} If ((Local1 == 0x05)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (One) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (One) } If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () } } If ((Local1 == 0x06)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (Zero) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (Zero) } If (CondRefOf (\_SB.PCI0.RGPM)) { \_SB.PCI0.RGPM () } } Return (Buffer (One) { 0x00 }) } Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Set LpmStateEnableMask UPDTim Wawrzynczak
Use the get_supported_lpm_states() function to set the respective FSP UPD. TEST=with patchtrain on brya0, /sys/kernel/debug/pmc_core/substate_requirements shows only the substates that are applicable to the design (S0i2.0, S0i3.0). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Add get_adl_cpu_type functionTim Wawrzynczak
This function searches the known MCH device IDs for Alder Lake and returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or unknown. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-09Revert "soc/amd/common: Skip psp_verstage on S0i3 resume"Karthikeyan Ramasubramanian
This reverts commit b90e6fdd25f7fcc9db6be50a0b117a7509c6fdb1. Latest releases of PSP does not load PSP verstage on S0i3 resume. Hence no need to skip PSP verstage on S0i3 resume. BUG=b:196400450 TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle and then a reboot and ensure that the system boots to OS. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitionsFelix Held
Add the pin definitions for the remote GPIOs and the GPIO pin mux values for the GPIO mode of those pins. For now, accessing the remote GPIOs is only supported from the native coreboot code running on the x86 cores and not from verstage on PSP or ACPI. BUG=b:194524995 TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and then toggling that GPIO in an infinite loop in the mainboard's bootblock code results in GPIO 262 toggling as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09soc/amd/common/block/acpi/gpio: add warning for remote GPIO usageFelix Held
Right now the ACPI code doesn't support accessing the remote GPIO block yet, so don't generate invalid remote GPIO access functions and warn about those being unsupported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-09-09soc/amd/common/block/gpio_banks: add remote GPIO supportFelix Held
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't located right after the 4th GPIO bank, but instead at a different location inside the APCIMMIO region. A difference to the first 4 GPIO banks is that the corresponding GPIO MUX registers aren't in a separate bank, but at the end of the remote GPIO region. So this remote GPIO region only supports 48 GPIOs with a 32 bit configuration register each and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the remote GPIO region. For now using the remote GPIOs from verstage on PSP isn't supported. To support this, it would need to map acpimmio_remote_gpio and update the pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a few others. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBMAULIK V VAGHELA
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time. Increasing it over 4 KiB doesn't result in significant improvement, thus keeping the value at 4 KiB as of now. Timing data: Note that before Data is with 1 KiB block size. |------------------------------------------------------| | Stage | Block Size | Before | After | |finished loading body| 4 KiB | 205,187 | 189,947 | |finished loading body| 8 KiB | 205,187 | 188,708 | |finished loading body| 16 KiB | 205,187 | 188,085 | |finished loading body| 32 KiB | 205,187 | 187,793 | |------------------------------------------------------| BUG=b:188577893 BRANCH=None TEST=Boot time for Brya improves by 20 - 25 msec Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09soc/intel/alderlake: Enable Irms UPD for ADLRonak Kanabar
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit is set to non zero. It results VR TDC Input current to be treated as it is root mean square. This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit for TdcEnable UPD. BRANCH=None TEST=Build and boot brya with debug FSP and verify Irms UPD value from logs Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-09-09mb/ocp: Remove superfluous FSP header CPP inclusionArthur Heymans
This is already done in drivers/intel/fsp2_0/Makefile.inc. Change-Id: Idfd15d0a9d2cb15e613881f80bb25c18bd7454bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09intel/xeon_sp/cpx: Hook up public microcode releaseArthur Heymans
Change-Id: I7e575cb17e2004bd931f4fa1d05f17c4cdca29ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09soc/intel/broadwell: Set FADT `duty_offset` to 0Angel Pons
From ACPI specification, version 6.2 Errata A: A `duty_width` value of 0 indicates that processor duty cycle is not supported and the processor continuously runs at its base frequency. Because Broadwell sets `duty_width` to 0, processor duty cycle is not supported, and the value of `duty_offset` is ignored. For consistency with Lynx Point, set `duty_offset` to 0. Change-Id: I68cb85ec32a6cceda0cea29d76df6c6219b78a40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-09soc/amd/common/block/acpimmio: add remote GPIO bank ACPIMMIO regionFelix Held
Currently coreboot for the AMD SOCs only supports accessing the up to 4 main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne have another GPIO bank in the ACPIMMIO region that can contain up to 48 GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO MUX registers. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-09soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macroFelix Held
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins array that is used for the sb_reset_i2c_peripherals call to bring the I2C buses into a defined state. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08soc/intel/common: Avoid NULL pointer deferenceJohn Zhao
Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458068, 1458070, 1458971, 1458073, 1458075, 1458076 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ib88fa5f44dd33ad1ad2e763d79438b5c5b78acb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-08soc/amd/cezanne/fsp_m_params: set usb_phy version and length.Julian Schroeder
Setting the usb_phy version and length in the soc code instead of devicetree. That way the devicetree code does not have to reapeat it for different AMD Cezanne based systems. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/{apl,glk}: Allow to select the primary graphics deviceMaxim Polyakov
Allow to select the primary graphics device between the IGD and the external PCIe GPU depending on the ONBOARD_VGA_IS_PRIMARY config. The option sets the priority only. This means that if a high priority is set for an external PCI device and it is not connected/not enabled, then the device with a lower priority will be used, in our case it is IGD. TEST = Set PRIMARY_PCI and boot Linux on the Kontron mAL10 [1] with the miniPCIe video adapter on the Silicon Motion SM750 controller. As a result, the display connected to an external GPU device shows the Tianocore logo + setup menu and the desktop. [1] https://review.coreboot.org/c/coreboot/+/39133 Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-09-08mb/google/cherry: Fix incorrect timestamps in eventlogChen-Tsung Hsieh
The eventlog requires RTC to provide correct timestamps, so we have to turn on the config and add the common drivers. BUG=b:199003609 TEST=check timestamp in 'mosys eventlog list' BRANCH=none Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-09-08soc/mediatek: preserve WDT reset reason for debuggingFengquan Chen
1. Disable external output reset signal in first WDT reset to preserve WDT original reset reason for WDT issue in kernel stage. 2. After preserved WDT reset reason, do fully reset again by sending external output reset signal. BUG=b:194025005 TEST=boot to kernel ok and function test pass Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com> Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-09-08soc/amd/common/block/gpio_banks: add comment about acpimmio_* symbolsFelix Held
Suggested-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0016a6c7d6581cb261cab6178268c1a86b89c839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56831 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: inline iomux_read8 and iomux_write8Felix Held
Since both functions are only called from one function each, inline them into those functions. Also get_gpio_mux just returned the return value of iomux_read8, so there were two functions with identical functionality which shouldn't be the case. Suggested-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5662d0226edb25a9954fa47b42e208729a79e5a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56830 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: factor out gpio_mux_ptrFelix Held
This aligns the GPIO MUX access more with the GPIO control register access and will facilitate adding support for the remote GPIO bank. Also change the GPIO number argument type to gpio_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO accessFelix Held
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers while only allowing GPIO accesses through the GPIO API on the SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/block/gpio_banks: move GPIO MUX access functionsFelix Held
Move those two functions near the top of the file to have all functions that do the hardware accesses in one place. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If787e6e1d124a932beafd73e5ce7d0ce4869e800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08soc/amd/common/block/gpio_banks/gpio: use unsigned types where neededFelix Held
Use unsigned integers for variables that aren't supposed to become negative. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ee037221b9818b0474fe0376323e522c1b3b516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-09-08soc/amd/common/block/gpio_banks/gpio: use gpio_t for GPIO numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7cf9cbd2a287dcfe3a47a8a6b164c2b3d8ae95d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common: move GPIO ACPIMMIO access functions to gpio_banks blockFelix Held
Since the raw GPIO MMIO register access is now only used inside the gpio_banks block, the gpio_read32 and gpio_write32 functions can be moved to that block to reduce the visibility and enforce the usage of the functions provided by the gpio_banks block. The iomux_read8 and iomux_write8 functions can't be easily moved to the gpio_banks block, since it's also used in the pre-SOC AMD chipsets that use the ACPIMMIO access functions directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia0d6dea72c6bebbbe6ce545bedfc74f91e0042c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2021-09-08soc/amd/common/block/gpio_banks: factor out get_gpio_muxFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d7a8c5a7188fd558a577352f8b246e61f3edd63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/block/i2c: move raw GPIO access functions to gpio_banksFelix Held
The I2C code should use some GPIO API to access the GPIO registers instead of accessing the GPIO MMIO regions itself. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84dff381ad86e0c7f879f0f079186aec9cafc604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/block/i2c: use common GPIO API in drive_sclFelix Held
No need to do raw GPIO MMIO accesses when basically the same functionality can be achieved by using existing APIs. Using the existing GPIO API instead of raw GPIO MMIO register accesses allows containing all direct GPIO MMIO accesses inside the common AMD GPIO code which will be done in subsequent patches. Since the value parameter of gpio_set is int, change the type of the val parameter of drive_scl to int as well even though I'm not sure why a signed integer was used for this in the common GPIO API. Since program_gpios already configures the SCL GPIOs as outputs, gpio_set can be used in drive_scl which only sets the output value, but doesn't configure the direction. TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook looks similar to the same as before during the reset_i2c_peripherals call, but due to the additional overhead of the read-modify-write to the GPIO register instead of just a write, the pulse width gets about 50% longer. Since the udelay call in drive_scl still has an open TODO to make this configurable and the pulses being longer is in the safe side, this side-effect can be addressed in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face Reviewed-on: https://review.coreboot.org/c/coreboot/+/56777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08soc/amd/*/bootblock,early_fch: rework i2c_scl_pins configurationFelix Held
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO configuration register and drives it as output, so don't initially configure the GPIO as input with no pull up/down. This is a preparation to use the common AMD GPIO access functions instead of the raw register accesses, since the gpio_set function only sets the output value, but doesn't reconfigure the direction. Using gpio_output there instead would reconfigure the direction as well, but would result in doubling the number of MMIO accesses, so just configure the GPIOs correctly right away to avoid that. TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook looks exactly the same as before during the reset_i2c_peripherals call. This was probed at the SCL pad of the unpopulated I2C level shifter on the side that is connected to the SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06soc/intel/broadwell: Drop unused PCH PCI device macrosAngel Pons
Get rid of several unused PCH PCI device macros. These macros expand to a call to the `pcidev_path_on_root_debug()` function, which only exists to debug bad code. If needed, these macros should be reimplemented with the `pcidev_path_on_root()` function instead. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I366e064f3fe708b55fb381aee25b2795b1c61142 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-06soc/intel/adl: Move USB4 hotplug Kconfig to commonFurquan Shaikh
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` that can be selected by mainboard to reserve hotplug resources for USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped from soc/intel/alderlake and instead the newly added Kconfig is now used. This new Kconfig is added so that the same config can be used across different platforms. In following changes, this Kconfig is utilized by TGL as well. Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-05soc/intel/common/cse: Add argument for CSE fixed client addrRizwan Qureshi
There are multiple HECI clients in the CSE. heci_send_receive() is sending HECI messages to only the MKHI client. Add an argument to heci_send_receive() function to provide flexibility to the caller to select the client for which the message is intended. With the above change heci_send() and heci_receive() functions are no longer required to be exposed. In the follow-up patches there will be messages sent to one other client. BUG=None BRANCH=None TEST=Build and boot brya. HECI message send and receive to MKHI client is working. Also, MEI BUS message to disable bus is working. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/alderlake: Add tpch device information under dptfSumeet Pawnikar
Add tpch device information for thermal functionality under dptf for alderlake soc based platform. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/common: Add PMC IPC commands for FIVRSumeet Pawnikar
Add PMC IPC commands information for FIVR control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/jasperlake: Utilize vbt data size Kconfig optionSeunghwan Kim
Currently maximum VBT data size for Jasper Lake is 8KB, but Bugzzy would use VBT data over 8KB. This change makes use of Kconfig option to increase the maximum VBT data size to 9KB for Jasper Lake. BUG=b:194029827 BRANCH=dedede TEST=build and boot bugzzy and verify fw screen is loaded Change-Id: I0abe1ba5609b48a8a8b15f88bec28342ce26c78f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57201 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-05soc/intel/elkhartlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-05soc/intel/cannonlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-05soc/intel/jasperlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I10f859f30b260d012f0bc8755f32413d8b2cf267 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-04soc/amd/picasso: select ADD_FSP_BINARIES if USE_AMD_BLOBS is selectedFelix Held
Since the FSP binaries for Picasso are present in the amd_blobs repo, select the ADD_FSP_BINARIES option if the Kconfig option to check out that repo is set. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-03sc7280: Refactor QSPI driverRoja Rani Yarubandi
Refactor Qcom QSPI driver to separate common and SoC specific driver code. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03soc/qualcomm/common/qspi: Add support for common QSPI driverRavi Kumar Bokka
copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder. This common QSPI driver works in master mode and provides read/write operation for the slave devices like flash. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03soc/qualcomm/sc7280: DDR One-Time-Training SupportRavi Kumar Bokka
Introduce DDR One-Time-Training Support Device reboots without training from second iteration and also DDR training data is 32kb size, hence update required in memlayout and to sync with upstream changes the Fmap size even got bumped up. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7280: Move to use common clock driver for sc7280Taniya Das
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. Also add support for Zonda PLL enable for CPU in common clock driver. Refactor the SC7280 clock driver to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/intel/alderlake: set power limits dynamically for thermalSumeet Pawnikar
Set power limit values dynamically based on CPU TDP and PCI ID of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/intel/common: get tdp of CPU for different SKUsSumeet Pawnikar
Get tdp value of CPU for different SKUs based on PKG POWER MSR. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-03soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chipsFelix Held
southbridge/amd/pi/hudson uses the common GPIO bank access code from soc/amd, but doesn't provide all functionality that would be needed to use the full functionality. Add a Kconfig option that switches off some functionality in the common SoC GPIO access code, so that more of the functionality proviced by the common SoC GPIO code can be used in the AMD binaryPI chipset and board code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/qualcomm/common: clock: Add support for common clock driverTaniya Das
The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7180: Clean up drivers with common clockTaniya Das
As we move to use the common clock driver, the sc7180 clock driver, watchdog and display drivers requires few cleanups, thus update the impacted drivers. Earlier the display client is expected to provide 2n divider value, as the divider value in register is in form "2n-1". mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; The older convention in the upcoming patches would be replaced with the common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated. mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0; To accommodate impacting the functionality, the half_divider is taken care in the clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03skylake: Default to `BOARD_TYPE_DESKTOP` for PCH-HAngel Pons
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H. Remove now-redundant mainboard code to set the `UserBd` UPD. Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03src/*: Specify type of `DIMM_MAX` onceAngel Pons
Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-02soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16Tim Crawford
TGL-H supports up to 8 cores (16 threads). Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01soc/amd/cezanne: Increase the FSP_M_SIZE configurationKarthikeyan Ramasubramanian
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is greater than the size allocated in DRAM. Increase the allocated size for FSP_M binary in DRAM to handle both debug and release FSP_M binaries. Also adjust the verstage load address accordingly. BUG=None TEST=Build and boot to OS in guybrush with both debug and release FSP_M. Perform warm, cold reboot and suspend/resume cycling for 10 iterations. Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01soc/intel/alderlake: Fix processor hang while plug unplug of TBT deviceSugnan Prabhu S
Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. BUG=b:194880254 Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01soc/amd/common: Change default spi speeds to 33MHzMartin Roth
In CB:56884 we discussed changing the default fast_read speed from 66MHz, which some platforms may not be capable of running, to 33MHz, which should be generally suitable for all platforms. This same change has been applied to the default for all SPI speeds. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31soc/amd/*/include/soc/gpio: remove GPIO_2_EVENTFelix Held
commit de7262f82cdc1a7c868dbc9ca41e186e885eb2ba (soc/amd: remove special GPIO_2 override soc_gpio_hook) removed the workaround that needed those definitions, so remove the now unused GPIO_2_EVENT definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/cezanne/fch: implement and use fch_clk_output_48MhzFelix Held
Make sure that the 48MHz clock output that is typically used as a clock source for an I2S audio codec or a Super I/O chip. TEST=On Guybrush before and after this patch the final state of MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd: Show SPI settings in bootblockMartin Roth
BUG=b:194919326 TEST=See SPI settings in bootblock Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 18:50:07 +0000