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2023-02-09amdfwtool: Add SOC family definition for CarrizoZheng Bao
For Carrizo, the soc name was set as UNKNOWN. The change is supposed to be binary unmodified, except the SPI settings. According to the spec, the Stoneyridge and Carrizo have the same definition of SPI setting in EFS. Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09treewide: Remove repeated wordsElyes Haouas
Found by linter Change-Id: I7a49cce0b56cf83d0e4490733f9190284a314c4a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09soc/amd/picasso/soc_util.c: Remove unneeded "break"Elyes Haouas
"break" is useless after "return". Change-Id: I84bc506a3d50e937797f42659299bf90ce392e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09soc/intel/common/block/gpio/gpio.c: Remove unnecessary line continuationElyes Haouas
Also remove unnecessary whitespace before "\n" Change-Id: Ia2c8fcb82658ed3e247759535d3112270d46e65d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09console: Add SimNow console loggingFred Reitberger
The AMD SimNow tool supports fast logging through an IO port. Add a new console to support SimNow logging through port 80. TEST=observe significant speed improvements on SimNow console log Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I42a431f48ea14ba4adacbd4a32e15abe7c5e4951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0Rex-BC Chen
For Geralt, we use BOE_TV110C9M_LL0 as MIPI firmware display, so add the power-on sequence for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72749 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-09mb/google/geralt: Init MT6359P only once in ramstageLiju-Clr Chen
The regulator MT6359P is needed by both firmware display and SD card. To avoid duplicate initialization in ramstage, publicize init_pmif_arb() as mt6359p_init_pmif_arb() and call it from mainboard_init(). This would save 13 ms for boot time on Geralt. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72839 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09soc/intel/meteorlake: Remove unsupported hybrid_storage_mode configSridhar Siricilla
The patch removes hybrid_storage_mode variable from soc_intel_meteorlake_config struct since hybrid storage is no longer supported on Meteor Lake platform. TEST=Verify the build for Rex board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"Felix Singer
This reverts commit d6e04aa00bc5a8912a041a569eb57f6962d1119a. Reason for revert: Breaks master. Change-Id: If7daeaaffe3f9ae9f5e2fbecef5817b9b62827d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72917 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-08device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORTSean Rhodes
Add NO_S0IX_SUPPORT for boards that do not support, or do not want to support S0IX. As all the boards in the tree that do this, don't support D3Cold, add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is selected to disable D3Cold support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-08soc/qualcomm/sc7280: init eMMCShelley Chen
Use common sdhci driver in coreboot to initialize eMMC for sc7280. This should allow us to initialize eMMC earlier in the boot process, taking it out of the critical path. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage Change-Id: Ifa88da500e82b44d7523f2e68763e01399c89f4d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71829 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/qualcomm/common: Add sdhci_msm_init functionShelley Chen
Porting from depthcharge changes for supporting eMMC driver functionality with standard SDHC controller on Qualcomm chipsets. sdhci_msm_init() needs to be run before the standard sdhci_mem_controller initiailzation. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72634 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd: use CPUID_FROM_FMS macro instead of magic numbersFelix Held
Port over the remaining AMD SoCs to use CPUID_FROM_FMS. The Glinda CPUID still needs to be updated to the actual CPUID, but for now just change it to use CPUID_FROM_FMS. TEST=Resulting image of timeless build for Gardenia (Stoneyridge), Majolica (Cezanne), Chausie (Mendocino), Mayan (Phoenix) and Birman (Glinda) don't change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia508f857d06f3c15e3ac9f813302471348ce3d89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72862 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/phoenix/soc_util: add get_soc_typeFelix Held
Implement a get_soc_type function to determine if the silicon the code is running on is Phoenix or Phoenix 2. This will for example be needed to provide the correct DXIO descriptor table for the SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f2b668b83432426b04e7f1354b694ddd6c300d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72861 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/picasso/soc_util: use cpuid_matchFelix Held
Now that there is a cpuid_match function, we can use it instead of doing basically the same thing manually. In the functions is_fam17_1x and is_fam17_2x both the stepping number and the lower nibble of the model number are masked out. To avoid having magic constants in the code, introduce the CPUID_ALL_STEPPINGS_AND_BASE_MODELS_MASK definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I758f9564c08c62c747cc4f93a8d6b540a1834a62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72860 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/mediatek: Add support for regulator VM18Sen Chu
To provide power to MIPI panel BOE_TV110C9M_LL0, add support for regulator VM18. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: Ib8c3b2df1157b23b37492b1e9b1716903ea67799 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72747 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08soc/mediatek: Remove unnecessary !! for boolean variableLiju-Clr Chen
Enable is already a boolean, so the !! is not needed. BUG=None TEST=build pass. Change-Id: I25a7cec632f21a258b8364c82e25b59e55ab7453 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72869 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08soc/amd/picasso: use CPUID_FROM_FMS macro instead of magic numbersFelix Held
TEST=Resulting image of timeless build for Mandolin doesn't change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44cb7759206e9e1ce79fd57f62b9a844e52f7394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72857 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/stoneyridge/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all family 15h model 60h and 70h steppings. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id05f849d59c04efa9f38dd66892f3cb99d94e3ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/72855 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/phoenix/include/cpu: add Phoenix CPUIDFelix Held
There are multiple Phoenix steppings, but that is now covered by using CPUID_ALL_STEPPINGS_MASK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4eb3502dec5ebdfdbba263b15b34621952d0554 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/glinda/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Glinda steppings once GLINDA_A0_CPUID is updated. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9b8cbb2dc925a8258db6a4eb0d1b00b2745637f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72852 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/phoenix/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Phoenix 2 steppings that might be available in the future. Right now it shouldn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If9878b4687360250cac4cfe1409d5dbad7147cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72851 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/mendocino/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Mendocino steppings that might be available in the future. Right now it shouldn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77ea8c6162667e0a318176e62078b1f57726c10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72850 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/cezanne: use CPUID_ALL_STEPPINGS_MASK to support all steppingsFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Cezanne steppings. This adds support for Cezanne stepping A1 and possible future steppings. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb020052685d9369109f391797fdd8f8790a91d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72849 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/picasso/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK to only need one CPU device ID table entry per family & model combination and not one per stepping. TEST=Mandolin with a Picasso APU with PICASSO_B1_CPUID (0x00810f81) still finished mpinit and boots successfully even though now only PICASSO_B0_CPUID (0x00810f80) with CPUID_ALL_STEPPINGS_MASK specified as device match mask. When commenting out the line with PICASSO_B0_CPUID as a negative test, mpinit fails as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I00ba43834ad86ecffa09d60599b17d122acd0b99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72848 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08arch/x86/cpu: introduce and use device_match_maskFelix Held
Instead of always doing exact matches between the CPUID read in identify_cpu and the device entries of the CPU device ID table, offer the possibility to use a bit mask in the CPUID matching. This allows covering all steppings of a CPU family/model with one entry and avoids that case of a missing new stepping causing the CPUs not being properly initialized. Some of the CPU device ID tables can now be deduplicated using the CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72847 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabledSean Rhodes
Both Alder Lake and Tiger Lake have Kconfig options for S3, which disables support for D3Cold. Unify these so that they are easier to compare. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/common/data_fabric: print decoded control register contentsFelix Held
Since all SoCs define the df_mmio_control union for the bits used in the code, data_fabric_print_mmio_conf can take advantage of that and also print a decoded version of those bits. Output on Mandolin before the patch: === Data Fabric MMIO configuration registers === idx control base limit 0 93 fc000000 febfffff 1 93 10000000000 ffffffffffff 2 93 d0000000 f7ffffff 3 1093 fed00000 fedfffff 4 90 0 ffff 5 90 0 ffff 6 90 0 ffff 7 90 0 ffff Output on Mandolin with the patch: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06e1d3a3e9abd664f59f2bb852394e7f723f2b30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/mendocino/data_fabric: add Rembrandt DF_MMIO_REG_SET_SIZEFelix Held
In contrast to Mendocino and all other AMD SoCs in the coreboot tree, Rembrandt, on which Mendocino is based on, has a DF_MMIO_REG_SET_SIZE of 3 instead of 4, so the next data fabric MMIO register is 3 DWORDs after the last one instead of the 4 DWORDs on the other SoCs. This was checked against PPR #56558 Rev 3.04. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I454ad5d182f0040db93c9b3a83941333392c6061 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/*/data_fabric: introduce and use DF_MMIO_REG_SET_SIZEFelix Held
To be able to handle a special case, add a per-SoC define for DF_MMIO_REG_SET_SIZE instead of having this hard-coded as 4 in the DF_MMIO_* macros. To avoid some duplication, also introduce the DF_MMIO_REG_OFFSET macro. TEST=Output from data_fabric_print_mmio_conf doesn't change on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67420a2973c8ef9a7f0ce19ddc0013de69731689 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/common/data_fabric: replace NB with DF prefix for DF registersFelix Held
Since the MMIO decode range registers in the data fabric are part of the data fabric and not of the northbridge, replace the NB prefix with a DF prefix to make this a bit clearer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ife5e4581752825e9224b50252955d485a067af74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/*/data_fabric: rename define for MMIO decode register set countFelix Held
This should make it a bit clearer that those registers are in the data fabric configuration registers. Also move those defines right after the register definition those are related to. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic107bd217f4af0a9ddfbe41aafd3c882aa968e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/phoenix/include/cpu: rename CPUID define to match CPU modelFelix Held
CPUID 0x00a70f80 is Phoenix 2 and not Phoenix, so update the define name to match. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7500130d5470fdd824980b81746f3a0f6d277d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72843 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-07soc/amd/stoneyridge/acpi: use acpigen_write_processor_deviceFelix Held
Since things are done a bit differently on Stoneyridge, it's probably safer to run a test instead of assuming that the test on Picasso was sufficient to be reasonably sure that this will also work as expected on Stoneyridge. TEST=No change of ACPI-related messages in dmesg with this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I432752fae8be08d3cbd7d30215b350c4528c7206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-07soc/intel/alderlake: Remove unused S0IX variableSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85fc5dabf10c6df7f11fd1defe8a39afc9f95325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72797 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07soc/amd/common/data_fabric_helper: normalize addresses in debug printFelix Held
Instead of just printing the register contents, normalize the contents of the base and limit registers to actual MMIO addresses and then print those. This will hopefully avoid some confusion caused by the shifted addresses. Output on Mandolin before the patch: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 1093 fed0 fedf 4 90 0 0 5 90 0 0 6 90 0 0 7 90 0 0 Output on Mandolin after the patch: === Data Fabric MMIO configuration registers === idx control base limit 0 93 fc000000 febfffff 1 93 10000000000 ffffffffffff 2 93 d0000000 f7ffffff 3 1093 fed00000 fedfffff 4 90 0 ffff 5 90 0 ffff 6 90 0 ffff 7 90 0 ffff Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-07src: Move POST_BOOTBLOCK_CAR to common postcodes and use itMartin Roth
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-07tree: Drop repeated wordsAlexander Goncharov
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-06soc/amd/glinda: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Glinda SoC, remove it form the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I627d05c09d9637caf15e17285dd2c8e0389747c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/phoenix: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Phoenix SoC, remove it form the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/72186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/mendocino: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Mendocino SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/cezanne: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/picasso: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Picasso SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/stoneyridge: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Stoneyridge SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Eventually the LIDS object should probably be moved to the EC's ACPI code, but that's out of scope for this patch. TEST=google/liara doesn't show ACPI errors in Linux' dmesg Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-02-06soc/intel/apl: Hook up cpu ops in devicetreeArthur Heymans
This simplifies the code flow of the cpu init. APL can do CPU init after calling FSP-S, while GLK needs to do that before. This is now reflected directly in the cpu ops rather than using CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT as a proxy. Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-02-04soc/amd/phoenix/chipset.cb: update USB portsFelix Held
Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: add remaining PCI devicesFelix Held
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2Felix Held
Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1Felix Held
Only the PCIe ports on the functions of device 2 were present in the devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the missing PCIe ports on the functions of device 1 and assign the amd_external_pcie_gpp_ops ops to them. This SoC uses a slightly different naming scheme for its PCIe GPP ports. Previously the PCIe GPP bridge number from the PCI Device ID Assignments table from the PPR was used. Those bridge numbers are one less than the function numbers of the device. This is due to function 0 being a dummy bridge to avoid having to shuffle around the function numbers when the first bridge is unused, since the PCIe specification mandates the function 0 to be implemented if any other function on the same device is implemented. In order for the device aliases to be consistent with the PCIe device and function numbers which is way more commonly used and also what lspci shows and what goes into the DXIO descriptors, change the naming scheme of the aliases. This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72736 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/intel/meteorlake: Enable MRC Fast BootSubrata Banik
This patch requests FSP to enable the MRC fast boot feature along with FSP v2473. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4a621e55c853505f7a702181ae5a70dc56d5b5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72745 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridgesFelix Held
Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree") missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge PCIe ports, so add them. Those devices were previously covered by the PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that got removed in the referenced commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04soc/amd: Use common reset code for PCO SoCMartin Roth
This switches the Picasso SoC to use the common reset code. Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET flag. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Use common reset code for PHX & Glinda SoCsMartin Roth
This switches the Phoenix & Glinda SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Use common reset code for CZN & MDN SoCsMartin Roth
This switches the Cezanne & Mendocino SoCs to use the common reset code. This patch does not change any behavior on those chips. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Create AMD common reset codeMartin Roth
This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_AMD_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/intel/*: Fix dead bootstate codeArthur Heymans
No bootstate hook is called on exit of BS_OS_RESUME or BS_PAYLOAD_BOOT. Change-Id: I2b5b834d0663616a9523fd119f007e3bac8e7bf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-02-04soc/intel/tgl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-03soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev treeKane Chen
This commit provides a dev tree setting for partners to enable/disable TccoldHandshake for the sighting in doc:723158 BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=compile ok and FSP UPD is config properly Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68635 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/alderlake: Add a few missing definitions in iomap.hJeremy Compostella
Some reserved address range listed in Alder Lake Platform Firmware Architecture Specification document 626540 section 6.4 ADL - System Memory Map such as North TraceHub ranges were missing. Details about North TraceHub (aka. Intel TraceHub) can be found in Intel Trace Hub (Intel TH) Developer's Manual document 671536. BUG=b:264648959 TEST=Compilation successful Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-03soc/intel/alderlake: Add a missing RPL-P power limits configurationJeremy Compostella
This patch adds the {MCH:a706, TDP:28W} missing 28W configuration. BUG=b:267666609 BRANCH=firmware-brya-14505.B TEST=Power Limit are properly set on skolas 28W Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-02soc/intel/alderlake: Add entries to eventLog on invocation of early SOLTarun Tuli
If we show the user early signs of life during CSE FW sync or MRC (re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:264648959 TEST=event shows in eventlog after CSE sync and/or MRC Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Signed-off-by: Tarun Tuli <taruntuli@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71295 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-02-02soc/intel/xeon_sp: add Kconfig file for SPR-SPJonathan Zhang
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. Change-Id: I14cf115b02d8edff9b48e744b798a3b1ba18b8bf Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-02soc/intel/meteorlake: Enable V1p05-PHY supply external FET controlSubrata Banik
This patch enables S0i2.2 by letting 1.5V Phy supply to control the externa FET. BUG=b:256805904 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72709 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-02soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUSLiju-Clr Chen
USB1_DRV_VBUS is used to provide 5V power for USB on MT8188 EVB and it's not used on Geralt. Therefore, remove the GPIO setting of USB1_DRV_VBUS. TEST=read usb data successfully. BUG=b:236331724 Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72641 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/qualcomm/sc7280: Memlayout change to support new Crypto sha updateVenkat Thogaru
With New Crypto upgrade we need to have 1 block of 4Kb increase in romstage, by which we can see an improvement of Boot performance by 100 msec. BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board Boot performance improved by 100 msec observed. Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-01soc/qualcomm/common/qup: Avoid double decompress of gsi_fw blobSudheer Kumar Amrabadi
During boot, gpi_firmware_load gets called twice because there are 2 serial engines. Thus gsi_fw blob is also decompressed twice and is written to base addresses of SEs. This is redundant. Perform the decompression once on first call and save the header in static variable which can be reused in next call. BUG=b:262426214 TEST=Validated on qualcomm sc7280 development board Saving of 80ms observed while testing with 130 boot cycles. Change-Id: If98a3974f0791dffdf675c02cc28375d0485c485 Signed-off-by: Vijaya Nivarthi <vnivarth@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71927 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/amd/mendocino: Force resets to be coldMartin Roth
Like Cezanne, Mendocino does not support warm resets. Change all resets (including resets in the OS) to cold resets (like Cezanne). BUG=b:248221908 TEST=Run suspend_stress_test, then reboot Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72486 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-01soc/intel/jsk: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/skl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic42c67163fe42392952499293e91e35537cb9147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/cnl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-01soc/intel/mtl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM. DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid a potential error seen in ADL devices as mentioned in commit 3fd5b0c4cdeb ("soc/intel/adl: remove DPTF from D-states list used to enter LPM") TEST=Built and tested on Rex, saw SSDT generated properly. BUG=b:231582182 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I9192ed9a7fb59ebba14f6d5082b400534b16ca72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72603 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/amd/glinda/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iec9cf7c195fa5cb5c8d992aeab400d05cbe801c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/phoenix/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I103cdce8c23ff4adbf1057fa26bd67275f2ab0e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/mendocino/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I036dcddf89e8d865d0dc3ef0bd9e48842d8bf6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/cezanne/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77a91c0a6d937772bf25fa936cec8a710b9acf72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/picasso/acpi: use acpigen_write_processor_deviceFelix Held
In CB:71614 Kyösti pointed out that ACPI_GPE0_BLK is the wrong address to assign to proc_blk_addr; the correct one would be ACPI_CPU_CONTROL. When looking a bit closer into this, it turned out that acpigen_write_processor is generating deprecated AML opcodes, so replace the acpigen_write_processor call with a call to the newly added acpigen_write_processor_device function that also doesn't have the proc_blk_addr and proc_blk_len parameters. The information about the IO port for entering C-states is already written into an SSDT by acpigen_write_CST_package which is likely also the reason why the wrong proc_blk_addr value wasn't noticed for a very long time. TEST=Mandolin still boots Ubuntu 22.04 LTS and Windows 10 and no possibly related errors show up. Linux gets the expected C-state information from the _CST package inside the processor device scope. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie67416e19e431029dd12da66ad44ddfa8586df03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL defineFelix Held
This register isn't used in coreboot and isn't defined in the Picasso PPR #55570 Rev 3.18. To enter a lower C-state, a read request to a special IO port is done. The base address of this group of IO ports is configured in set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave the CPU. IIRC trying to put the MMIO mapping for entering the lower C-states into the _CST package didn't work as expected when it was tried on I think Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-31soc/intel/ehl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I7dfd331e70f6d03c88248ca5147dbe6785a8e69d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-31soc/intel/alderlake: Pick an unused and safer graphics address spaceJeremy Compostella
It turns out that the [0xfa000000-0xfaffffff] range conflicts with some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and [0xfacfc000-0xfacfffff]). Experiments have established that this conflicting range results in an unpected PIPE A underrun issue reported by i915 and some visible flickers on the display during boot. The [0xf0000000-0xffffffff] range is a crowded memory space with resources statically assigned to some devices but also some ranges used at various point in the boot flow by the FSP. To not run into any other potential conflicts, we want to pick a unused memory space. But at this early stage of the boot, we do not have full knowledge of what memory space is going to be used by the FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range as: 1. It does not conflicting with any coreboot memory space usage 2. It is the address the FSP uses by default for GFX MMIO BAR0 and as such should not conflict with any FSP memory space usage. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=No flickers observed on boot Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-31soc/intel/apl: Ensure CPU_CLUSTER linked_list bus existsArthur Heymans
This fixes a NULL pointer deref introduced by 69cd729 (mb/*: Remove lapic from devicetree). Change-Id: I816fddfe3efe3c3aefe1b2ee28426dc1e1f3c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72599 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31soc/intel/common/block: Add LPC BIOS decode lockTim Chu
The LPC BIOS decode lock bit is defined in EBG EDS documentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71954 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-29soc/intel/xeon_sp/Kconfig: add SOC_INTEL_SAPPHIRERAPIDS_SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) chipset belongs to Xeon-SP family. It was product launched on Jan. 10, 2023. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifece05e2fbcc454cdee8e849cb4f146c89f54333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-29soc/intel/xeon_sp/include/soc/pmc.h: move to lbg directoryJonathan Zhang
The PMC registers are quite different between LBG and EBG. Move pmc.h to lbg directory to differentiate. Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-28soc/intel/common/block/acpi/pep: use acpigen_write_processor_namestringFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43590f0f792fca1c90ee8f8b32e6be47943c59df Reviewed-on: https://review.coreboot.org/c/coreboot/+/72453 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27intelblocks/cse: Add functions to check and change PTT stateMichał Żygowski
Add functions that allow checking and changing PTT state at runtime. Can be useful for platforms that want to use dTPM instead and have no means to stitch ME firmware binary with disabled PTT. The changing function also checks for the current feature states via HECI to ensure that the feature state will not be changed if not needed. TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-01-27soc/intel/adl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid an error seen after it was added to that table: "ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.DPTF (20200925/dspkginit-438)" TEST=Built and tested on anahera and saw the error is gone BUG=b:231582182 Change-Id: I00eddd7e4cc71a0c25e77ff53025dee5bf942de1 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-27soc/intel/mtl: Add missing claimed memory regionsEran Mitrani
This CL adds claimed memory regions that were missing for the resource allocator. See commit ca741055e6b6 ("soc/intel/adl: Add missing claimed memory regions") for details. TEST=Booted rex and saw the previously missing ranges getting added from AP Log (with this CL): SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000 SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000 SA MMIO resource: LT_SECURITY -> base = 0xfed20000, size = 0x00060000 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000 SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000 SA MMIO resource: DSM -> base = 0x7c000000, size = 0x04000000 SA MMIO resource: TSEG -> base = 0x7b000000, size = 0x00800000 SA MMIO resource: GSM -> base = 0x7b800000, size = 0x00800000 dmesg: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x00000000759c9fff] usable BIOS-e820: [mem 0x00000000759ca000-0x000000007fffffff] reserved BIOS-e820: [mem 0x00000000c0000000-0x00000000e0ffffff] reserved BIOS-e820: [mem 0x00000000f8000000-0x00000000f9ffffff] reserved BIOS-e820: [mem 0x00000000fd800000-0x00000000fe7fffff] reserved BIOS-e820: [mem 0x00000000feb00000-0x00000000feb7ffff] reserved BIOS-e820: [mem 0x00000000fec00000-0x00000000fecfffff] reserved BIOS-e820: [mem 0x00000000fed20000-0x00000000fed83fff] reserved BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved BIOS-e820: [mem 0x00000000fedc0000-0x00000000feddffff] reserved BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable BIOS-e820: [mem 0x000003fff0aa0000-0x000003fff0aa1fff] reserved Change-Id: I749e7b6e969f8d6314fcd2906acd7de69d4d9f9c Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-26soc/intel/alderlake: Wait for panel power cycle to completeJeremy Compostella
The Alder Lake PEIM graphics driver executed as part of the FSP does not wait for the panel power cycle to complete before it initializes communication with the display. It can result in AUX channel communication time out and PEIM graphics driver failing to bring up graphics. If we have performed some graphics operation in romstage, it is possible that a panel power cycle is still in progress. To prevent any issue with the PEIM graphics driver it is preferable to ensure that panel power cycle is complete. This patch replaces commit ba2cef5b5493 ("soc/intel/common/block/early_graphics: Introduce a 200 ms delay") workaround patch. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible in the recovery flow Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26drivers/intel/gma: Use libgfxinit Update_Output to turn off graphicsJeremy Compostella
We were using the libgfxinit `Initialize' function with the `Clean_State' parameter because the more appropriate `Update_Output' function was not performing all the necessary clean up operations for the PEIM driver to be successful when libgfxinit was used in romstage. Thanks to a lot of experiments and some log analysis efforts, we were able to identify the missing operation and fix the `Update_Output' function (cf. https://review.coreboot.org/c/libgfxinit/+/72123). The `initialized' global variable is now unnecessary as we track the initialization in the Ada code instead. Since the `Update_Output' function does not return any value, this patch modifies the `gma_gfxstop' prototype accordingly. This does not have any impact as the return value was not used anyway. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-25soc/intel/mtl/acpi: add FSPI to DSDTEran Mitrani
Getting an error from the Kernel on Rex devices: > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI (20210730/dspkginit-438) FSPI is defined in src/soc/intel/meteorlake/chipset.cb: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. See commit feed8e4bd9dc ("soc/intel/adl/acpi: add FSPI to DSDT") for the corresponding ADL CL. TEST=Built and tested on brya by verifying the error is gone. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id8d2a1b5e074f036345e028b117d420bf36a9042 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-25soc/intel/common/gpio: Add function to read GPIO TX valueCliff Huang
This function reads out the current value set to output for a GPIO pin. Ex: GPP_E0 is set to output int e0_val; e0_val = gpio_tx_get(GPP_E0); Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-25soc/intel/alderlake: Increase premem cbmem buffer size to 16KBTarun Tuli
Current size of the cbmem premem buffer (8KB) is sometimes insufficient to contain the complete debug log causing the cbmem console buffer to indicate overflow. This patch increases the premem cbmem buffer size to 16KB so that the complete debug log can be stored in it. TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Change-Id: I60c68322c52191eabf7e06b4be06e66f90ff8751 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25soc/intel/cmn/block/pcie: Make ASPM configurableMaximilian Brune
Currently ASPM cannot be disabled by individual mainboards, if the soc Kconfig includes SOC_INTEL_COMMON_PCH_CLIENT. Other options like PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE are already configurable by individual mainboards if needed. This change makes PCIEXP_ASPM one of these configurable options. Test: build prodrive/atlas and see that build/config.h lists the option CONFIG_PCIEXP_ASPM as disabled. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic9c049f1d225bc21d8da5bd208651ad847ae0c6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72117 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-24soc/intel/alderlake: Increase cbmem buffer size for the debug imageTarun Tuli
Currently most of the FSP debug messages (when enabled) are truncated due to insufficient size of cbmem buffer. Increase premem cbmem console size to 0x16000 bytes and cbmem buffer size to 0x100000 bytes so that cbmem buffer can contain most of the debug logs when FSP debug messages are enabled. TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled but MRC debug message. Change-Id: I0273fb14916f213b686270a9dec4c1b47612af4d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/alderlake: Increase cbmem buffer size to 256KBTarun Tuli
Current size of the cbmem buffer (128KB) is insufficient to contain the complete debug log causing the cbmem console buffer to wrap. This patch increases cbmem buffer size to 256KB so that the complete debug log can be stored in it. TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Change-Id: I2099386dd87a010c3a5937bd896620270f587b1c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71288 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. The chipset includes Emmitsburg PCH. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-24soc/intel/alderlake: Implement API to disable UFS controllersSubrata Banik
This patch implements a new API to make the UFS controller function disabled. Additionally, perform a warm reset post disabling the UFS controller to let PMC know about the state of the UFS controller and disable the MPHY clock. BUG=b:264838335 TEST=Able to build and boot Google/Marasov successfully. From the AP log, I am able to confirm that UFS is function disabled using PSF. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I940a634f70f8c97ef1234866d4c5a1ff224c6e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-24soc/intel/adl: Option to create unified AP FW for UFS/Non-UFS SKUsSubrata Banik
This patch makes it easy for OEMs to keep a unified AP firmware image to boot different SKUs with UFS and non-UFS as boot media. With a unified image while booting on non-UFS SKU is exhibiting S0ix failure due to UFS remain enabled in the strap although FSP-S is making the UFS controller function disabled. The potential root cause of this behaviour is although the UFS controller is function disabled but MPHY clock is still in active state. A possible solution to this problem is to issue a warm reboot (if boot path is S5->S0 or G3->S0) after disabling the UFS and let PMC read the function disable state of the UFS for disabling the MPHY clock. Mainboard users with such board design where OEM would like to use an unified AP firmware to support both UFS and non-UFS sku booting might need to choose this config to allow disabling UFS while booting on the non-UFS SKU. Note: selection of this config would introduce an additional warm reset in cold-reset scenarios due to function disabling of the UFS controller. BUG=b:264838335 TEST=Able to build and boot Google/Marasov successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a811d8f4aad41dab6f8988329eaa1d590a4637a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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