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2018-11-16soc/qualcomm/ipq{40xx,806x}/Kconfig: Remove unused MBN_ENCAPSULATIONElyes HAOUAS
Change-Id: I4cf5cd1d3bed7188590e4f143d8f14dc9e58b183 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16soc/intel/{broadwell,skylake}: Remove unused SERIAL_CPU_INITElyes HAOUAS
Change-Id: I2296ab3c53a82ee990649e35e1370e1dd304e392 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16mediatek: Refactor PMIC wrapper code among similar SoCsTristan Shieh
Refactor PMIC wrapper code which will be reused among similar SoCs. Move reusable code into the common folder. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16soc/intel/braswell: add vmx support via CPU_INTEL_COMMONMatt DeVillier
Braswell allready supported vmx, but offered no mechanism to unset it, nor to set the lock bit required for Windows to recognize virtualization. Enable this functionality by adding CPU_INTEL_COMMON config. Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows virtualization as enabled. Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/29570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16fsp_broadwell_de: Switch to common SPI controller driverWerner Zeh
The common SPI controller driver in src/southbridge/intel/common does match the SPI controller included in the PCH of Broadwell-DE SoC. Switch to the usage of this driver and delete the dedicated one for the FSP based Broadwell-DE implementation. TEST: Boot mc_bdx1 with SPI driver active in romstage Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/29633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16soc/amd: Convert from AMD units to coreboot unitsRichard Spiegel
There are several files under soc/amd that use units defined by file porting.h. These units use upper case, and are not recognized by checkpatch, thus causing problems when defining a pointer (request to use space before and after the star symbol). These are the definitions from porting.h showing the units that this patch will change and their coreboot definitions (not all are actually used): typedef uintptr_t UINTN; typedef int64_t INT64; typedef uint64_t UINT64; typedef int32_t INT32; typedef uint32_t UINT32; typedef int16_t INT16; typedef uint16_t UINT16; typedef int8_t INT8; typedef uint8_t UINT8; typedef char CHAR8; typedef unsigned short CHAR16; typedef unsigned char BOOLEAN; typedef void VOID; BUG=b:118775313 TEST=Build and boot grunt. Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16soc/amd/common: Remove unused variables of write_pci_cfg_irqs()Richard Spiegel
Function write_pci_cfg_irqs() has "no function" variables. One variable is set and never used, the other is only used to control a print. Remove them. BUG=b:117950052 TEST=Build grunt. Change-Id: Icd98db3e794e609b112f15979a3a00a2977a0fdb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-15soc/intel/skylake/acpi/dptf: Add support for Multi-DPTF ProfileKarthikeyan Ramasubramanian
Currently mode-aware DPTF depends on Tablet Mode Switch to load the right table. This does not scale well with device types and configuration. This change helps to decouple the mode-aware DPTF from Tablet Mode Switch. This change allows ACPI to load the appropriate DPTF table based on the profile number as detected by EC. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes(base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: Ibffe9c58f970aec37aa74a040170c4cf559bab33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29249 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-15ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES since it aligns with the use-case. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes (base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-15soc/intel/cannonlake: Make static IRQ mapping for PIC modeSubrata Banik
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC. Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29629 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-15soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devicesSubrata Banik
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call due to PCH requirement change from CNP PCH onwards, hence making static IRQ mapping for pci_irqs.asl and pcie.asl Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/ Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-15src/cpu: Remove dead sourced linesElyes HAOUAS
Change-Id: I836ff09da17373d47daf21c98e5ab975836cd47e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-15oc/intel/quark/Kconfig: Remove unused MMCOMF_SUPPORT_DEFAULTElyes HAOUAS
Change-Id: I24596b7b4f3e7caef7f42e4317a786caa42c5c2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-13soc/intel/cannonlake: Remove SmbusEnableDuncan Laurie
Remove the SmbusEnable config option from devicetree and instead use the state of the PCI device to determine if it should be enabled or disabled. Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-13soc/intel/icelake: Update GPIOs for Icelake SOCAamir Bohra
This implementation updates the GPIO pins, communities and group mapping. Change details: 1. Update 5 GPIO community includes 11 GPIO groups GPIO COM 0 GPP_G, GPP_B, GPP_A GPIO COM 1 GPP_H, GPP_D, GPP_F GPIO COM 2 GPD GPIO COM 4 GPP_C, GPP_E GPIO COM 5 GPP_R, GPP_S 2. Update GPIO IRQ routing. 3. Add GPIO configuration for iclrvp board. Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-11-13soc/intel/common: Add option to call EC _PTS/_WAK methodsDuncan Laurie
Some embedded controllers expect to be sent a command when the OS calls the ACPI \_PTS and \_WAK methods. For example see the code in ec/google/wilco/acpi/platform.asl that tells the EC when the methods have been executed by the OS. Not all ECs may define these methods so this change requires also setting a Kconfig option to enable it. Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-09soc/intel/apollolake: Disable HECI1 before jumping to OSFurquan Shaikh
This change disables HECI1 device at the end of boot sequence. It uses the P2SB messaging to disable HECI1 device before hiding P2SB and dropping privilege level. BUG=b:119074978 BRANCH=None TEST=Verified that HECI1 device is not visible in lspci on octopus. Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-09mb/google/kahlee: Tune eDP panel initialization timeChris Wang
1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-09mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/icelake Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-11-08soc/intel/common: Add option to disable eSPI SMI at runtimeDuncan Laurie
Add an option that will disable eSPI SMI when ACPI mode is enabled, and re-enable eSPI SMI when ACPI mode is disabled. Additionally it ensures eSPI SMI is disabled on the ACPI OS resume path. This allows a mainboard to ensure that the Embedded Controller will not be able to assert SMI at runtime when booted into an ACPI aware operating system. This was tested on a Sarien board with the Wilco EC to ensure that the eSPI SMI enable bit is clear when booted into the OS, and remains clear after resume. Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mediatek/mt8183: Add DDR driver of write leveling partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-08mediatek/mt8183: Add DDR driver of cmd bus training partHuayang Duan
BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-08mediatek/mt8183: Add DDR driver of pre-calibration partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28838 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08soc/intel/skylake: Add PCH sku id's supported for KBLPraveen hodagatta pranesh
This patch also add new SKL PCH-H device id's in soc platform reporting and common lpc driver. BUG=None TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id in serial logs. Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08soc/intel/apollolake: Improve cold boot and S3 resumeJohn Zhao
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07soc/intel/common: Include Icelake device IDsAamir Bohra
Add Icelake specific CPU, System Agent, PCH, IGD device IDs. Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07soc/amd/stoneyridge: Fix 81+ characters linesRichard Spiegel
There some files that do have at least 1 line over the 80 characters limit. Find and fix them. BUG=b:117950052 TEST=Build grunt. Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-07soc/intel/skylake: Add FSP CAR support for kabylakePraveen hodagatta pranesh
Kabylake RVP11 uses FSPT to support Intel security features like bootguard verify boot and measured boot. This patch add FSP CAR support for kabylake by programming tempraminit parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is selected in order to relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG=None TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified for successful FSP CAR setup. Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/cannonlake Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07soc/intel/apollolake: Provide interface to update TCC offsetJohn Su
This change provides an interface for apollolake to set TCC before BIOS reset complete happens in romstage. With this change, we can add code to update Tcc in devicetree. BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-07timer: Add wait_us/wait_ms helper macros to wait for conditionsJulius Werner
A very common pattern in drivers is that we need to wait for a condition to become true (e.g. for a lock bit in a PLL status register to become set), but we still want to have a maximum timeout before we treat it as an error. coreboot uses the stopwatch API for this, but it's still a little verbose for the most simple cases. This patch introduces two new helper macros that wrap this common application of the stopwatch API in a single line: wait_ms(XXX, YYY) waits for up to XXX milliseconds to see if the C condition 'if (YYY)' becomes true. The return value is 0 on failure (i.e. timeout expires without the condition becoming true) and the amount of elapsed time on success, so it can be used both in a boolean context and to log the amount of time waited. Replace the custom version used in an MTK ADC driver with this new generic version. Change-Id: I6de38ee00673c46332ae92b8a11099485de5327a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-06soc/amd/common: Fix function formatingRichard Spiegel
There are functions within heapmanager.c that have a space between the function name and open parenthesis. Remove these spaces. BUG=b:117950051 TEST=build grunt. Change-Id: I2120d9d5f663453b6201d1872f29c6dc4abd6191 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29230 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05soc/amd/stoneyridge: Get rid of void pointer mathRichard Spiegel
Pointer math with void pointers is illegal in many compilers, though it works with GCC because it assumes size of void to be 1. Change the pointers or add parenthesis to force a proper order that will not cause compile errors if compiled with a different compiler, and more importantly, don't have unsuspected side effects. BUG=b:118484178 TEST=Build and boot grunt. Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-05mediatek/mt8183: Add DDR driver of software impedance partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I42a33ffb66ffa2f938f85484ffc3a0d3788816b3 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-05src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstageFrans Hendriks
soc_rtc_init() is executed in ramstage The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC init from ramstage to romstage. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/29397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-05soc/intel/cannonlake: Enable ISH from deviceLijian Zhao
PCH ISH enabled/disabled in FSP memory init UPD, it will be match the setting in ISH device on/off in devicetree.cb. BUG=N/A TEST=Build and pass on whiskey lake rvp platform. Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-11-05soc/intel/cannonlake: Remove depreciated UPD selectionLijian Zhao
Several FSP silicon init UPD have been moved to memory init stage, modify the coreboot accordingly. The UPDs below are affected: SkipMpInit VtdBaseAddress VtdDisable X2ApicOptOut BUG=N/A TEST=Build pass with FSP revision 7.0.47.50. Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29260 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05riscv: add support smp_pause / smp_resumeXiang Wang
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume at the end of each stage. Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/29023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-11-05src: Remove unneeded include <arch/ioapic.h>Elyes HAOUAS
Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29292 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05soc/intel/icelake: Add PID based on Icelake EDSAamir Bohra
Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-02mediatek/mt8183: Add AUXADC driverPo Xu
We plan to get board id and RAM code from AUXADC on Kukui. Add AUXADC driver to support it. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I121a6a0240f9c517c0cbc07e0c18b09167849ff1 Signed-off-by: Po Xu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/29061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-02soc/intel: Enable GPIO functions in verstageDuncan Laurie
Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29407 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02soc/intel/icelake: Allow coreboot to reserve stack for fspAamir Bohra
Change-Id: I5f2d9548b8e2c7b1d154b7bad126ec7b1052231a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-31soc/amd/stoneyridge: Fix get_cpu_count()Martin Roth
In commit 41baf0c3ff (soc/amd/stoneyridge: Remove dev_find_slot where possible), the register being read was changed accidentally from HT_DEV (Device 18h, Func 0) to NB_DEV (Device 18h, Func 5) This doesn't return the correct value, and causes Grunt to reboot. BUG=b:118721473 TEST=Boot grunt Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/29367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-31soc/amd/stoneyridge: Get rid of domain_read_resourcesMartin Roth
The function domain_read_resources() didn't have any code to actually reserve any resources - it was just creating an empty resource entry. I looked at fixing it to actually reserve the space, but the values in the registers at the point when this runs aren't the final values that we want to reserve anyway, they're temp values with a range much larger than we want to reserve. I next looked at moving the amd_initcpuio() function earlier so that we could get the correct values for the registers, but even that doesn't give us what we really want. Ultimately removing this whole function seems to be the right thing. BUG=None TEST=Verify that the only resource that changes is the empty resource: PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080 Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/29345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-31soc/intel/apollolake: Revert the w/a nWR_24 settingJohn Zhao
GLK FSP 2.0.6.0 has properly determined MR1 value during InitializeJedec. Revert the w/a code "odt_config |= nWR_24" in coreboot. BUG=b:118422998 CQ-DEPEND=CL:*703187 TEST=Verified booting to kernel. Change-Id: I6dd3c14b2048259a5518e1f72ff1061b9c5c7dfe Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-31soc/intel/icelake: Open ports 0x60,0x64 for keyboard controllerShelley Chen
BUG=b:112110028 BRANCH=none TEST=boot into recovery in ec console: kblog on (type on keyboard) kblog make sure buffer is not empty Change-Id: I6525c2a46eef835dc64682466364a5b8fbb35226 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-30src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29177 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30soc/amd/stoneyridge: Set IOMMU support to follow device settingMartin Roth
Instead of forcing the IOMMU to be enabled, change it to only be enabled if the device is enabled in devicetree. BUG=b:118612241 TEST=Verify that IOMMU is disabled. Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/29343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-10-30soc/amd/stoneyridge: Remove dev_find_slot where possibleRichard Spiegel
The procedure dev_find_slot has 3 main uses. To find configuration (devicetree), to verify if a particular device is enabled at build \ time, and to get the address for PCI access while in bootblock/romstage. The third use can be hidden by using macros defined in pci_devs.h, making it very clear what PCI device is being accessed. replace the temporary pointers to device used with PCI access with SOC_XXX_DEV where XXX is the device being accessed, and remove the setting of the temporary pointers. BUG=b:117917136 TEST=Build grunt. Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30sifive/fu540: correct cbmem supportPhilipp Hug
Return correct memory location for cbmem instead of incorrectly returning memory size. Change-Id: If7f490a46edebb04c2280bf317d1adacef08f30d Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/29197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xiang Wang <wxjstz@126.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-29tegra210_lp0: make sure to build with compiler.h includedNico Huber
Like in ce1064e (tegra124_lp0: make sure to build with compiler.h included), fix builds where `compiler.h` is needed. Change-Id: If4b60a9db4520b58e48339a7e2726f2545cb4102 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-27soc/intel/*: Make FSP header path user configurablePatrick Georgi
Required to compensate for Chrome OS' tree differences Change-Id: I01fe80b55c69ff57da1c96a76bd1d9b5a2d4a9a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-26soc/intel/icelake: Do initial SoC commitAamir Bohra
Clone entirely from Cannonlake commit id: 3487095304dbbbf66de86f8bce0e40b7acb3ea27 List of changes on top off initial cannonlake clone 1. Replace "Cannonlake" with "Icelake" 2. Replace "cnl" with "icl" 3. Replace "cnp" with "icp" 4. Rename structrue based on Cannonlake with Icelake 5. Remove and clean below files 5.a. All NHLT blobs and related files. 5.b. remove cnl_memcfg_init.c file, will be added later. 5.c. Remove vr_config.c, this is WIP. 5.d. Clean up upd override in fsp_params.c, will be added once FSP available. 5.e Remove CNL-H based GPIO configuartion. Ice Lake specific changes will follow in subsequent patches. Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29162 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-26mediatek/mt8183: Correct MPU ctrl register addressHuayang Duan
Remove unused members in emi_mpu_regs and sdram_params. Change mpu_ctrl_d to array so the offset (0x804) for D1 is corrected. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/29251 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-26soc/intel/cannonlake: Add back PM TIMER EMULATIONLijian Zhao
ACPI PM timer emulation will be added back as default FSP stops TCO count for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER EMULATION will help UEFI payload pass, instead of endless loop wait for ACPI PM timer counter to increase. BUG=N/A TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell. Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28937 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-25soc/amd/common/def_callouts.c: Prefer using '"%s...", __func__'Richard Spiegel
In function agesa_GfxGetVbiosImage(), the function name is used in a print string. Use __func__ instead. BUG=b:117642170 TEST=Build grunt. Change-Id: I95a042bd95cc729305a8a008e3bb464f60c2668d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-25soc/amd/stoneyridge: Remove "else" after a returnRichard Spiegel
File ramtop.c has one instance of if()/else where the if tests for top mem in lower 4GiB, and returns just before the "else" statement. These "else" statements are not needed. BUG=b:117648025 TEST=Build and boot grunt. Change-Id: Iba16a416e78dae75a95a11d38179161c5a11b2ad Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29247 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-25soc/intel: Consolidate FSP CAR setup and teardown codePraveen hodagatta pranesh
This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-25soc/intel/cannonlake: Enable S4 sleep state supportpraveen hodagatta pranesh
Add ACPI entry in sleepstates.asl to support S4 (hibernate). TEST: boot to Windows on CFL RVP11 & RVP8, verified hibernate functionality. Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-25soc/amd/common/pi: Correct top of DRAM reporting by AGESAMarshall Dawson
Accurately reflect the intention of the syslimit value returned from AmdInitPost(). Assume FFs for the non-present bits. BUG=b:118178425 TEST=Boot Grunt and verify reported value = TOM2-1. Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-24mediatek/mt8183: Initialize DRAM with a sequence in constant arrayHuayang Duan
The DRAM init sequence is simply setting some values on register for all DRAM modules, no logic involved; so we can replace it by an array to configure easily. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Iacd3ce909ba7a0bdf699c5bfcb2b97f383d7bb6f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-24vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logicJoel Kitching
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23soc/amd/stoneyridge: Remove smbus.aslRichard Spiegel
The file smbus.asl has 0 bytes (no content). Now that it's no longer included, remove it. BUG=b:117814641 TEST=Build grunt and gardenia. Change-Id: I66389c721e272053d86357f71a6d1242ca767edd Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-23soc/intel/common/block/gpio: Allow GPI to be dual-routedFurquan Shaikh
This change adds new macros to GPIO common library helpers to allow a GPI pad to be dual routed using PAD_CFG_GPI_DUAL_ROUTE. It also adds a helper macro to configure a pad for IRQ and wake. Above macros are guarded using a newly added Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT that is selected only by SoCs that have been validated to allow dual route of GPIs. Currently, this config is selected only for APL/GLK/SKL/KBL that have been validated to work with dual-routing of GPIs for IRQ and wake. BUG=b:117553222 Change-Id: Iaa623d2d78a50f1504e3abe9a47a5a663693aead Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29188 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23soc/intel/common/block/gpio: Configure Tx Disable in IO standby for GPIsFurquan Shaikh
This change updates various PAD_CFG_GPI* macros to configure Tx as Disabled in IO Standby state. This is done to ensure that the Tx setting is same in IO Standby state as it was in active state i.e. Tx disabled. BUG=b:17553222 Change-Id: If462aee3884cc61a519fb358b84867c695ace251 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-23soc/intel/apollolake: Add reset code to postcar stagePatrick Georgi
Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22intel: Use CF9 reset (part 2)Patrick Rudolph
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22soc/amd: Implement common reset APINico Huber
Add an `amdblocks` internal API and rename soft_reset() => warm_reset() hard_reset() => cold_reset() as these terms are commonly used in the surrounding code. On Stoney Ridge, make board_reset() call cold_reset() to keep current behaviour of common code calling hard_reset(). But add a TODO if this is intended. Note: Stoney Ridge is using CF9 for the actual reset but the configuration for a cold reset doesn't use the usual full reset bit but some other mechanism. Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-22soc/samsung/exynos5250: Convert to `board_reset()`Nico Huber
Change-Id: I2f69d9f01ac5f7e28dd98e704f3280bf62b9ce58 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22soc/mediatek: Convert to `board_reset()`Nico Huber
Note, MT8183 didn't select HAVE_HARD_RESET before. So it might still need an update. Change-Id: Ic850f2775ada5e6e543ffb92aaa033b9209596f5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22soc/imgtech/pistachio: Convert to `board_reset()`Nico Huber
Change-Id: If8fc29c46e2cbc69f94ea8b6dc414a93d82ffb28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22soc/rockchip/rk3399: Convert to `board_reset()`Nico Huber
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22reset: Convert individual boards to `board_reset()`Nico Huber
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-19soc/lowrisc: Remove the remains of a LowRISC socPeter Lemenkov
Looks like we've got a race condition between commit ce8763fb with Change-Id I4e3e715106a1a94381a563dc4a56781c35883c2d ("mb/lowrisc: Remove the Nexys4DDR port") and commit 2e38dbe5 with Change-Id I5524732f6eb3841e43afd176644119b03b5e5e27 ("riscv: update mtime initialization"). Let's fix it. Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29165 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-19soc/intel/cannonlake: Enable HDA driver supportpraveen hodagatta pranesh
This patch selects common HDA driver and adds audio controller device id to enable audio on coffee lake platforms. BUG= None TEST= boot to yocto linux and windows os on CFL RVP11 & RVP8, verified audio functionalities. Change-Id: I4a60a4d7d8babcd0c14664a304ca81d47c668a6c Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29145 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18mediatek/mt8183: Add EMI init for DDR driver initHuayang Duan
Add EMI config to initialize memory. BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea Reviewed-on: https://review.coreboot.org/28835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18mediatek/mt8183: Add register definitions of DRAM controllerTristan Shieh
Add register definitions of DRAM controller. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I8b51486deab856a783b87f0b2812a991d4111020 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40Richard Spiegel
Register 0x40 of miscellaneous MMIO is double defined, with different names, which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO registers. BUG=b:117818431 TEST=Build grunt. Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIGRichard Spiegel
SPI100_SPEED_CONFIG is double defined. Bits and shift definitions on the first definition are unused. Remove first definition and its associated bits and shifts. BUG=b:117818430 TEST=Build grunt. Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-18soc/amd/stoneyridge: Remove double definition for wideioRichard Spiegel
WIDEIO_RANGE_ERROR and TOTAL_WIDEIO_PORTS are defined twice. Remove the definitions within MMIO definitions, as wideio is not related to MMIO. BUG=b:117814228 TEST=Build grunt. Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove DEV_D18F4 definitionRichard Spiegel
The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is the same as SOC_PM_DEV. Remove the definition, and replace its use in tsc_freq.c with SOC_PM_DEV. BUG=b:117754424 TEST=Build and boot grunt. Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove double defined GPIO MMIO basesRichard Spiegel
GPIO control a mux base addresses are defined within MMIO definitions and again bellow as GPIO specific base addresses. Eliminate those outside MMIO bases. Rename them to something indicating that they are both MMIO and related to GPIO. BUG=b:117754420 TEST=Build grunt. Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29156 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18amd/stoneyridge/include/soc: Re-arrange NB IOAPIC definitionsRichard Spiegel
There's no indication that they are accessed through D0F0. Add a D0F0 header and move IOAPIC definitions under it. The registers defined to be accessed through index/data pair should be indented relative to the index/data pair definition. BUG=b:117754786 TEST=Build grunt. Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29155 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge/smi.c: Prefer using '"%s...", __func__'Richard Spiegel
In function smm_setup_structures(), the function name is used in a print string. Use __func__ instead. BUG=b:117642170 TEST=Build grunt. Change-Id: Icac5ea997289ef75fb246a09715cbca4442a57f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29154 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge/southbridge.c: Change comparison orderRichard Spiegel
Comparison should place the constant on the right side. Southbridge.c has 6 instances where the opposite happens. Reverse the order of six comparisons to eliminate checkpatch warnings: WARNING: Comparisons should place the constant on the right side of the test BUG=b:117656929 TEST=Build grunt. Change-Id: I94f17b81f845fa94599f93c0be1144ffcb8e4165 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29153 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge: Remove "else" after a returnRichard Spiegel
File smbus_spd.c has 2 instances of if()/else where the if tests for an error condition and returns just before the "else" statement. These "else" statements are not needed. BUG=b:117648025 TEST=Build and boot grunt. Change-Id: Ie8298773ae455dbb1125420ec65df24f3c65eb44 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18intel/common/block: Fix issue found by klockworkJohn Zhao
src/soc/intel/common/block/pmc/pmclib.c Function acpi_get_sleep_type: Pointer ps checked for NULL may be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I15fe39fd9f930be56d03c2ffe62fb6f17249d4b5 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-18soc/intel/skylake: Prevent disabling of TCONaresh G Solanki
In Skylake/Kabylake, if ACPI PM timer is disabled then TCO also gets disabled & vice versa. FSP default config for EnableTcoTimer is disabled, this caused ACPI PM timer & TCO to be disabled by FSP even when config PmTimerDisable = 0. Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config PmTimerDisable. BUG=None TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused reboot after running shell command: cat >> /dev/watchdog0 Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/29108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake RVP8 platforms. - Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB, SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device. - Add new device IDs to intel common code respectively. - Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8. - CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c is modified accordingly. - Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8. BUG=None TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices are enumerated and cross checked devices ids in serial logs and UEFI shell. Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28718 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 15:01:20 +0000