diff options
| author | Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-11-03 01:49:15 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-07 16:44:20 +0000 |
| commit | ccd174686ea4f5b814486fd10e55d879c1f07bdc (patch) | |
| tree | 7234f4b0cc898cddc6bfacd653036d955b242f9f /src/soc | |
| parent | bd48b235fce91c53267063d00b912f621052ce6a (diff) | |
soc/intel/skylake: Add FSP CAR support for kabylake
Kabylake RVP11 uses FSPT to support Intel security features like
bootguard verify boot and measured boot.
This patch add FSP CAR support for kabylake by programming tempraminit
parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is
selected in order to relocate FSPT binary while adding it in CBFS so that
it can be executed in place.
BUG=None
TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified
for successful FSP CAR setup.
Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/fspcar.c | 34 |
3 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 1449d3db3d..2db8217e75 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -77,6 +77,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC + select FSP_T_XIP if FSP_CAR config CPU_INTEL_NUM_FIT_ENTRIES int diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 21dc5a4746..480c71ecfb 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -11,6 +11,7 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c +bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += bootblock/cpu.c bootblock-y += i2c.c bootblock-y += bootblock/pch.c diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c new file mode 100644 index 0000000000..a4c3726492 --- /dev/null +++ b/src/soc/intel/skylake/fspcar.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <bootblock_common.h> +#include <FsptUpd.h> + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = 0x545F4450554C424B, /* 'KBLUPD_T' */ + .Revision = 1, + .Reserved = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = + (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionSize = + (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = + (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, + }, +}; |