diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-11-06 17:07:01 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-11-09 06:09:37 +0000 |
| commit | 2df5abc53bf670786a472c9c315adfc4e988cf2a (patch) | |
| tree | 90f08cbb8531cdd35046db5394f967487655022e /src/soc | |
| parent | 26072787e02da496f617bbc044e8f70d4282ce15 (diff) | |
mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT generation
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/icelake
Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/icelake/acpi/cnvi.asl | 32 | ||||
| -rw-r--r-- | src/soc/intel/icelake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 1 |
3 files changed, 1 insertions, 35 deletions
diff --git a/src/soc/intel/icelake/acpi/cnvi.asl b/src/soc/intel/icelake/acpi/cnvi.asl deleted file mode 100644 index 634c6090ad..0000000000 --- a/src/soc/intel/icelake/acpi/cnvi.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/pm.h> - -/* CNVi Controller 0:14.3 */ -Device (CNVI) { - Name(_ADR, 0x00140003) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Name (_PRW, Package() { PME_B0_EN_BIT, 3 }) - - Method (_STA, 0) - { - Return (0xF) - } -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ff323c40a3..5cdc940523 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -56,8 +56,5 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* CNVi */ -#include "cnvi.asl" - /* GBe 0:1f.6 */ #include "pch_glan.asl" diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index bd31946ba7..12daea50c6 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -20,6 +20,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/gpe.h> #include <soc/gpio.h> #include <soc/pch.h> #include <soc/gpio_defs.h> |