| Age | Commit message (Expand) | Author |
|---|
| 2021-01-28 | soc/mediatek/mt8192: Implement dram all channel calibration | Huayang Duan |
| 2021-01-28 | soc/mediatek/mt8192: Add mt6315_romstage_init | Yidi Lin |
| 2021-01-28 | soc/mediatek/mt8192: Add function to raise the CCI frequency | Weiyi Lu |
| 2021-01-28 | soc/intel/xeon_sp/skx: Add soc_acpi_name | Marc Jones |
| 2021-01-28 | ACPI: Separate ChromeOS NVS in ASL | Kyösti Mälkki |
| 2021-01-28 | ACPI: Declare GNVS variables globally | Kyösti Mälkki |
| 2021-01-28 | arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits | Kyösti Mälkki |
| 2021-01-28 | arch/x86: Top-align .init in bootblock | Kyösti Mälkki |
| 2021-01-28 | cpu/x86: Rename __protected_start symbol | Kyösti Mälkki |
| 2021-01-28 | soc/intel: Refactor acpi_wake_source() | Kyösti Mälkki |
| 2021-01-28 | soc/intel: Refactor fill_acpi_wake() | Kyösti Mälkki |
| 2021-01-28 | soc/amd/picasso/acpi: Fix PCI0 MMIO window | Raul E Rangel |
| 2021-01-28 | soc/amd/picasso: fix CBFS MCACHE on Zork | Kangheui Won |
| 2021-01-28 | soc/amd/picasso/acpi: Remove DMA addresses for UARTs | Raul E Rangel |
| 2021-01-28 | soc/amd/cezanne/chip: add empty SoC device operations | Felix Held |
| 2021-01-28 | soc/amd/cezanne: compress FSP binaries in CBFS | Felix Held |
| 2021-01-27 | soc/amd/picasso/chip: use switch/case statement in enable_dev() | Felix Held |
| 2021-01-27 | soc/amd/stoneyridge: Change set_sb_nvs_final() | Kyösti Mälkki |
| 2021-01-27 | soc/amd/cezanne: Add UCODE firmware to CBFS | Zheng Bao |
| 2021-01-27 | soc/amd/picasso: Remove the useless definition of UCODE_FILEs | Zheng Bao |
| 2021-01-27 | soc/amd: Throw an error if FWM_POSITION_INDEX is empty | Zheng Bao |
| 2021-01-27 | soc/intel/alderlake: Generate LP4x SPD files using gen_spd.go | Amanda Huang |
| 2021-01-27 | soc/amd/common: Only set write_acpi_tables if ACPI table is enabled | Zheng Bao |
| 2021-01-27 | sb,soc/amd: Rename PMOD to PICM in ASL | Kyösti Mälkki |
| 2021-01-27 | ACPI: Separate device_nvs_t | Kyösti Mälkki |
| 2021-01-27 | soc/amd/common: Notify SMU of AC/DC state upon resume | Marshall Dawson |
| 2021-01-27 | soc/amd/common/block/smbus: remove stale comment | Felix Held |
| 2021-01-26 | soc/intel/braswell/romstage/romstage.c: Use __func__ | Elyes HAOUAS |
| 2021-01-26 | soc/amd: Add an option to select if SOC supports ESPI sub decode | Zheng Bao |
| 2021-01-26 | soc/intel/xeon_sp/acpi.c: Add ACPI C-State table | Marc Jones |
| 2021-01-26 | soc/intel: Move c-state resource define | Marc Jones |
| 2021-01-26 | sb,soc/intel: Refactor power_on_after_fail option | Kyösti Mälkki |
| 2021-01-26 | soc/amd: Refactor some ACPI S3 calls | Kyösti Mälkki |
| 2021-01-25 | soc/amd/picasso: Change GPIO _HID to AMDI0030 | Raul E Rangel |
| 2021-01-25 | soc/amd/picasso/acpi: Change I2C _HID to AMDI0010 | Raul E Rangel |
| 2021-01-25 | soc/amd/picasso/acpi: Change UART _HID to AMDI0020 | Raul E Rangel |
| 2021-01-25 | soc/intel/denverton_ns: Drop unused `pattrs.h` | Angel Pons |
| 2021-01-25 | soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver | Furquan Shaikh |
| 2021-01-25 | soc/amd/picasso: Use makefile variable to locate UCODE | Zheng Bao |
| 2021-01-25 | soc/amd/common: Refactor ACPI wake source | Kyösti Mälkki |
| 2021-01-25 | soc/amd: Refactor ACPI power state and ELOG | Kyösti Mälkki |
| 2021-01-25 | sb,soc/intel: Remove no-op APMC for C-state and P-state | Kyösti Mälkki |
| 2021-01-25 | cpu/x86/smm: Use common APMC logging | Kyösti Mälkki |
| 2021-01-25 | soc/amd/picasso: Add UPDs for support eDP power sequence adjust | Chris Wang |
| 2021-01-25 | soc/amd/picasso: Set UPDs for tuning eDP phy | Chris Wang |
| 2021-01-25 | soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring | Michael Niewöhner |
| 2021-01-25 | soc/intel/lpc_lib: mirror LPC registers to DMI when required | Michael Niewöhner |
| 2021-01-25 | soc/intel/xeon_sp/cpx: Fix loading MCU on APs | Arthur Heymans |
| 2021-01-25 | soc/amd/common/acpi: Add _UID for PNP0C02 devices | Raul E Rangel |
| 2021-01-25 | soc/amd/picasso/acpi: Add UID for PCI INT devices | Raul E Rangel |
| 2021-01-25 | soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver | Furquan Shaikh |
| 2021-01-25 | soc/intel/common: Add support for populating meminit data | Furquan Shaikh |
| 2021-01-25 | soc/intel/tigerlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD | Bora Guvendik |
| 2021-01-24 | soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Drop enable check from LPD0/LPD3 | Angel Pons |
| 2021-01-24 | soc/intel/quark/gpio_i2c.c: Use __func__ | Elyes HAOUAS |
| 2021-01-24 | soc/intel/denverton_ns/pmc.c: Use __func__ | Elyes HAOUAS |
| 2021-01-24 | soc/intel/denverton_ns/npk.c: Use __func__ | Elyes HAOUAS |
| 2021-01-24 | soc/intel/denverton_ns/lpc.c: Use __func__ | Elyes HAOUAS |
| 2021-01-24 | soc/samsung/exynos5250/dp-reg.c: Use __func__ | Elyes HAOUAS |
| 2021-01-24 | soc/amd/cezanne/Kconfig: select missing SSE2 option | Felix Held |
| 2021-01-24 | soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRS | Felix Held |
| 2021-01-24 | soc/amd/cezanne: add basic romstage | Felix Held |
| 2021-01-24 | soc,vendorcode/amd/cezanne: add basic FSP integration | Felix Held |
| 2021-01-24 | soc/amd/picasso: Remove some empty strings | Zheng Bao |
| 2021-01-24 | soc/amd/cezanne: Add PSP integration for cezanne | Zheng Bao |
| 2021-01-24 | soc/intel/xeon_sp/cpx: Account for 'rc' heap manager | Arthur Heymans |
| 2021-01-24 | soc/intel/lpc_lib: drop dead code | Michael Niewöhner |
| 2021-01-24 | soc/intel/icl: drop wrong, unused code | Michael Niewöhner |
| 2021-01-24 | soc/intel/cnl: use Kconfig to determine PCH type | Michael Niewöhner |
| 2021-01-24 | soc/intel/broadwell: Align raminit with Haswell | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Drop `struct romstage_params` | Angel Pons |
| 2021-01-24 | broadwell: Flatten `mainboard_pre_raminit` | Angel Pons |
| 2021-01-24 | broadwell: Clean up `mainboard_post_raminit` | Angel Pons |
| 2021-01-24 | soc/intel/broadwell/chip.h: Drop unused fields | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Select CPU_INTEL_HASWELL | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Move romstage.c to Haswell | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Drop now-unused CPU code | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Use Haswell CPU headers | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Allow to use Haswell CPU code instead | Angel Pons |
| 2021-01-24 | soc/intel/broadwell: Select INTEL_LYNXPOINT_LP | Angel Pons |
| 2021-01-23 | soc/intel/baytrail,broadwell: Use bootstate for save_wake_source() | Kyösti Mälkki |
| 2021-01-23 | ACPI: Add helpers for CBMEM_ID_POWER_STATE | Kyösti Mälkki |
| 2021-01-23 | soc/amd: Rename chipset_state to chipset_power_state | Kyösti Mälkki |
| 2021-01-23 | intel/baytrail,braswell,broadwell: Add const qualifier for power_state | Kyösti Mälkki |
| 2021-01-23 | ELOG: Add const qualifier for chipset_power_state | Kyösti Mälkki |
| 2021-01-23 | soc/amd/picasso/pcie_gpp: Remove duplication in pirq_data declaration | Raul E Rangel |
| 2021-01-23 | soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array | Raul E Rangel |
| 2021-01-23 | soc/amd/picasso/pcie_gpp: Add clarifying comment | Raul E Rangel |
| 2021-01-23 | soc/amd/picasso/acpi: Remove dummy AOAC parent device | Raul E Rangel |
| 2021-01-23 | soc/intel/cometlake: Add ucode for CML-H | Tim Crawford |
| 2021-01-23 | soc/intel/apl: drop LPC pad configuration code | Michael Niewöhner |
| 2021-01-22 | soc/amd/cezanne: add pci_devs.h | Felix Held |
| 2021-01-22 | soc/intel/alderlake: Adding Kconfig for ADL_M PCH | Varshit Pandya |
| 2021-01-22 | soc/intel/commmon: Include Alder Lake device IDs | Varshit Pandya |
| 2021-01-22 | soc/mediatek/mt8192: pmic: Set efuses manually | Hsin-Hsiung Wang |
| 2021-01-22 | soc/mediatek/mt8183: Fix pq module size config | Yu-Ping Wu |
| 2021-01-22 | soc/amd/common/block/smbus: always return SMBus MMIO in get_sm_mmio | Felix Held |
| 2021-01-22 | soc/intel/baytrail,broadwell: Refactor acpi_wake_source() | Kyösti Mälkki |
| 2021-01-21 | soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16 | Felix Held |
