diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-21 16:16:58 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-23 20:32:01 +0000 |
commit | d4b58259c4ecb0e68586282b5cde194f66de2bba (patch) | |
tree | 79b6db3ba190749f143bbcf4d79730f399ca674e /src/soc | |
parent | 2787237dd52550b5d7e1dc3dabcf380126ff804c (diff) |
soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()
Change-Id: I01be1b9dfefcfcf037de4153e9540c7258dc160f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49818
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 28 | ||||
-rw-r--r-- | src/soc/intel/broadwell/ramstage.c | 26 |
2 files changed, 34 insertions, 20 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 0c955e3073..f1401e2411 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpi_pm.h> +#include <bootstate.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -117,15 +118,9 @@ static void fill_in_pattrs(void) } /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void save_acpi_wake_source(void) +static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) { - struct chipset_power_state *ps = acpi_get_pm_state(); - struct global_nvs *gnvs = acpi_get_gnvs(); uint16_t pm1; - - if (!ps || !gnvs) - return; - pm1 = ps->pm1_sts & ps->pm1_en; /* Scan for first set bit in PM1 */ @@ -143,6 +138,21 @@ static void save_acpi_wake_source(void) gnvs->pm1i); } +static void acpi_save_wake_source(void *unused) +{ + const struct chipset_power_state *ps; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; + + if (acpi_pm_state_for_wake(&ps) < 0) + return; + + pm_fill_gnvs(gnvs, ps); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); + static void baytrail_enable_2x_refresh_rate(void) { u32 reg; @@ -164,10 +174,6 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); - /* Indicate S3 resume to rest of ramstage. */ - if (acpi_is_wakeup_s3()) - save_acpi_wake_source(); - /* Run reference code. */ baytrail_run_reference_code(); diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 93bc01dda0..0078939145 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpi_pm.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <string.h> @@ -12,16 +13,11 @@ #include <soc/intel/broadwell/chip.h> /* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ -static void save_acpi_wake_source(void) +static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) { - struct chipset_power_state *ps = acpi_get_pm_state(); - struct global_nvs *gnvs = acpi_get_gnvs(); uint16_t pm1; int gpe_reg; - if (!ps || !gnvs) - return; - pm1 = ps->pm1_sts & ps->pm1_en; /* Scan for first set bit in PM1 */ @@ -63,10 +59,22 @@ static void save_acpi_wake_source(void) gnvs->pm1i, gnvs->gpei); } -void broadwell_init_pre_device(void *chip_info) +static void acpi_save_wake_source(void *unused) { - if (acpi_is_wakeup_s3()) - save_acpi_wake_source(); + const struct chipset_power_state *ps; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; + if (acpi_pm_state_for_wake(&ps) < 0) + return; + + pm_fill_gnvs(gnvs, ps); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); + +void broadwell_init_pre_device(void *chip_info) +{ broadwell_run_reference_code(); } |