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2024-09-12soc/mediatek: Remove redundant struct pad_func and PAD_* definitionsYidi Lin
Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch also refactors the PAD_* macros by, - Repurposing PAD_FUNC and dropping PAD_FUNC_SEL. - Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit initialization. BUG=none TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09soc/mediatek/common: Move common GPIO definitions to gpio_defs.hYidi Lin
BUG=none TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24soc/mediatek: Refactor MMU operation for L2C SRAM and DMAJarried Lin
Refactor mmu operation by - moving mtk_soc_disable_l2c_sram to l2c_ops.c - keeping mtk_soc_after_dram in mmu_cmops.c Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24soc/mediatek: Require MCU and DRAM blobs to existYu-Ping Wu
When the config of MCU firmware blob such as CONFIG_SPM_FIRMWARE is non-empty, we should always expect the file to exist. Similarly, since the device is unlikely to boot without the DRAM blob (assuming MRC_CACHE doesn't contain valid memory training data), dram.elf should always exist as well. Therefore, remove the check for the existence of the blobs. Build would fail if any of the blobs is missing. Change-Id: I755e7c5a70b34b0c3d3915ab339c65263688aad7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84053 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23soc/mediatek/common: Move GPIO definition to the common directoryJarried Lin
To reduce duplicate gpio_base.h in each SoC folder, move gpio_base.h to mediatek/common folder. TEST=Build pass BUG=b:317009620 Change-Id: I815df8a3083cf04b821165ec834ca98ee71a0c78 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-10soc/mediatek/common: Refactor EINT driverYidi Lin
Refactor EINT driver by - Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to `gpio_calc_eint_pos_bit`. - Implement `gpio_get_eint_reg` to obtain EINT base address. This change is prepared for the driver change in MT8196. BUG=b:334723688 TEST=EINT works on Geralt Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START commentYu-Ping Wu
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-22soc/mediatek: Move memmory macros into MediaTek common directoryJarried Lin
To reduce duplicate memmory macros of MediaTek SoCs, move the header file to a common directory. TEST=Build geralt pass BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/mediatek: Move symbols.h into MediaTek common directoryJarried Lin
To reduce duplicate region declarations of MediaTek SoCs, move the header file to a common directory. BUG=b:317009620 TEST=Build geralt pass. Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83570 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/mediatek/mt8188: Respect ARM64_BL31_OPTEE_WITH_SMC optionYu-Ping Wu
Since BL31_MAKEARGS is already handled in arm64/Makefile.mk, remove the duplication from mt8188/Makefile.mk. In addition, reserve the memory range for running OP-TEE only if ARM64_BL31_OPTEE_WITH_SMC is enabled. BUG=b:347851571 TEST=emerge-geralt coreboot BRANCH=geralt Change-Id: I88a9a07a685a6c9fe9739b6101ccb8a5ce23fd8b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-05-29tree: Remove unused <stddef.h>Elyes Haouas
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-28soc/mediatek/mt8188: Decrease OP-TEE image size from 80 MB to 70 MBGavin Liu
The secure buffer shrank from 42 MB to 32 MB, decreasing the total OP-TEE image size from 80 MB to 70 MB. BUG=b:246837563 TEST=emerge-geralt coreboot build coreboot and verify SVP works well Change-Id: I6729e65f83ef994fe59b5bd4ed098e6d3a847695 Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-05-09soc/mediatek/mt8188: devapc: set devapc permission for MFGFei Yan
In order to support SVP Feature, EMI-MPU has to give MFG permissions to allow MFG to access secure buffer by secure read and write. Currently MFG is in domain 0, which include many other masters. Move MFG to domain 6. Set MFG remap, so that MFG can switch to protect mode by MFG register. Change MFG permission from NO_PROTECTION to SEC_RW_ONLY for domain 0, so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5. BUG=b:313855815 TEST=emerge-geralt coreboot Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d Signed-off-by: Fei Yan <fei.yan@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28soc/mediatek: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-26soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptiveYidi Lin
Starting from MT8195, MediaTek platform supports "dram adaptive" to automatically detect dram information, including channel, rank, die size..., and can automatically configure EMI settings. So we can just pass a placeholder param blob to `mt_mem_init_run` by enabling this option. Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive" need to implement `get_sdram_config` to get onboard DRAM configuration info. TEST=emerge-geralt coreboot && emerge-asurada coreboot TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMCYi Chou
BUG=b:248612503 TEST=Test with crrev.com/c/4756330 BRANCH=none Signed-off-by: Yi Chou <yich@google.com> Change-Id: I3dded9042abd85a948598f98475c21a1af9b4d80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80315 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24soc/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17soc/mediatek/mt8188: Enable EARLY_MMU_INITYidi Lin
The boot time is improved by 65ms. (762ms -> 697ms) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I74191ab8cbefa08b7e296312645ea40b46fabf77 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79991 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/mediatek: Add EARLY_MMU_INIT kconfig optionYidi Lin
Accessing RAM before mmu initialized is time consuming. During mmu initialization, `mmu_init()` and `mmu_config_range()` write logs to the console buffer and contribue the extra boot time. This patch adds a kconfig option to move `mtk_mmu_init()` to `bootblock_soc_early_init()`. When `EARLY_MMU_INIT` is enabled, mmu is initialized before `console_init()` ready. So `mmu_init()` and `mmu_config_range()` won't write logs to the console buffer and save the boot time. It saves about 65ms on Geralt with EARLY_MMU_INIT enabled. Before: 0:1st timestamp 239,841 (0) 11:start of bootblock 239,920 (79) 12:end of bootblock 323,191 (83,271) After: 0:1st timestamp 239,804 (0) 11:start of bootblock 239,884 (80) 12:end of bootblock 258,846 (18,962) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I7f4c3c6c836f7276119698c6de362794cf4222a6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-10soc/mediatek: Add common implementation to configure displayYidi Lin
The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on() - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to mediatek/common/display.c and refactors `struct panel_description` to generalize the display init sequences. configure_display() is also renamed to mtk_display_init(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_SNina Wu
Update BND_NORTH_APB2_S's domain 5 permission to allow the access from APU. The APU requires certain information saved in BND_NORTH_APB2_S for voltage tuning. If this information cannot be retrieved, the APU may operate at a high frequency with low voltage. Consequently, the APU may not function as expected. Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79348 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01soc/mediatek/mt8188: Support loading OP-TEE via an SMCkiwi liu
This patch adds compilation flags to BL31 to support loading OP-TEE via an SMC from rootfs. This patch also reserves 80MB memory space for running the OP-TEE image. BUG=b:246837563 TEST=emerge-geralt coreboot Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9 Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78801 Reviewed-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-11memlayout.ld: Increase RAMSTAGE size to more than 1MB everywherePatrick Georgi
This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-02soc/mediatek/mt8188: devapc: Add SCP domain settingJason Chen
Configure the SCP to operate within domain 8, allowing it to access only the necessary registers. Any unauthorized access will be prevented by the DAPC. - Set SCP domain from domain 0 to domain 8. - Lock register settings down to prevent unexpected modification. BUG=b:270657858 TEST=scp bootup successful with dapc settings Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77883 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-02soc/mediatek/mt8188: devapc: Set master domainsNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch sets domains for masters: SSPM - domain 3 CPUEB - domain 14 PCIE0 - domain 2 SPM - domain 9 Change-Id: Ie3e1d5055e72824257b66d6257982652eeb05953 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77862 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/mediatek/mt8188: devapc: Update permission for master domain setupNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch updates the permission settings for domains 2, 3, 4, 5, 7, 8, 9, and 14, as these domains will be assigned masters in the upcoming patch. BUG=b:270657858 TEST=build pass Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77861 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-22soc/mediatek: Move common devapc definitions to common/Nina Wu
Move following definitions to common/ 1) the definition of the bit fields for domain remap 2) the definition of the structure for the permission of all domains Change-Id: Iac84ebc908ae384a6280388af4120f6349a32ed4 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77860 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24soc/mediatek/mt8188: Remove GPT timer initYidi Lin
GPT timer init is no longer needed after DRAM blob is switching to ARM arch timer. BUG=b:229800119 TEST=boot to kernel Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-23soc/mediatek/mt8188: Simplify pmif init flowSen Chu
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx", MT8188G used in ChromeOS project does not support clock hardware monitor. Thus, we can simplify the initialization flow by removing the hardware default value check. BUG=b:292866009 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-06soc/mediatek/mt8188: Support ARM arch timerYidi Lin
Use ARM architectual timer by initializing frequency to 13 MHz. Since system timer is the source of the architectual timer, we also call `timer_prepare` in `init_timer`. BUG=b:229800119 TEST=run `suite:faft_bios` to verify the firmware stability. check timestamps by cbmem. Cq-Depend: chromium:4747539 Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/mt8188: Support 4K resolution displayHsiao Chien Sung
The original clock rate 416MHz is insufficient for 4K resolution and causing the screen to glitch. Set the clock rate to 594MHz to support 4K resolution. BUG=b:236328487 TEST=Glitching screen was fixed after applying this patch Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3 Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/geralt: Fix MIPI panel power on/off sequenceRuihai Zhou
Based on the power sequence of the panel [1], the power on T2 sequence VSP to VSN should be larger than 1ms, and the power off T2 sequence VSP to VSN should be larger than 0ms. We modify the power sequence to meet the datasheet requirement. [1] B5 TV110C9M-LL0 Product Specification Rev.P0 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-04-10soc/mediatek/mt8188: Set pin drive strength to 8mA for NORJason Chen
Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.8 and 5.19 in MT8188 Functional Specification. BUG=b:270911452 TEST=boot with following logs [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74064 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Add GPIO driving functionsJason Chen
Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74063 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Move GPIO driving-related functions to commonJason Chen
Move GPIO driving-related functions to common for code reuse. BUG=b:270911452 TEST=build pass Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74068 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytesYidi Lin
Original lastbus configuration consumes constant memory size by allocating 16 and 8 members arrays and the utilization is bad. Refactor the lastbus structs to save memory usage. BRANCH=none BUG=none TEST=bootblock.raw.bin size is reduced from 60328 bytes to 59048 bytes. Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74061 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/mediatek/mt8188: Shut down PMIC on power key long pressSen Chu
Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse Change-Id: I1626892fd582dfab8fe1c1ede1da00549bc97142 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73704 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-10soc/mediatek/mt8188: Enable lastbus debug hardwareot_zhenguo.li
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. There are two versions for lastbus: Version 1 for MT8186, and version 2 for MT8188. BUG=b:263753374 TEST=build pass. Change-Id: Ibaf510481d1941376bd8da0168ef17c99a0fb9a2 Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73624 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add MAX98390 support for GeraltTrevor Wu
Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05soc/mediatek/mt8188: Add bus protection for audio/video mtcmosgarmin chang
Bus protection is a HW mechanism to avoid bus hang and incomplete bus transactions. Bus protection HW must be enabled while the receiver of the transaction is not able to respond. BUG=b:264204465 TEST=build pass Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Signed-off-by: garmin chang <garmin.chang@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73375 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23soc/mediatek: Add "DRAM" to Kconfig MEDIATEK_BLOB_FAST_INIT nameYu-Ping Wu
In the current Kconfig option MEDIATEK_BLOB_FAST_INIT, the meaning of "BLOB" is unclear. Add "DRAM" to the name. BUG=b:204226005 TEST=./util/abuild/abuild -t GOOGLE_STEELIX -x Change-Id: Ida7bda770f1d1a40cae205b08c8cb22f2329e49f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73155 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-22soc/mediatek/mt8188: Fix audio sampling rateJohnson Wang
The current clock register definition is wrong, which results in wrong audio sampling rate. Fix it by adjusting the POSTDIV registers of APLL1-APLL5. TEST=build pass BUG=b:250459803, b:250464574 Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0 Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-22soc/mediatek/mt8188: Fix USB2 detection issueShaocheng Wang
MT8188 supports port0/port1 download. The hardware needs a trapping pin to select the port to use. When port1 is selected, the phy of port1 will be switched to port0. That is, port1 connector will be the physical line of port0. Since port0 phy isn't initialized in coreboot, switch back to port1 phy. BUG=b:269059211 TEST=can detect USB2 devices in depthcharge. Change-Id: Ic97d0bd9d0233883196b2e73ac2a22cd8ea9466b Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-09mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0Rex-BC Chen
For Geralt, we use BOE_TV110C9M_LL0 as MIPI firmware display, so add the power-on sequence for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72749 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-09mb/google/geralt: Init MT6359P only once in ramstageLiju-Clr Chen
The regulator MT6359P is needed by both firmware display and SD card. To avoid duplicate initialization in ramstage, publicize init_pmif_arb() as mt6359p_init_pmif_arb() and call it from mainboard_init(). This would save 13 ms for boot time on Geralt. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72839 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-02soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUSLiju-Clr Chen
USB1_DRV_VBUS is used to provide 5V power for USB on MT8188 EVB and it's not used on Geralt. Therefore, remove the GPIO setting of USB1_DRV_VBUS. TEST=read usb data successfully. BUG=b:236331724 Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72641 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19soc/mediatek/mt8188: Allow SSPM to access PWRAP interfaceSen Chu
Allow SSPM to access PWRAP interface. BUG=b:254566089 TEST=build pass and boot to OS. Change-Id: I4b134983dcde1cc293f4b798f91b997baf96d299 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-01-13soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-22soc/mediatek: Move dapc_init to commonYidi Lin
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this function to common/devapc.c TEST=emerge-corsola coreboot; emerge-cherry coreboot; emerge-geralt coreboot TEST=devapc log is shown as expected and the system boots to kernel Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-12mb/google/geralt: Put MIPI panel data in panel_geralt.cBo-Chen Chen
There are eDP and MIPI panels supported in geralt. We put the panels' specified functions - `power_on()` and `configure_panel_backlight()` in panel_geralt.c. Also provide the common interface `get_active_panel()` in panel.c to generalize the display initialization. Since each board may support a different set of MIPI panels, we put the MIPI data in a separate file panel_geralt.c. BUG=b:244208960 TEST=emerge-geralt coreboot Change-Id: Ie928759e020a916f29f0364201a3cf202dc512c3 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-05soc/mediatek/mt8188: Add support for MIPI panelBo-Chen Chen
We need to add DSI and MIPI_TX settings to support MIPI panel. BUG=b:244208960 TEST=emerge-geralt coreboot Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70184 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/mediatek/mt8188: Add display data path for MIPI outputBo-Chen Chen
For geralt project, we also support MIPI panel as our firmware display. So add this patch to configure ddp to choose eDP display or MIPI panel display. BUG=b:244208960 TEST=test firmware display pass for both eDP and MIPI panel on MT8188 EVB. Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18soc/mediatek/mt8188: Enable and initialize EINTJohnson Wang
Issue: Device can't wake up using power key. Root cause and solution: EINT event mask register is used to mask EINT wakeup sources. All wakeup sources are masked by default. So we add a driver here to unmask all wakeup sources. BUG=none TEST=wake the device up by power key on MT8188 EVB. Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69688 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-15mb/google/geralt: Enable RTC for eventlog timestampsLiju-Clr Chen
Without RTC, the timestamps in the eventlog are currently all '2000-00-00 00:00:00'. Enable RTC to get the correct timestamps. localhost ~ # head /var/log/eventlog.txt 0 | 2022-10-15 22:59:38 | Log area cleared | 4088 1 | 2022-10-15 22:59:38 | Memory Cache Update | Normal | Success 2 | 2022-10-15 22:59:45 | System boot | 0 3 | 2022-10-15 22:59:46 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown localhost ~ # localhost ~ # date Sun Oct 16 01:42:59 PDT 2022 localhost ~ # BUG=b:233720142 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69432 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/mediatek/mt8188: Disable input-gating for big-core SRAMLiju-Clr Chen
The input-gating is an experimental feature (but unfortunately default enabled) and would lead to crash on MT8188, so we have to disable it in the firmware stage. BUG=b:233720142 TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69089 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driverLiju-Clr Chen
When enabling cpufreq-hw driver, it is required for MCUPM to access secure registers. Therefore, we enable side-band to allow MCUPM to access the secure registers. BUG=b:236331463 TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-11-04Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers"Liju-Clr Chen
This reverts commit a8172c329fe309f3b5b409c1a59a227186400dd4. In the aforementioned patch, we allowed MCUPM to access secure registers and set the domain to DOMAIN_2. Additional attribute settings are also required when a hardware is set to a specific domain. Otherwise, there would be violation between hardware. Since MT8188 is in bring-up stage, we simply enable access register permission for the DOMAIN_0 by default. So remove the wrong setting for MCUPM, SCP and SSPM. We will complete DEVAPC setting when the settings are confirmed. Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-25soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITRex-BC Chen
For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so replace "GPL-2.0-only" with "GPL-2.0-only OR MIT". Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/mediatek/mt8188: Update mtcmos settings for display and audioBo-Chen Chen
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are required. - For audio, it requires powering on adsp_ao_pwr_con, adsp_infra_pwr_con and audio_pwr_con. - Add new power domain data `ext_buck_iso_bits` for buck isolation control. BUG=b:244208960 TEST=access display registers successfully. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25soc/mediatek/mt8188: Add eDP support for firmware displayBo-Chen Chen
MT8188 supports eDP as internal display interface. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25soc/mediatek/mt8188: Add ddp driver to support eDP outputNathan Lu
Add DDP (display data path) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings to MT8188 to support multi-layer display. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Nathan Lu <nathan.lu@mediatek.com> Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68487 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/mediatek/mt8188: Rename SPM registerBo-Chen Chen
The SPM register at offset 0x0 is often named as poweron_config_set in previous MediaTek SoCs. To use common driver, we rename it from poweron_config_en to poweron_config_set. BUG=none TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek: Unify PLL function namesRex-BC Chen
For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek: Move SPMI interface configuration to SoC folderSen Chu
The SPMI interface configuration is SoC-dependent. - MT8192 and MT8195 are the same. - MT8186 does not need to implement this. - MT8188 is different from MT8195, and we will submit another patch to fix this. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registersLiju-Clr Chen
This patch fixes AP hanging issue caused by the handshaking between MCUPM and CPUfreq driver. CPUfreq hardware failed to read MCUPM registers due to DEVAPC permission. Therefore, update the DEVAPC settings to fix this issue. BUG=none TEST=CPUfreq in kernel test pass. Change-Id: I6b30b01fc0be052182599709cbcc9139e6d09742 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67724 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Set PLLs to hardware default valuesGarmin Chang
Some PLLs are not used in firmware, so we should keep them as hardware default values. If their modules want to set them, the corresponding drivers should set them in the kernel stage. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9bee18005ffed7fc1785c7fd3c0370c8293064ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/67547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Fix indention in pll.cGarmin.Chang
BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I567d1ded1c3b5e36a25026cec697d43d92d5524c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67546 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Change vpp_sel default mux for 4k supportGarmin Chang
vpp_sel and ethdr_sel are vdosys clock source select mux. Steps to change to support 4K source: 1. Change vpp_sel source to mainpll_d6 to run at 416MHz. 2. Change ethdr_sel source to univpll_d6 to run at 416MHz. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I24f133b9b383fd019983cb29a213b47717148e97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67545 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Fix some wrong settings for PLLsGarmin Chang
The observed CPU big core frequency is double compared with the current PLL setting. Therefore fix the wrong setting for PLL register APMIXED_ARMPLL_BL. Moreover, we also fix some wrong settings for other PLLs. TEST=CPU frequency of big core CPU is correct and bootup correctly. BUG=b:244215537 Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9126f439d7a5136b2fb8d66f103ef427a0b08a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67543 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08soc/mediatek/mt8188: Enable ARM Trusted Firmware integrationRex-BC Chen
Enable configuration to build with MT8186 arm-trusted-firmware drivers. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id16405c84f6e0a2e21f95cc45babf85bd980b43e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67356 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/google/geralt: Pass reset gpio parameter to BL31Bo-Chen Chen
Pass the reset gpio parameter to BL31 to support SoC reset. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifdfbd6bd82f64b084f6349cb617443053c89a3f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67357 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxesJohnson Wang
Some of the pll settings are incorrect, which cause problems in GPU after booting into kernel. - MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix it to enable MFGPLL properly. - Switch SPMI clock muxes to 260M to avoid kernel hang while probing SPMI kernel driver. TEST=GPU bringup correctly. BUG=b:233720142 Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-08-31soc/mediatek/mt8188: Add SPM loader and initialize SPM in RAM stageRex-BC Chen
Add support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. SPM is an essential component on MediaTek SoC, so we initialize PPM in soc_init(). For MT8188, SPM will handshake with DPM to do initialization, so we need to call spm_init() after dpm_init(). This SPM flow adds 33ms to the boot time. firmware log: mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 25 msecs SPM: spm_init done in 33 msecs, spm pc = 0x400 TEST=spm pc is 0x400 which is in idle state. BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I1a1f49383e0ceadc259a18272fc1c277b65406ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/66973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek/mt8188: Use MHz as unit for current_clkBo-Chen Chen
The unit of current_clk in pmif_ulposc_check() should be MHz. We use pmif_get_ulposc_freq_mhz() to get the default hardware value in MHz. Without this modification, the judgement in pmif_ulposc_check() is alway wrong due to the wrong unit. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3bf80a23bb35ff657023eb4b7e009fa233f61244 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek/mt8188: Add DEVAPC basic driverNina Wu
Add basic DEVAPC (device access permission control) driver. DEVAPC driver is used to set up bus fabric security and data protection among hardwares. DEVAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DEVAPC driver. 1. Initialize DEVAPC. 2. Set master domain and secure side band. 3. Set default permission. TEST=check logs of DEVAPC ok. BUG=b:236331724 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Change-Id: Iad3569bc6f8ba032d478934ba839dc4b5387bafc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek/mt8188: Initialize DPM in ramstageXi Chen
Add initialization of DPM drvier for DRAM low power mode. DPM is an essential component on MediaTek SoC, so we initialize DPM in soc_init(). This DPM flow adds 22ms to the boot time. coreboot logs: CBFS: Found 'dpm.dm' @0x156c0 size 0xfc in mcache @0xfffdd110 mtk_init_mcu: Loaded (and reset) dpm.dm in 6 msecs (422 bytes) CBFS: Found 'dpm.pm' @0x15800 size 0x3c59 in mcache @0xfffdd140 mtk_init_mcu: Loaded (and reset) dpm.pm in 16 msecs (18910 bytes) TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I46baa7b49e90d53dd4d1d95af9c46622faf30419 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66969 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek/mt8188: Support 4 channel DRAM in DPM init flowXi Chen
TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: Ia68aca1d1e8729739246157904727123e5d001e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66968 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek/mt8188: Add DPM firmware filesXi Chen
DPM is a hardware module for DRAM power management, which is used for DRAM low power mode. TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I872396fe2c5accd92ba5c14b124125bd58257771 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66967 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27soc/mediatek/mt8188: Enable USE_CBMEM_DRAM_INFOXi Chen
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8188. Therefore, we select this configuration to enable it. TEST=build pass BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I14f3d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66280 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27soc/mediatek/mt8188: Add DRAM fast calibration supportXi Chen
Define fields of sdram_params and enable MEDIATEK_BLOB_FAST_INIT to run fast calibration for MT8188 using blob. DRAM fast calibration logs: DRAM-K: Fast calibration passed in 19530 msecs dram size (romstage): 0x200000000 TEST=Fast calibration pass. BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2468d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-27soc/mediatek/mt8188: Add DRAM full calibration supportXi Chen
- Use common SoC drivers for DRAM calibration support. - Remove emi.h because sdram_size() is already declared in common/include/soc/emi.h. - Add dramc_param.h and dramc_soc.h to prepare for implementation of DRAM full calibration. TEST=build pass BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2f88d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-13soc/mediatek/mt8188: Initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d19dc6f4e47ed69ba2ea87c79984020a413aee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66586 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Fix the order of register address in addressmap.hRex-BC Chen
TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ie9d7b361dda8c5850bc0682c255bc20f9e26675c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66668 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Add tracker dumpRex-BC Chen
Tracker is a debugging tool. When bus timeout occurs, the system will reboot and latch some values of tracker registers which could be used for debugging. This function will be triggered only when it encounters the bus hanging issue. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I78f676c08ea44e9bb10bd99bbfed70e3e8ece993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66584 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-13soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITMacpaul Lin
This replaces 'SPDX-License-Identifier' tags in all the files under soc/mediatek/mt8188 for better code re-use in other open source software stack. These files were originally from MediaTek and follow coreboot's main license: "GPL-2.0-only". Now MediaTek replaces these files to "GPL-2.0-only OR MIT" license. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Change-Id: If61e8b252400e8e5ecd185b6806b1ca279065f15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66628 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-07-29soc/mediatek/mt8188: Add SPI supportLiya Li
The gpios and the tick delay register are different between MT8188 and previous MediaTek SoCs, so we need to add this patch to support SPI. TEST=build pass BUG=b:236331724 Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com> Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek/mt8188: Add clk_buf support in romstageSong Fan
TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: Ic300b70a38ac204b098ca9ab15cf7045b66fd76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66182 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek/mt8188: Add RTC supportSong Fan
Add RTC header file for SoC-specific settings. Add RTC support in romstage. TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: I38115ce0c9a4e1c1b2b7c8e6d40f47e99f7f86b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66181 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek/mt8188: Add AUXADC supportHui Liu
TEST=get voltage as 340mV for channel 0 in MTK EVB. BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: Idd1edcce6cb62fcf6991bb9342c409150989c5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-26soc/mediatek/mt8188: Initialize SSPMRex-BC Chen
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 21 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x21680 size 0xa815 in mcache @0xffffeac4 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137348 bytes) TEST=we can see the sspm logs. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib6443b64734048c1d71eeac650f36d7c4ac709cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-26soc/mediatek/mt8188: Initialize MCUPMRex-BC Chen
Load MCUPM firmware and boot up MCUPM in ramstage. It takes 41 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x12580 size 0xf0c6 in mcache @0xffffead0 mtk_init_mcu: Loaded (and reset) mcupm.bin in 41 msecs (122184 bytes) TEST=we can see the mcupm logs after reset releases. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id1e62d9d6ede1c453e03eeda0d9b16fafa9e2372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-22soc/mediatek/mt8188: Add eMMC and SD card configurationsAndy-ld Lu
Geralt reference design has both eMMC and SD card interfaces, so we have to configure both in ramstage. Implement msdc.c (mass storage device class) to place the eMMC and SD card drivers. This implementation is based on chapter 5.9 in MT8188 Functional Specification. TEST=boot to kernel using emmc successfully. BUG=b:236331724 Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com> Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21soc/mediatek/mt8188: Add VMCH, VMC support for MT8188Hui Liu
For MT8188, we need to enable and adjust VMCH and VMC to support SD cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21soc/mediatek/mt8188: Add PMIF and PMIC init supportHui Liu
Add PMIF, SPI, SPMI and PMIC init code. These PMIC settings are used by MediaTek internally. We can find these registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and "MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek designers. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13soc/mediatek/mt8188: add usb host supportShaocheng Wang
Add usb host function support. TEST=read usb data successfully. BUG=b:236331724 Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Change-Id: I3494b687b811466cb6b988164d3c5b6fecc3016a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65754 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 18:46:00 +0000