soc/mediatek/mt8188: Add bus protection for audio/video mtcmos

Bus protection is a HW mechanism to avoid bus hang and incomplete bus
transactions. Bus protection HW must be enabled while the receiver of
the transaction is not able to respond.

BUG=b:264204465
TEST=build pass

Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1
Signed-off-by: garmin chang <garmin.chang@mediatek.corp-partner.google.com>
Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73375
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8188/mtcmos.c b/src/soc/mediatek/mt8188/mtcmos.c
index 3143b019f1..2339f37c98 100644
--- a/src/soc/mediatek/mt8188/mtcmos.c
+++ b/src/soc/mediatek/mt8188/mtcmos.c
@@ -5,7 +5,78 @@
 #include <soc/mtcmos.h>
 #include <soc/spm.h>
 
+enum {
+	VPPSYS0_PROT_STEP_6_MASK	= 0x00100000,
+	VPPSYS0_PROT_STEP_5_MASK	= 0x00276C16,
+	VPPSYS0_PROT_STEP_4_MASK	= 0x00800000,
+	VPPSYS0_PROT_STEP_3_MASK	= 0x00800200,
+	VPPSYS0_PROT_STEP_2_MASK	= 0x80302846,
+	VPPSYS0_PROT_STEP_1_MASK	= 0x00000400,
+	VDOSYS0_PROT_STEP_4_MASK	= 0x00000060,
+	VDOSYS0_PROT_STEP_3_MASK	= 0x00800000,
+	VDOSYS0_PROT_STEP_2_MASK	= 0x00000020,
+	VDOSYS0_PROT_STEP_1_MASK	= 0x00100000,
+	VPPSYS1_PROT_STEP_3_MASK	= 0x00040000,
+	VPPSYS1_PROT_STEP_2_MASK	= 0x00800000,
+	VPPSYS1_PROT_STEP_1_MASK	= 0x00000020,
+	VDOSYS1_PROT_STEP_3_MASK	= 0x00000400,
+	VDOSYS1_PROT_STEP_2_MASK	= 0x00400000,
+	VDOSYS1_PROT_STEP_1_MASK	= 0x40000000,
+	ADSP_PROT_STEP_2_MASK		= 0x00001000,
+	ADSP_PROT_STEP_1_MASK		= 0x00100000,
+	AUDIO_PROT_STEP_2_MASK		= 0x00600000,
+	AUDIO_PROT_STEP_1_MASK		= 0x00000F00,
+};
+
 void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd)
 {
 	clrbits32(&mtk_spm->ext_buck_iso, pd->ext_buck_iso_bits);
 }
+
+void mtcmos_protect_display_bus(void)
+{
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr,
+		VPPSYS0_PROT_STEP_6_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
+		VPPSYS0_PROT_STEP_5_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr,
+		VPPSYS0_PROT_STEP_4_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
+		VPPSYS0_PROT_STEP_3_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr,
+		VPPSYS0_PROT_STEP_2_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr,
+		VPPSYS0_PROT_STEP_1_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr,
+		VDOSYS0_PROT_STEP_4_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr,
+		VDOSYS0_PROT_STEP_3_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr,
+		VDOSYS0_PROT_STEP_2_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr,
+		VDOSYS0_PROT_STEP_1_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
+		VPPSYS1_PROT_STEP_3_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr,
+		VPPSYS1_PROT_STEP_2_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr,
+		VPPSYS1_PROT_STEP_1_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
+		VDOSYS1_PROT_STEP_3_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr,
+		VDOSYS1_PROT_STEP_2_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr,
+		VDOSYS1_PROT_STEP_1_MASK);
+}
+
+void mtcmos_protect_audio_bus(void)
+{
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2,
+		ADSP_PROT_STEP_2_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2,
+		ADSP_PROT_STEP_1_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2,
+		AUDIO_PROT_STEP_2_MASK);
+	write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2,
+		AUDIO_PROT_STEP_1_MASK);
+}