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2023-10-09soc/mediatek: PCI: Fix translation windowJianjun Wang
Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78044 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22soc/mediatek: Move common devapc definitions to common/Nina Wu
Move following definitions to common/ 1) the definition of the bit fields for domain remap 2) the definition of the structure for the permission of all domains Change-Id: Iac84ebc908ae384a6280388af4120f6349a32ed4 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77860 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14soc/mediatek/common/dsi: Add actual values to the log messagesRuihai Zhou
Per the suggestion in CB:76218, print actual values to the error messages, which may be helpful for debugging. Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Id3a7a8c76b6ad15e7cf71225d8529f3e034935ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/76442 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-10mb/google/corsola: Add support for AW37503 Power ICRuihai Zhou
The AW37503 is designed to supply positive/negative supply for driving the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we need to program the registers at boot. We program the target positive/negative output voltage via I2C and enable the power rails by pulling up ENP and ENN pins. On Starmie, we need +/-6V power supply for the MIPI panel. We program the AW37503 registers in coreboot so that kernel can control AW37503 via fixed regulators without additional settings(what we did for TPS65132). Since we distinguish AW37503 and TPS65132 by reading the vendor ID, we need to initialize I2C bus as early as possible. Therefore, we move mtk_i2c_bus_init() to mainboard_init(). BUG=b:289482828 TEST=emerge-staryu coreboot chromeos-bootimage TEST=Test the sequence the voltage Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26soc/mediatek: Enable DRAM scramble on fast calibration flowXi Chen
No matter what DRAM calibration is performed, DRAM scramble should be enabled as long as MEDIATEK_DRAM_SCRAMBLE is set to y. Currently, DRAM scramble is enabled only if full calibration is performed. Correct the behavior by adding DRAMC_CONFIG_SCRAMBLE to the header config in fast calibration flow. BUG=b:285474337 TEST=Check the scramble feature is disabled on serial build Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I907bccd4e68e040179e1971db6bf7a57b88dec1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21soc/mediatek: Add a prompt string for MEDIATEK_DRAM_SCRAMBLEXi Chen
Make the default MEDIATEK_DRAM_SCRAMBLE value overridable by adding a prompt string. BUG=b:285474337 TEST=build pass and check scramble feature is disabled on serial build Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I703ac9aa3ccc4dd9d0fef9949c6b0d49449971a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75815 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/common: Disable DRAM scramble by defaultYidi Lin
Geralt SoC does not support 'persist certain regions' across reboots. Considering the impact of missing ramoops for debugging, set MEDIATEK_DRAM_SCRAMBLE to default n to disable this feature in production FW image. BUG=b:269049451,b:278478563 TEST=emerge-geralt coreboot and confirm CONFIG_MEDIATEK_DRAM_SCRAMBLE=n Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/75562 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/mediatek/common: Add support for power supply TPS65132SRuihai Zhou
The TPS65132S is designed to supply positive/negative driven application. It communicates through standard I2C compatible interface, and it intergrates a EEPROM whose contents will be loaded into the register at startup. Since TPS65132S is used in staryu and geralt projects, we move the implementation to mediatek/common. The datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:282902297 TEST=boot starmie to firmware screen Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75488 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24soc/mediatek/dptx.c: Remove set but unused variablesArthur Heymans
This fixes clang warning about set but unused variables. Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-04-14soc/mediatek: Add support for regulator VIO18Cong Yang
To provide power to MIPI panel STA_HIMAX83102_J02, add support for regulator VIO18. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74341 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
2023-04-10soc/mediatek/mt8186: Move GPIO driving-related functions to commonJason Chen
Move GPIO driving-related functions to common for code reuse. BUG=b:270911452 TEST=build pass Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74068 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Reduce GPIO code size in bootblockJason Chen
Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downsized from 1480 bytes to 24 bytes. BUG=b:270911452 TEST=build pass Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74062 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytesYidi Lin
Original lastbus configuration consumes constant memory size by allocating 16 and 8 members arrays and the utilization is bad. Refactor the lastbus structs to save memory usage. BRANCH=none BUG=none TEST=bootblock.raw.bin size is reduced from 60328 bytes to 59048 bytes. Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74061 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10soc/mediatek/mt8188: Enable lastbus debug hardwareot_zhenguo.li
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. There are two versions for lastbus: Version 1 for MT8186, and version 2 for MT8188. BUG=b:263753374 TEST=build pass. Change-Id: Ibaf510481d1941376bd8da0168ef17c99a0fb9a2 Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73624 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-02soc/mediatek: Add config to control DRAM scrambleXi Chen
The DRAM scramble feature enhances DRAM data protection. When it's enabled, the written DRAM data will be scrambled and hence can prevent the data from being hacked. This feature would make debugging more difficult (for example ramoops would be lost after reset). Therefore, add a new config to allow enabling or disabling the feature from coreboot, without having to maintain two versions of the DRAM calibration blob. BUG=b:269049451 TEST=build pass and check scramble enable or disable successfully Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: Ib4279bc1cc960fae9c9f5da39f4448a5627288d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-23soc/mediatek: Add "DRAM" to Kconfig MEDIATEK_BLOB_FAST_INIT nameYu-Ping Wu
In the current Kconfig option MEDIATEK_BLOB_FAST_INIT, the meaning of "BLOB" is unclear. Add "DRAM" to the name. BUG=b:204226005 TEST=./util/abuild/abuild -t GOOGLE_STEELIX -x Change-Id: Ida7bda770f1d1a40cae205b08c8cb22f2329e49f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73155 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09mb/google/geralt: Init MT6359P only once in ramstageLiju-Clr Chen
The regulator MT6359P is needed by both firmware display and SD card. To avoid duplicate initialization in ramstage, publicize init_pmif_arb() as mt6359p_init_pmif_arb() and call it from mainboard_init(). This would save 13 ms for boot time on Geralt. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72839 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-08soc/mediatek: Add support for regulator VM18Sen Chu
To provide power to MIPI panel BOE_TV110C9M_LL0, add support for regulator VM18. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: Ib8c3b2df1157b23b37492b1e9b1716903ea67799 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72747 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08soc/mediatek: Remove unnecessary !! for boolean variableLiju-Clr Chen
Enable is already a boolean, so the !! is not needed. BUG=None TEST=build pass. Change-Id: I25a7cec632f21a258b8364c82e25b59e55ab7453 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72869 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-16commonlib/storage: Add common eMMC functionsShelley Chen
Now that multiple platforms are trying to initialize eMMC in coreboot instead of depthcharge, lets move common functionality into commonlib instead of copying the same functionality between multiple platforms. Note for consistency, changed name of set_early_mmc_wake_status() to mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function for retrieving the Operating Conditions Register (OCR) contents. BUG=b:218406702 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage flash onto villager device and make sure still boots ChromeOS Change-Id: Id00535b05bbd379081712601ef10e762c1831747 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12soc/mediatek/common/mcu.c: Use 'enum cb_err' instead of 'int'Elyes Haouas
mtk_init_mcu() function already returns enum cb_err. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I562bfbdc5c917a17ce1aa656046b69eb56dce48c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-10soc/mediatek/common: Reset the watchdog timer before triggering resetRunyang Chen
When the watchdog timer reaches 0, the timer value won't reset to the default value unless there is an external reset or a kick. It will result in the watchdog failing to trigger the reset signal. We kick the watchdog to reset the timer to the default value. Also, because WDT hardware needs about 94us to synchronize the registers, add a 100us delay before triggering the reset signal. BUG=b:264003005, b:264017048 BRANCH=corsola TEST= Reboot successfully with the following cmd stop daisydog sleep 60 > /dev/watchdog& Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com> Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/mediatek: Add DEVAPC_DEBUG optionYidi Lin
Add DEVAPC_DEBUG option and set this option to disabled by default. This option prevents DEVAPC log flooding during the boot process. Enable this option when we need to debug DEVAPC issues. TEST=DEVAPC log is disabled by default. Change-Id: I26bc0378b8a766c6a8cc4903d64a921c3e96b93f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71158 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/mediatek: Move dapc_init to commonYidi Lin
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this function to common/devapc.c TEST=emerge-corsola coreboot; emerge-cherry coreboot; emerge-geralt coreboot TEST=devapc log is shown as expected and the system boots to kernel Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-13soc/mediatek/common: Use write32p()Elyes Haouas
Change-Id: I83707071fe1801322dffad7fc89afaef5617f3c7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-09mem_chip_info: Update to new formatJulius Werner
The original version of the mem_chip_info structure does not record rank information and does not allow precise modeling of certain DDR configurations, so it falls short on its purpose to compile all available memory information. This patch updates the format to a new layout that remedies these issues. Since the structure was introduced so recently that no firmware using it has been finalized and shipped yet, we should be able to get away with this without accounting for backwards compatibility. BRANCH=corsola Cq-Depend: chromium:3980175 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68871 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-12-05soc/mediatek: Fix DSI register definition for MT8186Bo-Chen Chen
The DSI CMDQ offset of MT8186 is different from previous SoCs. Therefore, we define two versions for DSI register header files. The v1 is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188. BUG=b:244208960 TEST=build pass BRANCH=corsola Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23soc/mediatek: Add error handling for dptx_get_edid()Liju-Clr Chen
Skip eDP initialization when we failed to get EDID. This prevents the PLL assertion in dp_intf_config() if the display could not be initialized properly. BUG=b:233720142 TEST=boot to depthcharge on MT8188 EVB. Change-Id: I0fd672b175feb9b813c1d9ec4140e4273079ff07 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69858 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas
Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-04lib/coreboot_table: Rename lb_fill_pcieArthur Heymans
By convention 'fill_lb_xxx' is used. Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69183 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04lib/coreboot_table: Simplify API to set up lb_serialArthur Heymans
Instead of having callbacks into serial console code to set up the coreboot table have the coreboot table code call IP specific code to get serial information. This makes it easier to reuse the information as the return value can be used in a different context (e.g. when filling in a FDT). This also removes boilerplate code to set up lb_console entries by setting entry based on the type in struct lb_uart. Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-10-26coreboot_tables: Drop uart PCI addrArthur Heymans
Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-25soc/mediatek/mt8188: Update mtcmos settings for display and audioBo-Chen Chen
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are required. - For audio, it requires powering on adsp_ao_pwr_con, adsp_infra_pwr_con and audio_pwr_con. - Add new power domain data `ext_buck_iso_bits` for buck isolation control. BUG=b:244208960 TEST=access display registers successfully. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25soc/mediatek: Add support for input 1P mode of dp_intfRex-BC Chen
MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct member `input_mode` is added to `struct mtk_dpintf` for differentiation. We also move SoC-specific data `dpintf_data` to soc folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25soc/mediatek: Move DP drivers to commonBo-Chen Chen
DP drivers can be shared for both MT8195 and MT8188, so move them to common folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-21soc/mediatek: Unify PLL function namesRex-BC Chen
For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add support for PMIC MT6315Sen Chu
On MT8186T, the big cores are powered on by MT6315 via PMIF. This patch adds the following changes. - Add MT6315 settings. - Configure PMIC PMIF for MT6315. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek: Move SPMI interface configuration to SoC folderSen Chu
The SPMI interface configuration is SoC-dependent. - MT8192 and MT8195 are the same. - MT8186 does not need to implement this. - MT8188 is different from MT8195, and we will submit another patch to fix this. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig optionRex-BC Chen
For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't need to configure PMIF SPMI IO pins. Add a config to control that. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig optionRex-BC Chen
On MT8186, PMIC interface supports PWRAP and PMIF_SPMI while other MediaTek SoCs support PMIF_SPMI and PMIF_SPI. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68577 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add support for reading CPU IDRex-BC Chen
MT8186 has two slightly different versions: MT8186G and MT8186T (turbo version). Add get_cpu_id() to identify different CPUs. BUG=b:249436110 TEST=cpu id is correct. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec Reviewed-on: https://review.coreboot.org/c/coreboot/+/68576 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/mediatek/mt8186: Add DEVAPC settings for ADSPTinghan Shen
Add DEVAPC permission settings for ADSP and set its domain number to 6. TEST=SOF driver is functional. BUG=b:204229221 Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/mediatek/mt8186: Add mtcmos power-on control for ADSPMandy Liu
To use SOF correctly, we need to enable power domain of ADSP. TEST=SOF driver is functional. BUG=b:204229221 Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com> Change-Id: I39d1357af5f901a91379fdf7e595f16952b962de Reviewed-on: https://review.coreboot.org/c/coreboot/+/68288 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9cf4097518034fa4c3ae1899840ae3a276936f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67581 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-09soc/mediatek/mt8186: Enable lastbus debug hardwareot_zhenguo.li
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. TEST=build pass. BUG=none Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: Iff39486dfad556a3104b2f2b6811c34c2ded6954 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-08src: De-conflict CALIBRATION_REGION definitionsMartin Roth
Change the name of the CALIBRATION_REGION definitions used in two separate locations. This conflict was causing an error for the lint-001-no-global-config-in-romstage test. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-07soc/mediatek: a common implementation to register BL31 resetHung-Te Lin
The implementations of register_reset_to_bl31() are the same for MedaiTek platforms, so we extract them to soc/common/bl31.c. BUG=None TEST=build pass Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek: Move some SPM functions to commonBo-Chen Chen
Some functions are the same in spm.c for MT8192, MT8195, MT8186 and MT8188, so we move them to common/spm.c. TEST=build pass. BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I29ddefc47d8bd156fa1ca0cedd4deaed676ae7e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek/mt8188: Use MHz as unit for current_clkBo-Chen Chen
The unit of current_clk in pmif_ulposc_check() should be MHz. We use pmif_get_ulposc_freq_mhz() to get the default hardware value in MHz. Without this modification, the judgement in pmif_ulposc_check() is alway wrong due to the wrong unit. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3bf80a23bb35ff657023eb4b7e009fa233f61244 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek: Move common DEVPAC enums and functions to commonBo-Chen Chen
Some enums and functions are the same in DEVAPC driver for MT8195, MT8186, and MT8188, so we move them to common folder. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia7d2145780780fd54b76952db96424b8ea477594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek: Move dpm_4ch.c to commonXi Chen
MT8195 and MT8188 share the same dpm_4ch.c, so we move it to common folder. TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I13406707d3b331ced57af62f4ba4f365e9ac4f84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66966 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-27soc/mediatek: Move emi.c to common folderRex-BC Chen
The emi.c is the same for MT8186 and MT8188, so we could move it to the common folder and reuse it. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I225f1d07c973129172f01bf7f4d7f5d5abe7c02b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66328 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek: Move common definition of DFD to common folderRex-BC Chen
We use the same dump address and size for DFD in all MediaTek SoCs, so we move them to dfd_common.h and rename dfd_common.h to dfd.h. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I162bbb0a82e3b55c8cfbbd20e28a54ad01fd6b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66585 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen
Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay settingRex-BC Chen
MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.hRex-BC Chen
Move the common definitions to rtc_reg_common.h, so we can reuse those definitions on MT8188. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek: Move struct mtk_auxadc_regs to auxadc_common.hRex-BC Chen
The AUXADC register definitions are the same for all MediaTek SoCs, so we move struct mtk_auxadc_regs to auxadc_common.h. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-22mb/google/geralt: Implement regulator interfaceHui Liu
Control regulator more easily with regulator interface. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mb/google: Use boolean type for "enable" argument for regulatorRex-BC Chen
Because 0 and 1 are the only possible values, 1. Change input argument "enable" of mainboard_enable_regulator to bool. 2. Change return value of mainboard_regulator_is_enabled() to bool. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21mb/google: Replace some strings in regulator.cRex-BC Chen
From comments of CB:65875, we replace *_vol to *_voltage. s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/ s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/ TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-21soc/mediatek/mt8188: Add VMCH, VMC support for MT8188Hui Liu
For MT8188, we need to enable and adjust VMCH and VMC to support SD cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21soc/mediatek: Create a function to check ulposcRex-BC Chen
We will use the same drivers for checking ulposc in MT8188, so we add a new function pmif_ulposc_check() to common. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40136eaeb2c08a97cd65bfb8a81f2f24739d4d51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65841 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek: Move SPMI device table to SoC folderHui Liu
The SPMI devices on MT8188 are different from previous SoCs, so we move them to SoC folder. We also move SoC-specific definitions to soc/pmif.h. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I666c2a8222a2bd8cd460e2225a7ae48b001da9d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65757 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12soc/mediatek: Add mt_pll_set_usb_clock() to enable usb clockRex-BC Chen
There are clock settings for usb in mt8195 and mt8188, so we add a new function which is implemented in pll.c to do this. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40b358b197541bc5281645879553340059829db3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/mediatek: Move FLASH_DUAL_READ to commonRex-BC Chen
FLASH_DUAL_READ is a common configuration for all MediaTek SoCs, so we move it to common folder and select it in SoCs' Kconfig. As suggested in CB:58837, we also rename FLASH_DUAL_READ to FLASH_DUAL_IO_READ to reduce confusion. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If267a332519412a7919c5b7817047fabe4a564c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65620 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/mediatek: Move some gpio functions to common/gpio_op.cRex-BC Chen
gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd() can be reused for mt8192, mt8195 and mt8186, so move it to new file "gpio_op.c" in common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Make timer_prepare() a common functionRex-BC Chen
timer_prepare() is the same for MT8195 and MT8186, so move it to common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen
There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-12soc/mediatek: pass access mode to the payloadWenbin Mei
Some eMMCs (for example, Kingston-EMMC64G-TX29-HP) may enter the ready state by sending CMD1 twice. If it is in the ready state, then the payload (for example, depthcharge) will not send CMD1, but the access mode is only available from the response of CMD1. Therefore, we need to pass the access mode to the payload by defining the following types: - MMC_STATUS_CMD1_READY: in ready state and access mode is byte mode. - MMC_STATUS_CMD1_READY_HCS: in ready state and access mode is sector mode. BUG=b:234672726 BRANCH=cherry TEST=boot ok Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iad905781d8ba0105911cf87a6b845cd8df57521e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65054 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-03soc/mediatek: Rename mtk_wdt_preinit() to mtk_wdt_set_req()Rex-BC Chen
To simplify the calling sequence for mtk_wdt_preinit() and we always adjust request setting in mtk_wdt_preinit(), we rename mtk_wdt_preinit() to mtk_wdt_set_req() and call it in mtk_wdt_init(). From this modification, we can also enable thermal hardware reset feature (CB:64676, CB:64675) in MT8192 and MT8195. BUG=none TEST=build pass Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-28soc/mediatek/mt8186: Enable thermal hardware resetRunyang Chen
Under the current watchdog setting, the system will not reboot when the temperature is too high. To enable thermal hardware reset, we need to enable thermal control request and set it to reboot mode. Note that because thermal throttle (by lowering cpu frequency) is currently enabled, the thermal hardware reset shouldn't be triggered under normal circumstances. This feature is only for new hardware structure for thermal. Therefore, we only need to apply it on MT8192/MT8195/MT8186. This setting is based on thermal and watchdog section of MT8186 Function Specification. BUG=none TEST=emerge-corsola coreboot TEST=thermal hardware reset is working. Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: Id2ed55e6d4f4eec450bf7c849f726a389eeb6694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64659 Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-20CBMEM: Change declarations for initialization hooksKyösti Mälkki
There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20soc/mediatek: Fill coreboot table with PCIe infoJianjun Wang
In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-09soc/mediatek: Demote log level of SPMI clock calibration problem to infoRex-BC Chen
It's expected that the mismatch logs will be shown when doing calibration for spmi clock. If it is failed to do calibration for spmi clock for all data, the system will enter "die". Therefore, we adjust the log level from BIOS_ERR to BIOS_INFO. BUG=b:231531254 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64090 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-31soc/mediatek/early_init: Fix function return typeJianjun Wang
Fix return type of early_init_get_elapsed_time_us() to comply with the data type of return value. Also replace memset() with struct initializer. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Fixes: commit 41faa22 (soc/mediatek: Add early_init for passing data across stages) Change-Id: I7c361828362c2dfec91358ad8a420f5360243da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29soc/mediatek: Ensure PERST# deassertion time follows the specJianjun Wang
According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met, calculate the elapsed time since assertion. If it is smaller than 100ms, do an extra delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the measured PERST# time: [DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries) And the SSD information in boot log is as follows: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/mediatek: Add early_init for passing data across stagesJianjun Wang
Add support for "early_init_data" region, which can be used to store data initialized in an early stage (such as bootblock), and retrieve it in later stages (such as ramstage). TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"Rex-BC Chen
The memory initialization reference code didn't support returning DRAM information in the old platforms, for example MT8192 and MT8195. So we have to add a new configuration USE_CBMEM_DRAM_INFO to make sure the common code will try to get DRAM information on new platforms supporting that. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-27soc/mediatek: Include 'console/console.h' when appropriateElyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-03-27src/soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27src: Remove unused <bootmode.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <bootmode.h>' -- src/) <(git grep -l 'platform_is_resuming\|gfx_set_init_done\|gfx_get_init_done\|display_init_required\|get_ec_is_trusted\|get_lid_switch\|get_wipeout_mode_switch\|clear_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_write_protect_state\|init_bootmode_straps' -- src/) |grep "<" Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-25soc/mediatek/i2c.c: Remove unused variablesArthur Heymans
Change-Id: Iaa643feb76530cc74acf4d714d8a7f96709be1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-23soc/mediatek: Save dram info to cbmemXi Chen
Store dram info in cbmem for ramstage or payloads to use. BUG=b:206014043 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-18soc/mediatek/mt8186: Disable unused spm_thermalRex-BC Chen
In MT8186, we need to disable spm_thermal to prevent it from influencing other wdt status. There are two hardware pathes which are used for asserting watchdog from thermal. We can disable status of path 1 because status of path 2 is used. 1. Thermal -> SPM -> WDT 2. Thermal -> WDT Spm_thermal (path 1) is a flexible option for software control, and the hardware designer suggests that we should disable it if we don't use it. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0Rex-BC Chen
Because we close external signal in kernel driver since MT8195, it's more reasonable to trigger sw reset with exteranl signal again whenever the wdt status is not equal to 0. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-16soc/mediatek: PCI: Remove global variableJianjun Wang
Remove global variable and use 'pcidev_path_on_root()' to get the base address of PCIe controller. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16soc/mediatek: Add chip config for setting PCIe configJianjun Wang
Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15i2c: Add configurable I2C transfer timeoutJes Klinke
This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US, which controls how long to wait for an I2C devices to produce/accept all the data bytes in a single transfer. (The device can delay transfer by stretching the clock of the ack bit.) The default value of this new setting is 500ms. Existing code had timeouts anywhere from tens of milliseconds to a full second beween various drivers. Drivers can still have their own shorter timeouts for setup/communication with the I2C host controller (as opposed to transactions with I2C devices on the bus.) In general, the timeout is not meant to be reached except in situations where there is already serious problem with the boot, and serves to make sure that some useful diagnostic output is produced on the console. Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-15soc/mediatek/common: Add halt() after triggering wdt resetRex-BC Chen
It's more reasonable to halt when we trigger watchdog reset because the whole system should be reset afterwards. BUG=b:222217317 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-09soc/mediatek/mt8186: Add GPIO driving functionsGuodong Liu
Add GPIO driving functions to adjust pin driving. The value of drive strength is different for each SoC, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09commonlib/bsd: Remove cb_err_tJulius Werner
cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09soc/mediatek: Add PCIe supportJianjun Wang
Add PCIe support for MediaTek platform. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) - linux/drivers/pci/controller/pcie-mediatek-gen3.c This code is based on MT8195 platform, but it should be common in each platform with the same PCIe IP in the future. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02soc/mediatek: remove unused RTC_GPIO_USER_MASKRex-BC Chen
RTC_GPIO_USER_MASK is not used in any drivers, so we remove them. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-23src/mediatek: Refactor dramc_param to share more structuresXi Chen
The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To prevent code duplication, move it as well as other related structs and enums to a common header. Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-12soc/mediatek: Fix printing SPM versionYu-Ping Wu
Currently the SPM version string is stored at the end of the blob, possibly without a trailing '\0'. Therefore, we should be careful not to print characters beyond the blob size. BUG=b:211944565 TEST=emerge-corsola coreboot TEST=SPM version looked good in AP console BRANCH=asurada,cherry Change-Id: Icfeb686539dc20cf5b78de77c27bdbb137b5d624 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-11soc/mediatek: Only update required bits when triggering WDT resetRex-BC Chen
To prevent to modify original value of wdt_mode, we use setbits32 to update required bits. BUG=b:218420108 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I743c1af3583c18ec8500fc1eb89f31cdbce5317c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61729 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-09soc/mediatek/mt8186: Fix issue of clearing watchdog statusRex-BC Chen
The implementation of clearing watchdog status is wrong in CB:58835. The value written to the 'wdt_mode' register should be 'wdt_mode | 0x22000000' instead of 'wdt_status | 0x22000000'. BUG=b:204229208 TEST=check watchdog status is cleared. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-09soc/mediatek/mt8186: Support DRAM fast calibration using blobXi Chen
For most MediaTek SoCs (MT8183, MT8192, MT8195) we rely on an external program (e.g., the "DRAM blob") to do the full DRAM calibration first, then store and and apply the generated parameters to the reference "fast DRAM calibration" in the vendor/mediatek folder for normal system boot. Starting with MT8186 the implementation of fast calibration may need to be changed, and a "DRAM blob" only path is introduced for devices that have to do both full and fast calibration using the external blob. TEST=fast calibration pass on kingler/krabby BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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