soc/mediatek: Unify PLL function names

For consistency with the PLL function naming:
- Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel().
- Rename mux_set_sel() to pll_mux_set_sel().

BUG=none
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 6 insertions, 3 deletions

diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index 5c73a122a1..5484d67783 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -64,14 +64,17 @@ DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0)
 
 DEFINE_BITFIELD(PLL_CON1, 31, 0)
 
+/* PLL internal interface */
 void pll_set_pcw_change(const struct pll *pll);
-void mux_set_sel(const struct mux *mux, u32 sel);
+void pll_mux_set_sel(const struct mux *mux, u32 sel);
 int pll_set_rate(const struct pll *pll, u32 rate);
+
+/* PLL internal interface */
 void mt_pll_init(void);
 void mt_pll_raise_little_cpu_freq(u32 freq);
 void mt_pll_raise_cci_freq(u32 freq);
 void mt_pll_set_tvd_pll1_freq(u32 freq);
-void edp_mux_set_sel(u32 sel);
+void mt_pll_edp_mux_set_sel(u32 sel);
 void mt_pll_spmi_mux_select(void);
 void mt_pll_set_usb_clock(void);
 
diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c
index ca6226a91a..f13911b2d7 100644
--- a/src/soc/mediatek/common/pll.c
+++ b/src/soc/mediatek/common/pll.c
@@ -5,7 +5,7 @@
 #include <soc/pll.h>
 #include <types.h>
 
-void mux_set_sel(const struct mux *mux, u32 sel)
+void pll_mux_set_sel(const struct mux *mux, u32 sel)
 {
 	u32 mask = GENMASK(mux->mux_width - 1, 0);
 	u32 val = read32(mux->reg);