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2021-06-10soc/mediatek/mt8195: add power and power control for eDPJitao Shi
1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate. 2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel. 3. Add eDP power domain control. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/mediatek: Extract spm_parse_firmware to commonRex-BC Chen
spm_parse_firmware can be shared by MT8192 and MT8195. TEST=emerge-asurada coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55139 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01soc/mediatek: Move the SSPM driver to commonRex-BC Chen
The SSPM driver can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{asurada, kukui} coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55050 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/mediatek: Move the MT8192 MCUPM driver to commonRex-BC Chen
The MPUCM drivers can be shared by MT8192 and MT8195. TEST=emerge-asurada coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I07a66bcf5a149582f34df1cfd08b5514fc5c2eb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-14soc/mediatek: Remove duplicate enum declarationRex-BC Chen
Remove dram_cbt_mode in dramc_soc.h. TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idc4a3887c9cc3f77cbdd7282e2977f6df858817d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
2021-05-10soc/mediatek/mt8195: Add RTC driverYuchen Huang
Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10soc/mediatek/mt8195: Add clk_buf driverYuchen Huang
Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek/mt8195: Add mtcmos init supportWeiyi Lu
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek: Move the power domain data under each SoCWeiyi Lu
In follow-up patches, we need to set multiple power domains to power on the display and audio on MT8195. Move the power domain data under each SoC and make power_on() API to support multiple settings. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8c3d19f1e9a4e516d674d68989ad509f37e5b593 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek: Move the common part of SPI drivers to common/Rex-BC Chen
The SPI drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Cherry P0 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek/mt8195: add pmif/spmi/pmic driverRex-BC Chen
MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-28soc/mediatek: Move the common part of PMIC drivers to common/Yidi Lin
The PMIC drivers can be shared by MT8192 and MT8195. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie17e01d25405b1e5119d9c70c5f7afb915daf80b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Add timer supportYidi Lin
TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/mediatek/mt8195: Initialize watchdogYidi Lin
MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-21soc/mediatek: Move mt8192 ufs driver to commonYidi Lin
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I28eb13edcded95a9a4c17bdf92da9f792883a613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-21src/mediatek: Move mt8192 eint driver to commonYidi Lin
The eint driver can be shared by multiple platforms so we want to move it to common/. BRANCH=asurada TEST=emerge-asurada coreboot Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id8e0b631d5079e51213831ed17aa540e0afadd4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-16soc/mediatek: Remove misleading memory logsYu-Ping Wu
When MRC cache region type is not found (for example, in recovery mode with !HAS_RECOVERY_MRC_CACHE), mrc_cache_stash_data() will return 0. Therefore, the platform code is not able to tell from the return value if the MRC cache data is actually written to flash or not. Since the MRC driver is already pretty verbose, ignore the return value and remove the misleading memory logs. BUG=none TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: I6b411664ca91b9be2d4518a09e9734d26db02d6e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52361 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/mediatek: Include sdram_info in ddr_base_infoYu-Ping Wu
Sync dramc_param.h with private repo mtk-dramk (CL:*3751861). BUG=none TEST=emerge-asurada coreboot TEST=Hayato boots with fast calibration BRANCH=asurada Change-Id: I79541f66ce68a75147c22b83a456e6268ca1485e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-09soc/mediatek: add new driver 'msdc' for eMMCWenbin Mei
Add MTK host mmc driver support. MTK host controller supports eMMC5.1 spec. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-08soc/mediatek: dsi: fine tune the delta time for EoTpJitao Shi
We seperate the EoTp packet extra data. So need to reduce the delta. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-27soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_ENDJitao Shi
ANX7625 requires the line packets to end at the same time. Otherwise, the display will be shifted. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Jacuzzi Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-24soc/mediatek: Use MRC cache API for asuradaYu-Ping Wu
Use the MRC cache API for asurada, and sync dramc_param.h with dram blob (CL:*3674585). With this change, the checksum, originally stored in flash, is replaced with a hash in TPM. In addition, in recovery boot, full calibration will always ne performed, and the cached calibration data will be cleared from flash. This change increases ROMSTAGE size from 236K to 264K. Most of the increase is caused by TPM-related functions. Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be moved to soc folder. With this CL, there is no significant change in boot time. Normal AP reboot time (fast calibration) is consistently 0.98s as before, so this change should not affect the result of platform_BootPerf. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Hayato boots with both full and fast calibration BRANCH=none Cq-Depend: chrome-internal:3674585, chrome-internal:3704751 Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-16cbfs: Remove prog_locate() for stages and rmodulesJulius Werner
This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/mediatek/common: Move DRAM implementation from mt8192 to commonXi Chen
To reduce duplicated dram sources on seperate SOCs, add dpm, dram_init, dramc_params, memory(fast-k or full-k) implementations, also add dramc log level macro header files. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28soc/mediatek/mt8192: Add function to raise the CCI frequencyWeiyi Lu
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency. Usage: mt_pll_raise_cci_freq(1400UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07soc/mediatek: rtc: Use `bool` as return typeYidi Lin
BUG=b:176307061 TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot boot to shell on Asurada Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-01soc/mediatek: dsi: Fix EoTp flagShaoming Chen
SoC will transmit the EoTp (End of Transmission packet) when MIPI_DSI_MODE_EOT_PACKET flag is set. Enabling EoTp will make the line time larger, so the hfp and hbp should be reduced to keep line time. BUG=b:168728787 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Move flash_controller.c to common/Yidi Lin
The flash controller driver can be shared among mt8173 and mt819x. TEST=boot to kernel on Asurada boot to kernel on Hana (w/o BL31) Change-Id: I4e5213563189336496122a0f2d8077b3e5245314 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-28soc/mediatek/mt8192: add rtc MT6359P driverYuchen Huang
Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor mt8173 and mt8183 code by extracting common API. Move rtc_read and rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via pmic wrapper, while mt8192 accesses it via pmif. Reference datasheet: Document No: RH-D-2018-0101. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-22soc/mediatek/mt8192: Do memory pll init before calibrationHuayang Duan
Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode. TEST=Confirm Memory PLL frequency is right by frequency meter Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-14soc/mediatek/mt8183: Move dsi driver to common/Yidi Lin
The mt8183 dsi driver can be shared with mt819x SoC. Move dsi.c to common/ folder and rename it to dis_v2.c to differentiate it from mt8173's dsi driver. TEST=emerge-kukuki coreboot Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-14soc/mediatek/mt8192: add i2c driver supportQii Wang
Add I2C controller for MT8192, and revise the common I2C driver to support I2C controller running in APDMA async mode. In that case we have to initiate a different handshake protocol and reset I2C differently. BUG=b:155715435 TEST=Asurada boots up to shell Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/common: Add common API for loading firmwaresYidi Lin
Add mtk_init_mcu to load the firmware to the specified memory address and run the firmware. This function also measures the load time and the blob size. For example: mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (14004 bytes) Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-20soc/mediatek: Move auxadc driver from MT8183 to commonPo Xu
The auxadc (auxiliary analogue-to-digital conversion) is a unit to identify the plugged peripherals or measure the temperature or voltages. The MT8183 auxadc driver can be shared by multiple MediaTek SoCs so we should move it to the common folder. Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-18mb/google/asurada: Implement enable_regulator and regulator_is_enabledYidi Lin
SD Card driver needs to access two regulators - MT6360_LDO5 and MT6360_LDO3. These two regulators are disabled by default. Two APIs are implemented: - mainboard_enable_regulator: Configure the regulator as enabled/disabled. - mainboard_regulator_is_enabled: Query if the regulator is enabled. BUG=b:168863056,b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46687 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18mb/google/asurada: Implement board-specific regulator controlsYidi Lin
Currently, five regulator controls are implemented for DRAM calibration and DVFS feature. The regulators for VCORE and VM18 are controlled by MT6359. The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360 via EC. BUG=b:147789962 BRANCH=none TEST=verified with DRAM driver Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-22soc/mediatek/mt8192: Add board-specific regulator APIsYidi Lin
To enable DVFS, DRAM driver needs to access four different regulators that SoC can't access directly and need board-specific implementations. To support that we need to define the getter and setter APIs for those regulators. BUG=b:147789962 BRANCH=none TEST=verified with DRAM driver Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I0c2d471a7f8628735af90c5b5a5ab3012831e442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46405 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/mediatek: Add function to measure clock frequency of MT8192Weiyi Lu
Implement mt_fmeter_get_freq_khz() in MT8192 to measure frequency of some pre-defined clocks by frequency meter. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45402 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/mediatek: Add function to raise the CPU frequency of MT8192Weiyi Lu
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq(). Implement mt_pll_raise_little_cpu_freq() in MT8192. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-17soc/mediatek/mt8192: Add mtcmos init supportWeiyi Lu
Using common mtcmos code to power on audio and display modules in SOC. TEST=Boots correctly on MT8192EVB. Passes the status check at the end of mtcmos_power_on() Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ie7bff831eecfc2b4d315a577f6ff86befc483eab Reviewed-on: https://review.coreboot.org/c/coreboot/+/45394 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16soc/mediatek: move power status bits under each chipWeiyi Lu
The power status bits of display and audio of MT8192 are different from the bits of MT8173 & MT8183, so move those under each chip. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Iaa211b8db733d8aa52d93af9e507042bf0984d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-10soc/mediatek: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-26soc/mediatek: Include addressmap.h in gpio_common.hCK Hu
The gpio_common.h needs EINT_BASE from addressmap.h. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I20834e38343410526da0a489fed907acbf479d02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-12soc/mediatek/mt8192: Add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-06soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem initHuayang Duan
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I072745933fe141cac26afd044836a564e345d036 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43795 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src/soc/mediatek: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: I8e4a7af68a52d82117b8b091fa448bb6ad40ae7d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove duplicated includesElyes HAOUAS
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18soc/mediatek: dsi: adjust hfp_byte and hbp_byte if too smallPaul Ma
If panel has too small hfp or hbp, hfp_byte or hbp_byte may become very small value or negative value. When very small value or negative value is used, the panel will be scrolling or distorted. This patch adjusts their values so that they are greater than the minimum value and keep total of them unchanged. DSI transfer HBP or HFP, There are some extra packet. ex. packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). the hfp_byte = HFP * BPP - packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). So the min hfp_byte is 2 when HFP = 4. This is equivalent to the Linux kernel DSI change in: https://chromium-review.googlesource.com/c/chromiumos/third_party/ kernel/+/2186872 BUG=b:144824303 BRANCH=kukui TEST=boot damu board with panel CMN N120ACA-EA1 (12" panel and its hbp only 6), the panel can display without scrolling or distortions. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: I608c01d41ae93c8d5094647bbf3e0ae4a23d814c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41163 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stddef.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l 'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\ |MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05soc/mediatek: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7c3c75eaf2d7a64e7d833541bcf168b93921a142 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/mediatek: Fix typos in commentsElyes HAOUAS
Also add missing whitespace. Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-02-17soc/mediatek: dsi: Correct bits_per_pixel for MIPI_DSI_FMT_RGB666Yu-Ping Wu
The number of bits per pixel for MIPI_DSI_FMT_RGB666 should be 24 instead of 18. BRANCH=none BUG=none TEST=none Change-Id: I9574502b2dec4b5a042df3886922ddd8c755da1a Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jitao Shi <jitao.shi@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-17soc/mediatek: dsi: reduce the hbp and hfp for phy timingJitao Shi
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen. To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442. Also rename 'phy_timing' to 'timing' to sync with kernel upstream. Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed. BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=Boots and sees firmware screen on krane and juniper TEST=No scrolling issue on juniper AUO and InnoLux panels Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-17soc/mediatek: dsi: Increase pcw precisionYu-Ping Wu
When configuring MIPI DSI Tx, the value of pcw was calculated from data rate in MHz, leading to loss of precision. This patch changes to use data rate in Hz for the calculation so that the resulting value should be consistent with the one in kernel (CL:1786327). In addition, change the type of data rate to u32, and calculation of data rate from pixel clock is changed to use DIV_ROUND_UP for consistency with kernel (CL:1761843). Also remove unused variable txdiv. BRANCH=kukui BUG=b:149051882 TEST=emerge-jacuzzi coreboot TEST=No scrolling issue on Juniper AUO and InnoLux panels Change-Id: I23220d446833b956431006027bbc8cb20fc696a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38827 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20src: Replace min/max() with MIN/MAX()Elyes HAOUAS
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33688 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src: Remove unneeded 'include <delay.h>'Elyes HAOUAS
Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34230 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-11-11soc/mediatek: Add missing '#include <console/console.h>'Elyes HAOUAS
Change-Id: I2e79ff3352fe974a070b7b3f5e4b5570ed2b294c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-23soc/mediatek/mt8183: add dphy reset after setting lanes numberJitao Shi
Add dphy reset after setting lanes number to avoid dphy fifo error. BUG=b:139150763 BRANCH=kukui TEST=Boots correctly on kukui Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-23soc/mediatek/mt8183: fine tune the phy timingJitao Shi
To fix MIPI D-PHY test failure, the hs-prepare should be less than LimitMin from spec, and we have to enlarge TEOT margin. BUG=b:138344447 BRANCH=kukui TEST=Boots correctly on kukui Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-19cpu,mb,soc: Init missing lb_serial struct fieldsJacob Garber
Initialize the input_hertz and uart_pci_addr fields of the lb_serial struct to prevent later undefined reads in lb_add_serial(). This was done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c: Init new serial struct variables), and this patch finishes the rest. Note that not all of the drivers can have the UART PCI address configured at build time, so a follow-up patch will be needed to correct those ones. Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1354778 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34548 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06soc/mediatek: Fix USB enumeration issueChangqi Hu
Some USB 3.0 devices fail to be enumerated after USB reset, and xhci port status register shows the device is disconnected. After measuring the USB signal, we found that the USB disconnect threshold was lower and that the disconnect event was triggered unexpectedly. USB designers suggest changing discth to 15. BUG=b:122047652 TEST=emerge-kukui coreboot chromeos-bootimage Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Signed-off-by: Changqi Hu <changqi.hu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21mediatek: Use GPIO based SPI CSYu-Ping Wu
Some boards (e.g., Kukui) need GPIO based CS for SPI0. This patch changes the pinmux and binds the pins to the correponding SPIs. When using GPIO based SPI CS, we need to manually make CS log/high before/after SPI transactions. BUG=b:132311067 BRANCH=none TEST=Verified that b/132311067 is irreproducible Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-20arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15soc/mediatek: Change DSI init commands to take flexible length arrayHung-Te Lin
The fixed size of init command in lcm_init_table is wasting lots of space and we should change to packed array since the command buffer already provides length information. With this change, BOE panel init commands have been reduced from 4848 bytes to 1309 bytes. BUG=b:80501386,b:117254947 TEST=emerge-kukui coreboot chromeos-bootimage; Boots properly Change-Id: I359dde8e6f2e1c0983f4677193bb47a7ae497ca6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34778 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15soc/mediatek/mt8183: Add DSI driverHung-Te Lin
The MT8183 display serial interface (DSI) is based on MIPI Alliance Specification, supporting high-speed serial data transfer between host processor and peripheral devices such as display modules. DSI supports both video mode and command mode data transfer defined in MIPI spec, and it also provides bidirectional transmission with low-power mode to receive messages from the peripheral. Reference: MT8183 Application Processor Functional Spec, 6.7 Display Serial Interface (DSI) BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15soc/mediatek: dsi: Support sending MIPI init commandsHung-Te Lin
For systems with real MIPI panels (8173/oak was using PS8640 eDP bridge), we have to send DCS commands to initialize panel. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Ie7c824873465ac82a95bcb0ed67b8b9866987008 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34773 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15soc/mediatek: dsi: Refactor video timing calculationHung-Te Lin
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-14soc/mediatek: dsi: Refactor PHY timing calculationHung-Te Lin
The PHY timing should be calculated by data rate (Mbps). However for 8173 some values were hard-coded so we want to introduce a new mtk_phy_timing structure and a weak function mtk_dsi_override_phy_timing that allows per-SOC customization to apply PHY timings. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-13soc/mediatek: dsi: Refactor MIPI TX configurationHung-Te Lin
The only platform-specific difference in mtk_dsi_phy_clk_setting is how to configure MIPI TX because those registers (and logic) are quite different across different SOCs. The calculation of data rate is actually the same so we should isolate it and move to common, and rename mtk_dsi_phy_clk_setting to a better name as mtk_dsi_configure_mipi_tx. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-13soc/mediatek: dsi: Unify format to bpp conversionHung-Te Lin
The 'bpp' was referred to both 'bits per pixel' and 'bytes per pixel' in MTK DSI driver and should be corrected. By this change we now always consider 'bpp' as 'bits per pixel', and rename the variables for other cases. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Ibd405220b73859e5592c68f498af07eef8d7edbc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34770 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13soc/mediatek: Create common DSI driver from mt8173Hung-Te Lin
The DSI initialization is almost the same for 8173 and 8183, so we want to move most of common functions into common/dsi.c. The major board-specific functions left are: - reset (controller register has different format) - pin_drv_ctrl (8183 does not need this) BUG=b:80501386,b:117254947 TEST=make -j # board=oak (mt8173) Change-Id: I8d4369a3c84db551287a9c9d1b22f552c5f7518d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34769 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/mediatek/mt8173: Refactor display driver to share common partsHung-Te Lin
Move those will be shared by other MTK SOCs (for example, MT8183) to common/ddp.c. BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Oak Change-Id: Ie5709ab6e263caa21fdf7e799dc2ee884ffaf800 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-02mediatek: Refactor I2C code among similar SOCsQii Wang
Refactor I2C code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Signed-off-by: qii wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/mediatek: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Id6d881055826044d04843ba165641131b9111342 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-11mediatek: Fill in input_hertz to coreboot tableTristan Shieh
Set input_hertz to 26 MHz. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I7f9c329ae5d610f2516e60f06b2ac96ebbeaa897 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-06mediatek/mt8183: Enable RTC eosc calibration feature to save powerRan Bi
When system shuts down, RTC enable eosc calibration feature to save power. Then coreboot RTC driver needs to call rtc_enable_dcxo function at every boot to switch RTC clock source to dcxo. BUG=b:128467245 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21mediatek: Add SPI tick_dly settingMengqi Zhang
Add spi tick_dly setting for high-speed spi xfer. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-29src/soc: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-29mediatek: Add function to raise the CPU frequencyTristan Shieh
Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency. Move the function declaration to common header. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-17mediatek: Use the 64-bit timerTristan Shieh
GPT4 is a 32-bit timer and the counter of GPT4 will overflow in about 330 seconds (0xffffffff / 13MHz). Timer and delay functions will not work properly if the counter overflows. To fix that we should use the 64-bit timer (GPT6). BUG=b:80501386 BRANCH=none Test=emerge-elm coreboot; emerge-kukui coreboot Change-Id: I9f080e47253a1b1bab4636a45cb86c8666a25302 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-06src: Use #include <timer.h> when appropriateElyes HAOUAS
Also, extra-lines added or removed and local includes moved down. Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02mediatek/mt8183: Fix RTC initialization flowRan Bi
1. Fix RTC lpd settings. Rewrite powerkeys after lpd init to enable low power detect function. 2. Rearrange RTC initialization flow. 3. Add return status for rtc_init. 4. Add log if calling pwrap_write or pwrap_read fail. 5. Increase timeout time to resolve unexpected timeout. BUG=b:127405695 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28mediatek/mt8183: Add RTC supportRan Bi
This patch implements RTC initialization. 1. initialization dcxo 2. rtc clock using dcxo 32k 3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN 4. rtc register initialization 5. refactor the driver common part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-29mediatek: Separate WDT reset function from WDT driverTristan Shieh
Separate WDT reset function from WDT driver, then we can use the common WDT driver and have a board-specific reset function on different boards. In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config "MISSING_BOARD_RESET" in Kukui to pass the build for now. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot; Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31121 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05mediatek: Share GPIO external interrupts (EINT) code among similar SoCsChuanjia Liu
Refactor GPIO EINT code which can be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot Change-Id: Ib01b43cf1aa4082d7d968fe1ef82f75e8cf05b8b Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16mediatek: Refactor PMIC wrapper code among similar SoCsTristan Shieh
Refactor PMIC wrapper code which will be reused among similar SoCs. Move reusable code into the common folder. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>