diff options
| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-04-22 13:34:04 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-04-26 02:42:33 +0000 |
| commit | 6968782ac0309bd0178eb4a421355e1bb7bf3a92 (patch) | |
| tree | f50a54a2fe0c3a800044a6148b82816d7ad4f669 /src/soc/mediatek/common | |
| parent | fdad5ad74baea3f29495126c31159a9bcb352d79 (diff) | |
soc/mediatek/mt8195: Initialize watchdog
MT8195 requires writing speical value to mode register to clear
status register. This value is invalid on other platforms. We can
do this safely in the common watchdog driver.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/common')
| -rw-r--r-- | src/soc/mediatek/common/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/mediatek/common/include/soc/wdt.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/common/wdt.c | 5 |
3 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 543bc02d13..29cd2109f9 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -29,4 +29,9 @@ config MEMORY_TEST This option enables memory basic compare test to verify the DRAM read or write is as expected. +config CLEAR_WDT_MODE_REG + bool + help + Enable this option to clear WTD mode register explicitly. + endif diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index 44ab5c7700..5847d4953f 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -21,6 +21,7 @@ struct mtk_wdt_regs { /* WDT_MODE */ enum { MTK_WDT_MODE_KEY = 0x22000000, + MTK_WDT_CLR_STATUS = 0x230001FF, MTK_WDT_MODE_DUAL_MODE = 1 << 6, MTK_WDT_MODE_IRQ = 1 << 3, MTK_WDT_MODE_EXTEN = 1 << 2, diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index e9edb48ef5..44a9ce50b6 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -9,9 +9,12 @@ int mtk_wdt_init(void) { uint32_t wdt_sta; - /* Write Mode register will clear status register */ + /* Writing mode register will clear status register */ wdt_sta = read32(&mtk_wdt->wdt_status); + if (CONFIG(CLEAR_WDT_MODE_REG)) + write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); + printk(BIOS_INFO, "WDT: Last reset was "); if (wdt_sta & MTK_WDT_STA_HW_RST) { printk(BIOS_INFO, "hardware watchdog\n"); |