diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-04-27 21:20:06 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-05 07:36:48 +0000 |
| commit | 47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed (patch) | |
| tree | fe8a77a9c18fbadb256a274797c11cf554f7db18 /src/soc/mediatek/common | |
| parent | 0575778667e9802a3af9766f459f43f833330d88 (diff) | |
soc/mediatek: Move the common part of SPI drivers to common/
The SPI drivers can be shared by MT8183, MT8192 and MT8195.
TEST=emerge-{oak, kukui, asurada, cherry} coreboot;
verified on Cherry P0
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/common')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/spi_common.h | 30 | ||||
| -rw-r--r-- | src/soc/mediatek/common/spi.c | 19 |
2 files changed, 34 insertions, 15 deletions
diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 918f3d2717..a70b9b1e1a 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -3,21 +3,12 @@ #ifndef MTK_COMMON_SPI_H #define MTK_COMMON_SPI_H +#include <device/mmio.h> #include <soc/gpio_base.h> #include <spi-generic.h> #include <types.h> enum { - SPI_CFG1_CS_IDLE_SHIFT = 0, - SPI_CFG1_PACKET_LOOP_SHIFT = 8, - SPI_CFG1_PACKET_LENGTH_SHIFT = 16, - - SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT, - SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT, - SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT, -}; - -enum { SPI_CMD_ACT_SHIFT = 0, SPI_CMD_RESUME_SHIFT = 1, SPI_CMD_RST_SHIFT = 2, @@ -59,7 +50,24 @@ enum spi_pad_mask { SPI_PAD_SEL_MASK = 0x3 }; -struct mtk_spi_regs; +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); struct mtk_spi_bus { struct spi_slave slave; diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index afc64c6bb7..f465027ab9 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -34,6 +34,19 @@ static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave) return &spi_bus[slave->bus]; } +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, + u32 cs_ticks, unsigned int tick_dly) +{ + SET32_BITFIELDS(®s->spi_cfg0_reg, SPI_CFG_CS_HOLD, cs_ticks - 1, + SPI_CFG_CS_SETUP, cs_ticks - 1); + + SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1, + SPI_CFG_SCK_HIGH, sck_ticks - 1); + + SET32_BITFIELDS(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly, + SPI_CFG1_CS_IDLE, cs_ticks - 1); +} + static void spi_sw_reset(struct mtk_spi_regs *regs) { setbits32(®s->spi_cmd_reg, SPI_CMD_RST_EN); @@ -121,10 +134,8 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out, else size = MIN(*bytes_in, *bytes_out); - clrsetbits32(®s->spi_cfg1_reg, - SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, - ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | - (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); + SET32_BITFIELDS(®s->spi_cfg1_reg, SPI_CFG1_PACKET_LENGTH, size - 1, + SPI_CFG1_PACKET_LOOP, 0); if (*bytes_out) { const uint8_t *outb = (const uint8_t *)out; |