soc/mediatek: Move the common part of SPI drivers to common/

The SPI drivers can be shared by MT8183, MT8192 and MT8195.

TEST=emerge-{oak, kukui, asurada, cherry} coreboot;
     verified on Cherry P0

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

8 files changed, 68 insertions, 155 deletions

diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h
index 918f3d2717..a70b9b1e1a 100644
--- a/src/soc/mediatek/common/include/soc/spi_common.h
+++ b/src/soc/mediatek/common/include/soc/spi_common.h
@@ -3,21 +3,12 @@
 #ifndef MTK_COMMON_SPI_H
 #define MTK_COMMON_SPI_H
 
+#include <device/mmio.h>
 #include <soc/gpio_base.h>
 #include <spi-generic.h>
 #include <types.h>
 
 enum {
-	SPI_CFG1_CS_IDLE_SHIFT = 0,
-	SPI_CFG1_PACKET_LOOP_SHIFT = 8,
-	SPI_CFG1_PACKET_LENGTH_SHIFT = 16,
-
-	SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT,
-	SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT,
-	SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT,
-};
-
-enum {
 	SPI_CMD_ACT_SHIFT = 0,
 	SPI_CMD_RESUME_SHIFT = 1,
 	SPI_CMD_RST_SHIFT = 2,
@@ -59,7 +50,24 @@ enum spi_pad_mask {
 	SPI_PAD_SEL_MASK = 0x3
 };
 
-struct mtk_spi_regs;
+/* SPI peripheral register map. */
+typedef struct mtk_spi_regs {
+	uint32_t spi_cfg0_reg;
+	uint32_t spi_cfg1_reg;
+	uint32_t spi_tx_src_reg;
+	uint32_t spi_rx_dst_reg;
+	uint32_t spi_tx_data_reg;
+	uint32_t spi_rx_data_reg;
+	uint32_t spi_cmd_reg;
+	uint32_t spi_status0_reg;
+	uint32_t spi_status1_reg;
+	uint32_t spi_pad_macro_sel_reg;
+	uint32_t spi_cfg2_reg;
+	uint32_t spi_tx_src_64_reg;
+	uint32_t spi_rx_dst_64_reg;
+} mtk_spi_regs;
+
+check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24);
 
 struct mtk_spi_bus {
 	struct spi_slave slave;
diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c
index afc64c6bb7..f465027ab9 100644
--- a/src/soc/mediatek/common/spi.c
+++ b/src/soc/mediatek/common/spi.c
@@ -34,6 +34,19 @@ static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave)
 	return &spi_bus[slave->bus];
 }
 
+void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks,
+			u32 cs_ticks, unsigned int tick_dly)
+{
+	SET32_BITFIELDS(&regs->spi_cfg0_reg, SPI_CFG_CS_HOLD, cs_ticks - 1,
+			SPI_CFG_CS_SETUP, cs_ticks - 1);
+
+	SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1,
+			SPI_CFG_SCK_HIGH, sck_ticks - 1);
+
+	SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly,
+			SPI_CFG1_CS_IDLE, cs_ticks - 1);
+}
+
 static void spi_sw_reset(struct mtk_spi_regs *regs)
 {
 	setbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
@@ -121,10 +134,8 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out,
 	else
 		size = MIN(*bytes_in, *bytes_out);
 
-	clrsetbits32(&regs->spi_cfg1_reg,
-		     SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK,
-		     ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) |
-		     (0 << SPI_CFG1_PACKET_LOOP_SHIFT));
+	SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_PACKET_LENGTH, size - 1,
+			SPI_CFG1_PACKET_LOOP, 0);
 
 	if (*bytes_out) {
 		const uint8_t *outb = (const uint8_t *)out;
diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h
index 47da0f80cd..b267aa0d92 100644
--- a/src/soc/mediatek/mt8173/include/soc/spi.h
+++ b/src/soc/mediatek/mt8173/include/soc/spi.h
@@ -7,32 +7,16 @@
 
 #define SPI_BUS_NUMBER 1
 
-/* SPI peripheral register map. */
-typedef struct mtk_spi_regs {
-	uint32_t spi_cfg0_reg;
-	uint32_t spi_cfg1_reg;
-	uint32_t spi_tx_src_reg;
-	uint32_t spi_rx_dst_reg;
-	uint32_t spi_tx_data_reg;
-	uint32_t spi_rx_data_reg;
-	uint32_t spi_cmd_reg;
-	uint32_t spi_status0_reg;
-	uint32_t spi_status1_reg;
-	uint32_t spi_pad_macro_sel_reg;
-} mtk_spi_regs;
+#define GET_SCK_REG(x) x->spi_cfg0_reg
 
-check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24);
+DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0)
+DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8)
+DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 23, 16)
+DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 24)
 
-enum {
-	SPI_CFG0_SCK_HIGH_SHIFT = 0,
-	SPI_CFG0_SCK_LOW_SHIFT = 8,
-	SPI_CFG0_CS_HOLD_SHIFT = 16,
-	SPI_CFG0_CS_SETUP_SHIFT = 24,
-};
-
-enum {
-	SPI_CFG1_TICK_DLY_SHIFT = 30,
-	SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT,
-};
+DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
+DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
 
 #endif
diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c
index 4abd650bd9..d3c8ad4cbb 100644
--- a/src/soc/mediatek/mt8173/spi.c
+++ b/src/soc/mediatek/mt8173/spi.c
@@ -26,20 +26,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus,
 	gpio_set_mode(GPIO(MSDC2_CMD), 0);
 }
 
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
-			unsigned int tick_dly)
-{
-	write32(&regs->spi_cfg0_reg,
-		((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) |
-		((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) |
-		((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
-		((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
-	clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK |
-		     SPI_CFG1_TICK_DLY_MASK,
-		     (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
-		     ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
-}
-
 static const struct spi_ctrlr spi_flash_ctrlr = {
 	.max_xfer_size = 65535,
 	.flash_probe = mtk_spi_flash_probe,
diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h
index 5efa618d39..5bc70e5d36 100644
--- a/src/soc/mediatek/mt8183/include/soc/spi.h
+++ b/src/soc/mediatek/mt8183/include/soc/spi.h
@@ -7,39 +7,18 @@
 
 #define SPI_BUS_NUMBER 6
 
-/* SPI peripheral register map. */
-typedef struct mtk_spi_regs {
-	uint32_t spi_cfg0_reg;
-	uint32_t spi_cfg1_reg;
-	uint32_t spi_tx_src_reg;
-	uint32_t spi_rx_dst_reg;
-	uint32_t spi_tx_data_reg;
-	uint32_t spi_rx_data_reg;
-	uint32_t spi_cmd_reg;
-	uint32_t spi_status0_reg;
-	uint32_t spi_status1_reg;
-	uint32_t spi_pad_macro_sel_reg;
-	uint32_t spi_cfg2_reg;
-	uint32_t spi_tx_src_64_reg;
-	uint32_t spi_rx_dst_64_reg;
-} mtk_spi_regs;
-
-check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24);
-
-enum {
-	SPI_CFG0_CS_HOLD_SHIFT = 0,
-	SPI_CFG0_CS_SETUP_SHIFT = 16,
-};
-
-enum {
-	SPI_CFG2_SCK_LOW_SHIFT = 0,
-	SPI_CFG2_SCK_HIGH_SHIFT = 16,
-};
-
-enum {
-	SPI_CFG1_TICK_DLY_SHIFT = 29,
-	SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT,
-
-};
+#define GET_SCK_REG(x) x->spi_cfg2_reg
+
+DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
+
+DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
+
+DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
+DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
+
 
 #endif
diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c
index 87362dc33c..c172f377da 100644
--- a/src/soc/mediatek/mt8183/spi.c
+++ b/src/soc/mediatek/mt8183/spi.c
@@ -103,23 +103,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
 		gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
 }
 
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
-			unsigned int tick_dly)
-{
-	write32(&regs->spi_cfg0_reg,
-		((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
-		((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
-
-	write32(&regs->spi_cfg2_reg,
-		((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
-		((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
-
-	clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
-		     SPI_CFG1_CS_IDLE_MASK,
-		     (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
-		     ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
-}
-
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{
 		.ctrlr = &spi_ctrlr,
diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h
index 034fa3570a..db3ba21613 100644
--- a/src/soc/mediatek/mt8192/include/soc/spi.h
+++ b/src/soc/mediatek/mt8192/include/soc/spi.h
@@ -7,38 +7,17 @@
 
 #define SPI_BUS_NUMBER 8
 
-/* SPI peripheral register map. */
-typedef struct mtk_spi_regs {
-	uint32_t spi_cfg0_reg;
-	uint32_t spi_cfg1_reg;
-	uint32_t spi_tx_src_reg;
-	uint32_t spi_rx_dst_reg;
-	uint32_t spi_tx_data_reg;
-	uint32_t spi_rx_data_reg;
-	uint32_t spi_cmd_reg;
-	uint32_t spi_status0_reg;
-	uint32_t spi_status1_reg;
-	uint32_t spi_pad_macro_sel_reg;
-	uint32_t spi_cfg2_reg;
-	uint32_t spi_tx_src_64_reg;
-	uint32_t spi_rx_dst_64_reg;
-} mtk_spi_regs;
-
-check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24);
-
-enum {
-	SPI_CFG0_CS_HOLD_SHIFT = 0,
-	SPI_CFG0_CS_SETUP_SHIFT = 16,
-};
-
-enum {
-	SPI_CFG2_SCK_LOW_SHIFT = 0,
-	SPI_CFG2_SCK_HIGH_SHIFT = 16,
-};
-
-enum {
-	SPI_CFG1_TICK_DLY_SHIFT = 29,
-	SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT,
-};
+#define GET_SCK_REG(x) x->spi_cfg2_reg
+
+DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
+
+DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
+
+DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
+DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
 
 #endif
diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c
index f7a8756d1a..b5abc85b83 100644
--- a/src/soc/mediatek/mt8192/spi.c
+++ b/src/soc/mediatek/mt8192/spi.c
@@ -112,23 +112,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
 		gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
 }
 
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
-			unsigned int tick_dly)
-{
-	write32(&regs->spi_cfg0_reg,
-		((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
-		((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
-
-	write32(&regs->spi_cfg2_reg,
-		((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
-		((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
-
-	clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
-		     SPI_CFG1_CS_IDLE_MASK,
-		     (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
-		     ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
-}
-
 static const struct spi_ctrlr spi_flash_ctrlr = {
 	.max_xfer_size = 65535,
 	.flash_probe = mtk_spi_flash_probe,