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The CedarIsland FSP Integration recommends locking down some things.
Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is required for CbNT.
Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is required for CBnT.
Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the
source statement.
Also, no kconfig files under src/soc/intel/common/basecode/. Clean
that up.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Now that CHAP device is declared in chipset devicetree, hook it up to
devicetree configuration.
Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Structure with chromeos_acpi_t is expected to have size
0x1000. Only ones with device_nvs_t have size 0x2000.
Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Rename to graphics_soc_panel_init, to more accurately convey
operations performed by the function. Guard execution so we
don't attempt to reconfigure the panel after FSP has already
done so.
This fixes FSP/GOP display init on APL/GLK, which was broken by
attempting to configure the panel after FSP had already done so.
Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Isochronous operation negatively impacts memory performance, as
per Intel MLC (Memory Latency Checker) benchmark results. Thus,
disable isochronous operation, like analogous UEFI firmware does.
The MLC results after disabling isoch:
"--max_bandwidth"
ALL Reads : 106948.17
3:1 Reads-Writes : 101580.46
2:1 Reads-Writes : 100523.26
1:1 Reads-Writes : 99059.44
Stream-triad like : 97762.47
"--peak_injection_bandwidth"
ALL Reads : 105724.3
3:1 Reads-Writes : 100655.8
2:1 Reads-Writes : 99463
1:1 Reads-Writes : 98708
Stream-triad like : 91515
The MLC results before disabling isoch:
"--max_bandwidth"
ALL Reads : 88824.96
3:1 Reads-Writes : 94820.81
2:1 Reads-Writes : 94867.53
1:1 Reads-Writes : 92567.36
Stream-triad like : 91900.43
"--peak_injection_bandwidth"
ALL Reads : 88859.6
3:1 Reads-Writes : 94064
2:1 Reads-Writes : 94186.2
1:1 Reads-Writes : 92516.1
Stream-triad like : 85147.4
TEST=On OCP Delta Lake, verify that MLC benchmark results have
improved.
Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48738
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the unused SOC_INTEL_COMMON_ACPI Kconfig option.
Change-Id: Id62cd44e0f7e4175ae65c9388569231d5c8c1fbc
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Remove the unnecessary header file includes.
Change-Id: I0d849cb236f304b87332aa64b2f10c73cad2d4dd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Port commit ba75c4c (soc/intel/tigerlake: Enable support for
extended BIOS window) for Alderlake
Change-Id: Iaa8464d45884de433cca4f6a250cdd8d4c8f3661
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Port commit 237afda (src/soc/intel/tigerlake: Add SPI DMI Destination ID)
into Alderlake.
Change-Id: Ia0b465d405ab3c70b7d4094d32c182cab30fe531
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Commit 56fcfb5 misused the PCH_DEVFNs passed to the XHCI elog driver, by
passing them directly to pci_s_read_config32. This is incorrect, as it
is the wrong PCI devfn encoding to pass to that function.
BUG=b:175996770
TEST=abuild
Change-Id: Id7c146c1f50ee64a725bd50f9f11a7f159013a2b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Current implementation uses CPUID 0Bh function that returns the number
of logical cores of requested level. The problem with this approach is
that this value doesn't change when HyperThreading is disabled (it's in
the Intel docs), so it breaks generate_cpu_entries() because `numcpus`
ends up being zero due to integer division truncation.
- Use MSR 0x35 instead, which returns the correct number of logical
processors with and without HT.
- Use cpu_read_topology() to gather the required information
Tested on Prodrive Hermes, the ACPI code is now generated even with
HyperThreading disabled.
Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Following up 3ccae2b7, this patch adds Iccmax and AC/DC
loadlines and iPL2 for CML-S CPUs. The information is from
CML EDS volume 1, doc #606599 and pdg #610244.
Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.
Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the common block ACPI to further reduce the duplicate code.
Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Don't depend on the MTRR setup left over from FSP-M ExitTempRam.
Change-Id: I299123b3cd3c37b4345102c20fda77bf261892a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: I42ddea2c04bf1ecb2466db3d56d15d51bda486c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Add a hook for SOCs to provide an IOAPIC MADT table. If the
SOC doesn't provide a table then a standard setting is used.
Change-Id: Ic818a634e4912d88ef93971deb4da5ab708c9020
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change static calculate_power() function to global and update the name
to common_calculate_power_ratio() for SOC ACPI code use.
Change-Id: I0e2d118ad52b36859bfc6029b7dee946193841f4
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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Also tidy up some adjacent comments.
Change-Id: I2e881900a52e42ab3f43ffe96cfbdcc63ff02e23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The `azalia_set_bits` will mask out all bits, so just use zero for
clarity. The resulting behavior is the same in both cases.
Change-Id: I27777f1e836fa973859629d48964060bec02c87a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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coreboot already unconditionally enables CLKRUN_EN in SoC common code.
Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.
Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I346040eb6531dac6c066a96cd73033aa17f026d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This function is equivalent to `azalia_find_verb` in its current form,
so replace them. Also, adapt and move the function description comment.
Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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There's many copies of this function in the tree. Make the copy in
azalia_device.c non-static and rename it to `azalia_set_bits`, then
replace all other copies with it. Since azalia_device.c is only built
when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary.
This has the side-effect of building hda_verb.c from the mainboard
directory. If this patch happens to break audio on a mainboard, it's
because its hda_verb.c was always wrong but wasn't being compiled.
Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on
xeon_sp and denverton_ns. This allows to set test config UPDs from
mainboard code as well.
Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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On SKX FSP-M does not return if this is set too early.
Tested on OCP/Tiogapass, boots.
Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The region top_of_ram -> cbmem_top is used by FSP and cbmem, but is
also just regular DRAM. Marking it as such improves the final MTRR
solution a lot and fixes MTRR starvation depending on the setup.
Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47868
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.
During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.
Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.
Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.
Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Tigerlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Drawlet
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialization as HMRFPO_ENABLE HECI command (which is used by
cse_fw_sync()) is expected to be executed after DRAM initialization. With
this change, it improves the cold boot time by ~154ms.
Test=Verified on JSL and TGL platforms
BUG=b:174694480
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch modifies CSE Lite driver to use 'if' C-lanugage construct
instead of #if macro and adds 'if SOC_INTEL_CSE_RW_UPDATE' to the prompts
of CSE Update related KConfigs to prevent appearing them in the menu.
TEST=Built the code for drawcia
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob
and CSE RW boot are different.
TEST=Verified on drawcia.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also,
use SMM_TSEG_SIZE in place of a magic number.
Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.
Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Unset devicetree settings default to zero, so the devicetree setting can
be removed. Looks like no one needs it anyway.
Change-Id: Iad94538c5465347b37a99c6c9f20988168661593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Only Google Eve uses a non-zero value, but it overwrites in C code.
Drop the devicetree setting, since no mainboard uses it.
Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TESTED on ocp/tiagopass: Microcode updates are properly applied (via
FIT). Tested with out of tree patches to report the revision.
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The value for this setting is not used anywhere. Drop it.
Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48571
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure DPR to span the region between cbmem_top and TSEG base.
This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Currently it's not possible to add multiple graphics drivers into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics drivers can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple independent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace all duplications of fill_fb_framebuffer and provide a single one
in edid_fill_fb.c. Should not change the current behaviour as still only
one graphic driver can be active at time.
Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I5f5da8dfcec7dd35981611830b555cab5d6af3e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48572
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I6ce43071c95eeb41c35ddfdb734db52d863ea8e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: Ia928c4bbddd1c160228a9af8faf5d4be787f73f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: Ia9c8347cad479c6b4e678630921f768e0fdee6d9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Add LPC/eSPI device ID of Emmitsburg (EMB) for setting LPC resources.
Refer to Emmitsburg PCH EDS (606161).
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie5a5d9ba7e4f664ada2dae2294d6e4d0280a2157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update IRQ routing settings.
Extra reference:
- ACPI spec 6.2.13 _PRT
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Update USB & PCIe devices in ASL files as per EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values
for USB_PORT_MID.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48541
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS.
Also update device function number for GSPI #2 in asl file.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If166fefe567a857ca29527d0367197139efbf6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For EHL, SpiProtectionMode is added to HFSTS register #1.
The original Manufacturing Mode is detected via FpfSocConfigLock
instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode,
and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates PCI device definition according to EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skip the ACPI UART debug table if common block UART isn't selected.
Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48247
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the southbridge_write_acpi_tables declaration from acpi.h to common
lpc_lib.h, as common LPC is always the caller. This removes a duplicate
declaration since all soc/intel devices use common LPC, but not all use
common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c
with the other acpi functions.
Note that this would have the reverse problem if there is ever a non-common
LPC device.
Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS
or North XHCI block has a similar enough PCI MMIO structure to make this
code mostly reusable.
1) Rename everything to drop the `pch_` prefix
2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI
controller
3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI
controller
BUG=b:172279037
TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via
EC; type on keyboard, verify it wakes up, eventlog contains:
39 | 2020-12-10 09:40:21 | S0ix Enter
40 | 2020-12-10 09:40:42 | S0ix Exit
41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1
42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109
which verifies it still functions for the PCH XHCI controller
Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there
isn't anything uncommon with the soc NVS, use the Intel common NVS.
This covers the NVS cases of common code used by xeon_sp. Update
the mainboards for this change.
Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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When EHL initial mainboard patch is uploaded, there are some build
errors caused by EHL soc codes. Here are the fixes:
1. include gpio_op.asl to resolve undefined variables in scs.asl
2. remove unused variables in fsp_params.c
3. rearrage sequences of #includes to fix build dependency of
soc/gpio_defs.h in intelblocks/gpio.h
4. add the __weak to mainboard_memory_init_params function
5. add the missing _len as per this patch changes
https://review.coreboot.org/c/coreboot/+/45873
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support to lock down the DMI configuration
in dmi_lockdown_cfg() by setting Secure Register Lock (SRL)
bit in DMI control register.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move definitions of DMI control register and Secure Register
Lock (SRL) bit into common/block/dmi driver header file.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables support for extended BIOS window by selecting
FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW and providing base and size of the
extended window in host address space.
BUG=b:171534504
Cq-Depend: chromium:2566231
Change-Id: I039155506380310cf867f5f8c5542278be40838a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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This change adds support to Lock down the configuration of
extended BIOS region. This is done as part of
fast_spi_lockdown_cfg() so that it is consistent with the
other lockdown.
Change includes:
1. New helper function fast_spi_lock_ext_bios_cfg() added that
will basically set EXT_BIOS_LOCK.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables caching for extended BIOS region.
Currently, caching is enabled for the standard BIOS region
upto a maximum of 16MiB using fast_spi_cache_bios_region,
used the same function to add the support for caching for
extended BIOS region as well.
Changes include:
1. Add a new helper function fast_spi_cache_ext_bios_window()
which calls fast_spi_ext_bios_cache_range() which calls
fast_spi_get_ext_bios_window() to get details about the
extended BIOS window from the boot media map and checks for
allignment and set mtrr.
2. Make a call to fast_spi_cache_ext_bios_region() from
fast_spi_cache_bios_region ().
3. Add new helper function fast_spi_cache_ext_bios_postcar()
which does caching ext BIOS region in postcar similar to 1.
4. If the extended window is used, then it enables caching
for this window similar to how it is done for the standard
window.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47991
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds the SPI-DMI Destination ID for tigerlake
soc. This is needed for enabling support for extended
BIOS region. Also, implements a SOC helper function
soc_get_spi_dmi_destination_id() which returns SPI-DMI
Destination id.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0b6a8af0c1e79fa668ef2f84b93f3bbece59eb6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change enables support for configuration of extended BIOS
region decode window. This configuration needs to be performed
as early as possible in the boot flow. This is required to
ensure that any access to the SPI flash region below 16MiB in
coreboot is decoded correctly. The configuration for the extended
BIOS window if required is done as part of fast_spi_early_init().
Changes include:
1. Make a call to fast_spi_enable_ext_bios() before the bus master
and memory space is enabled for the fast SPI controller.
2. Added a helper function fast_spi_enable_ext_bios() which calls
fast_spi_get_ext_bios_window() to get details about the extended
BIOS window from the boot media map.
3. Depending upon the SPI flash device used by the mainboard and
the size of the BIOS region in the flashmap, this function will
have to perform this additional configuration only if the BIOS
region is greater than 16MiB
4. Adddditionally, set up the general purpose memory range
registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47990
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change allows configuring the General Purpose
Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality:
1. Add a helper function dmi_enable_gpmr which takes as input base,
limit and destination ID to configure in general purpose memory range
registers and then set the GPMR registers in the next available
free GMPR and enable the decoding.
2. Add helper function get_available_gpmr which returns available free
GPMR.
3. This helper function can be utilized by the fast SPI driver to
configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds details about the memory map windows to translate
addresses between SPI flash space and host address space to coreboot
tables. This is useful for payloads to setup the translation using the
decode windows already known to coreboot. Until now, there was a
single decode window at the top of 4G used by all x86
platforms. However, going forward, platforms might support more decode
windows and hence in order to avoid duplication in payloads this
information is filled in coreboot tables.
`lb_spi_flash()` is updated to fill in the details about these windows
by making a call to `spi_flash_get_mmap_windows()` which is
implemented by the driver providing the boot media mapping device.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change reserves the window used for extended BIOS decoding as a
fixed MMIO resource using read_resources callback in systemagent
driver. This ensures that the resource allocator does not allocate
from this window.
Additionally, this window is also marked as fixed memory region in
_CRS for PNP0C02 device.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I42b5a0ebda2627f72b825551c566cd22dbc5cca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change enables support for a custom boot media device in fast SPI
controller driver if the platform supports additional decode window
for mapping BIOS regions greater than 16MiB. Following new Kconfigs
are added:
1. FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW: SoC can select this to indicate
support for extended BIOS window.
2. EXT_BIOS_WIN_BASE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is
selected, this provides the base address of the host space that is
reserved for mapping the extended window.
3. EXT_BIOS_WIN_SIZE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is
selected, this provides the size of the host space reserved for
mapping extended window.
If platform indicates support for extended BIOS decode window,
cbfstool add command is provided additional parameters for the decode
window using --ext-win-base and --ext-win-size.
It is the responsibility of the mainboard fmap author to ensure that
the sections in the BIOS region do not cross 16MiB boundary as the
host space windows are not contiguous. This change adds a build time
check to ensure no sections in FMAP cross the 16MiB boundary.
Even though the platform supports extended window, it depends upon the
size of BIOS region (which in turn depends on SPI flash size) whether
and how much of the additional window is utilized at runtime. This
change also provides helper functions for rest of the coreboot
components to query how much of the extended window is actually
utilized.
BUG=b:171534504
Change-Id: I1b564aed9809cf14b40a3b8e907622266fc782e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48396
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Align the SATA mode names with soc/skl providing a consistent API.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The Skylake FSP isn't used by coreboot anymore. Therefore, drop the
misleading comment and the "KBLFSP" extension from the names of these
enums.
Also, drop the "MODE" extension to make their names shorter in general,
since it doesn't add any more value.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48376
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates the translated region device (xlate_region_dev) to
support multiple translation windows from the 1st address space to
2nd address space. The address spaces described by the translation
windows can be non-contiguous in both spaces. This is required so that
newer x86 platforms can describe memory mapping of SPI flash into
multiple decode windows in order to support greater than 16MiB of
memory mapped space.
Since the windows can be non-contiguous, it introduces new
restrictions on the region device ops - any operation performed on the
translated region device is limited to only 1 window at a time. This
restriction is primarily because of the mmap operation. The caller
expects that the memory mapped space is contiguous, however, that is
not true anymore. Thus, even though the other operations (readat,
writeat, eraseat) can be updated to translate into multiple operations
one for each access device, all operations across multiple windows are
prohibited for the sake of consistency.
It is the responsibility of the platform to ensure that any section
that is operated on using the translated region device does not span
multiple windows in the fmap description.
One additional difference in behavior is xlate_region_device does not
perform any action in munmap call. This is because it does not keep
track of the access device that was used to service the mmap
request. Currently, xlate_region_device is used only by memory mapped
boot media on the backend. So, not doing unmap is fine. If this needs
to be changed in the future, xlate_region_device will have to accept a
pre-allocated space from the caller to keep track of all mapping
requests.
BUG=b:171534504
Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47658
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Probabilistic interrupt storm is observed while kernel is configuring
the GPIO for SD card CD pin. The root cause is that the macro
PAD_CFG_GPI_GPIO_DRIVER isn't configuring trigger as PAD_TRIG(OFF).
The way GPIO interrupts are handled is:
1. Pad is configured as input in coreboot.
2. Pad IRQ information is passed in ACPI tables to kernel.
3. Kernel configures the required pad trigger.
Therefore, PAD_TRIG(OFF) should be added in PAD_CFG_GPI_GPIO_DRIVER
to turn off the trigger while pad is configured as input in coreboot
and then let kernel to configure the required pad trigger.
BUG=b:174336541
TEST=Run 1500 reboot iterations successfully without any interrupts
storm.
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com>
Change-Id: Icc805f5cfe45e5cc991fb0561f669907ac454a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Change-Id: Id014828d282350bcb1f4de295d5cfb72b6950634
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch removes 1 unnecessary whitespace and add 1 whitespace into IA
common car code block.
Change-Id: I3690b5f219f5326cfca7956f21132062aa89648e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.
Note: Currently, this only works with the AST PCI bridge disabled or the
VGA jumper set to disabled on coreboot, while it works on vendor
in any case. The reason for this is still unclear.
Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
instead of just PC3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The patch modifies KConfig behaviour if CSE Lite SKU is integrated into
the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents
writing to ME region but keeps read access enabled. Since CSE Lite driver
checks the signature of RW partition to identify the interrupted CSE
firmware update, so host must have read access to the ME region. Also, the
patch modifies the KConfig's help text to reflect the change.
When CSE Lite SKU is integrated, master access permissions:
FLMSTR1: 0x002007ff (Host CPU/BIOS)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: enabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: enabled
Host CPU/BIOS Region Read Access: enabled
Flash Descriptor Read Access: enabled
BUG=b:174118018
TEST=Built and verified the access permissions.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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This patch renames the cbfs_boot_load_file() to cbfs_load() to
avoid the build errors for cselite and align with the new changes
to API https://review.coreboot.org/c/coreboot/+/39304 .
Change-Id: I717f0a3291f781cc3cf60aae88e7479762ede9f9
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch exposes acoustic noise mitigation related UPDs/configuration
to be filled from devicetree.
For each variant, we might have different values for various parameters.
Filling it from devicetree will allow us to fill separate values for
each board/variant.
Note that since JasperLake only has one VR, we're only filling index 0
for slew rate and FastPkgCRampDisable.
BUG=b:162192346
BRANCH=dedede
TEST=code compilation is successful and values from devicetree are
getting reflected in UPDs
Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Don't use the common block acpi.h when we aren't using the
COMMON_ACPI config. Fixes a dependency build issue in an upcoming
commit.
Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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This patch adds the PCI device ID for Alderlake
CPU xHCI.
Change-Id: I4074a81aa9be2ef3a0956da08bece32a613415ab
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Refer pci_devs.h naming to align chipset.cb.
Correct thc0, thc1 and add cnvi_bt.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables the PCH HDA device based on the devicetree
configuration.
Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add NMI_EN and NMI_STS registers, so they can be configured for using
NMI gpios.
References:
- CMP-LP: Intel doc# 615146-1.2
- CMP-H: Intel doc# 620855-002
- SPT-H: Intel doc# 332691-003
- SPT-LP: Intel doc# 334659-005
- CNP-H: Intel doc# 337868-002
Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before
but now makes the Linux kernel complain about a NMI.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Especially server boards, like the Supermicro X11SSM-F, often have a NMI
button and NMI functionality that can be triggered via IPMI. The purpose
of this is to cause the OS to create a system crashdump from a hang
system or for debugging.
Add code for enabling NMI interrupts on GPIOs configured with
PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI
function was copied and adapted. The `pad_community` struct gained two
variables for the registers.
Also register the NMI for LINT1 in the MADT in accordance to ACPI spec.
Test: Linux detects the NMI correctly in dmesg:
[ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, when a SMI GPIO gets configured, the whole status register is
get written back and thus, all SMIs get reset.
Do it right and reset only the correspondig status bit of the GPIO to be
configured.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48089
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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