diff options
| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-12-12 22:42:41 +0000 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-12-17 20:05:49 +0000 |
| commit | ac857ca3b166d385caa4faf62b4f1b8fc3b3f2da (patch) | |
| tree | 7dadb9454b084736d7a931b8cb98c5da5dfe11db /src/soc/intel | |
| parent | a04400d1aac35299568774304cf9664188570d07 (diff) | |
soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
coreboot already unconditionally enables CLKRUN_EN in SoC common code.
Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.
Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 5 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c9519cdc29..ef16f388d7 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -338,7 +338,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; - params->PchPmLpcClockRun = config->PmConfigPciClockRun; params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index f4744c9631..7d9d93460c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -377,11 +377,6 @@ struct soc_intel_skylake_config { } PmConfigSlpAMinAssert; /* - * This member describes whether or not the PCI ClockRun feature of PCH - * should be enabled. Values 0: Disabled, 1: Enabled - */ - u8 PmConfigPciClockRun; - /* * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, * 1: Enabled */ |