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2021-09-10soc/intel/common/block/acpi: Move pep.asl to acpigenTim Wawrzynczak
There is a use-case for generating the AML bytecode at runtime for the Intel Power Engine device, which comes in a followup patch. BUG=b:185437326 TEST=verified on google/brya and google/dratini by dumping SSDT and verifying the PEPD device matches what was previously in the DSDT: Scope (\_SB.PCI0) { Device (PEPD) { Name (_HID, "INT33A1") Name (_CID, EisaId ("PNP0D80") Method (_DSM, 4, Serialized) { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x63 }) } If ((Local1 == One)) { Return (Package (0x01) { Package (0x03) { \NULL, Zero, Package (0x02) { Zero, Package (0x02) { 0xFF, Zero } } } }) } If ((Local1 == 0x02)){} If ((Local1 == 0x03)){} If ((Local1 == 0x04)){} If ((Local1 == 0x05)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (One) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (One) } If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () } } If ((Local1 == 0x06)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (Zero) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (Zero) } If (CondRefOf (\_SB.PCI0.RGPM)) { \_SB.PCI0.RGPM () } } Return (Buffer (One) { 0x00 }) } Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Set LpmStateEnableMask UPDTim Wawrzynczak
Use the get_supported_lpm_states() function to set the respective FSP UPD. TEST=with patchtrain on brya0, /sys/kernel/debug/pmc_core/substate_requirements shows only the substates that are applicable to the design (S0i2.0, S0i3.0). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Add get_adl_cpu_type functionTim Wawrzynczak
This function searches the known MCH device IDs for Alder Lake and returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or unknown. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-09soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBMAULIK V VAGHELA
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time. Increasing it over 4 KiB doesn't result in significant improvement, thus keeping the value at 4 KiB as of now. Timing data: Note that before Data is with 1 KiB block size. |------------------------------------------------------| | Stage | Block Size | Before | After | |finished loading body| 4 KiB | 205,187 | 189,947 | |finished loading body| 8 KiB | 205,187 | 188,708 | |finished loading body| 16 KiB | 205,187 | 188,085 | |finished loading body| 32 KiB | 205,187 | 187,793 | |------------------------------------------------------| BUG=b:188577893 BRANCH=None TEST=Boot time for Brya improves by 20 - 25 msec Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09soc/intel/alderlake: Enable Irms UPD for ADLRonak Kanabar
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit is set to non zero. It results VR TDC Input current to be treated as it is root mean square. This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit for TdcEnable UPD. BRANCH=None TEST=Build and boot brya with debug FSP and verify Irms UPD value from logs Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-09-09mb/ocp: Remove superfluous FSP header CPP inclusionArthur Heymans
This is already done in drivers/intel/fsp2_0/Makefile.inc. Change-Id: Idfd15d0a9d2cb15e613881f80bb25c18bd7454bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09intel/xeon_sp/cpx: Hook up public microcode releaseArthur Heymans
Change-Id: I7e575cb17e2004bd931f4fa1d05f17c4cdca29ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09soc/intel/broadwell: Set FADT `duty_offset` to 0Angel Pons
From ACPI specification, version 6.2 Errata A: A `duty_width` value of 0 indicates that processor duty cycle is not supported and the processor continuously runs at its base frequency. Because Broadwell sets `duty_width` to 0, processor duty cycle is not supported, and the value of `duty_offset` is ignored. For consistency with Lynx Point, set `duty_offset` to 0. Change-Id: I68cb85ec32a6cceda0cea29d76df6c6219b78a40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-08soc/intel/common: Avoid NULL pointer deferenceJohn Zhao
Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458068, 1458070, 1458971, 1458073, 1458075, 1458076 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ib88fa5f44dd33ad1ad2e763d79438b5c5b78acb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/{apl,glk}: Allow to select the primary graphics deviceMaxim Polyakov
Allow to select the primary graphics device between the IGD and the external PCIe GPU depending on the ONBOARD_VGA_IS_PRIMARY config. The option sets the priority only. This means that if a high priority is set for an external PCI device and it is not connected/not enabled, then the device with a lower priority will be used, in our case it is IGD. TEST = Set PRIMARY_PCI and boot Linux on the Kontron mAL10 [1] with the miniPCIe video adapter on the Silicon Motion SM750 controller. As a result, the display connected to an external GPU device shows the Tianocore logo + setup menu and the desktop. [1] https://review.coreboot.org/c/coreboot/+/39133 Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-09-06soc/intel/broadwell: Drop unused PCH PCI device macrosAngel Pons
Get rid of several unused PCH PCI device macros. These macros expand to a call to the `pcidev_path_on_root_debug()` function, which only exists to debug bad code. If needed, these macros should be reimplemented with the `pcidev_path_on_root()` function instead. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I366e064f3fe708b55fb381aee25b2795b1c61142 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-06soc/intel/adl: Move USB4 hotplug Kconfig to commonFurquan Shaikh
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` that can be selected by mainboard to reserve hotplug resources for USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped from soc/intel/alderlake and instead the newly added Kconfig is now used. This new Kconfig is added so that the same config can be used across different platforms. In following changes, this Kconfig is utilized by TGL as well. Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-05soc/intel/common/cse: Add argument for CSE fixed client addrRizwan Qureshi
There are multiple HECI clients in the CSE. heci_send_receive() is sending HECI messages to only the MKHI client. Add an argument to heci_send_receive() function to provide flexibility to the caller to select the client for which the message is intended. With the above change heci_send() and heci_receive() functions are no longer required to be exposed. In the follow-up patches there will be messages sent to one other client. BUG=None BRANCH=None TEST=Build and boot brya. HECI message send and receive to MKHI client is working. Also, MEI BUS message to disable bus is working. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/alderlake: Add tpch device information under dptfSumeet Pawnikar
Add tpch device information for thermal functionality under dptf for alderlake soc based platform. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/common: Add PMC IPC commands for FIVRSumeet Pawnikar
Add PMC IPC commands information for FIVR control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05soc/intel/jasperlake: Utilize vbt data size Kconfig optionSeunghwan Kim
Currently maximum VBT data size for Jasper Lake is 8KB, but Bugzzy would use VBT data over 8KB. This change makes use of Kconfig option to increase the maximum VBT data size to 9KB for Jasper Lake. BUG=b:194029827 BRANCH=dedede TEST=build and boot bugzzy and verify fw screen is loaded Change-Id: I0abe1ba5609b48a8a8b15f88bec28342ce26c78f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57201 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-05soc/intel/elkhartlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-05soc/intel/cannonlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-05soc/intel/jasperlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I10f859f30b260d012f0bc8755f32413d8b2cf267 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-03soc/intel/alderlake: set power limits dynamically for thermalSumeet Pawnikar
Set power limit values dynamically based on CPU TDP and PCI ID of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/intel/common: get tdp of CPU for different SKUsSumeet Pawnikar
Get tdp value of CPU for different SKUs based on PKG POWER MSR. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-03skylake: Default to `BOARD_TYPE_DESKTOP` for PCH-HAngel Pons
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H. Remove now-redundant mainboard code to set the `UserBd` UPD. Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03src/*: Specify type of `DIMM_MAX` onceAngel Pons
Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-02soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16Tim Crawford
TGL-H supports up to 8 cores (16 threads). Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01soc/intel/alderlake: Fix processor hang while plug unplug of TBT deviceSugnan Prabhu S
Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. BUG=b:194880254 Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-27broadwell: Drop weak `mainboard_fill_spd_data` definitionAngel Pons
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define this function accordingly. Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/broadwell: Move `mainboard_fill_spd_data`Angel Pons
Move the `mainboard_fill_spd_data` function out of romstage, in preparation to confine `pei_data` usage to as few files as possible. Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/denverton_ns: Ensure CPU device has a valid linkFurquan Shaikh
This change calls `add_more_links()` in `denverton_init_cpus()` if `dev->link_list` is NULL. This condition can occur if mainboard does not add any APIC device in the device tree. Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26soc/intel/tigerlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ice4c727f2b75893cd012345a556fd21d9807dfaa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/intel/alderlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/intel/common/block: Add PAM locking functionTim Wawrzynczak
Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit instead of the FSP, therefore add a function in the common code to do this. Source: ADL & TGL FSP integration guides Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-25soc/intel/cannonlake: Fix PCH-H IRQ constraintsAngel Pons
Cannon Point PCH-H does not implement the eMMC, I2C4 and I2C5 devices. Guard the IRQ constraints for these devices to prevent FSP assertions. Tested on Prodrive Hermes, debug FSP builds no longer fail to boot. Change-Id: I58674d1c3c5fe4535c022020674d48d6a5315bf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25soc/intel/tigerlake: Hook up ucode for TGL-HTim Crawford
Hook up microcode from 3rdparty repo for: - 06-8d-01 (CPUID signature: 0x806d1) Verified microcode blob was found in CBFS on system76/gaze16 (TGL-H). CBFS: Found 'cpu_microcode_blob.bin' @0x11700 size 0x18400 in mcache @0x76c2d0ac microcode: sig=0x806d1 pf=0x2 revision=0x2c Change-Id: Icf0d8bc700a73697f06503e9d1bb40ce26741cdf Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57067 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/broadwell: Move `pei_data` out of romstage.cAngel Pons
Prepare to confine all `pei_data` references in raminit.c and refcode.c so that mainboards don't need to know about its existence. Change-Id: I55793fa274f8100643855466b6cca486896fb2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/broadwell: Do early ME init a bit earlierAngel Pons
Do early ME init before adding the "start of raminit" timestamp. Change-Id: If8b27a9d4eb3b801e3e05dc2f2b95bf748985707 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55800 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/tigerlake: Add USB ACPI devices for PCH-HJeremy Soller
Change-Id: Ia1c1c3d172366ddcc8c194cb2e0b0c2fb2acf678 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add SPI_DMI_DESTINATION_ID for PCH-HJeremy Soller
Change-Id: I9a316b91b31166831f23eaf9e271a7d67ac4ccff Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Set UserBd to recommended default for PCH-HJeremy Soller
Change-Id: Ie8a28d8e03d7176df5409e6cb507a0a802ff026f Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56951 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-HJeremy Soller
Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add TGL-H PEG portsJeremy Soller
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCIe root ports for PCH-HJeremy Soller
Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H GPIO definitionsJeremy Soller
Add TGL-H GPIO definitions, based on existing TGL definitions and how CNP/CNP-H handles the split. Reference: - Intel doc 619207 - TigerLake FSP - linux/drivers/pinctrl/intel/pinctrl-tigerlake.c Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H PMC GPE group definitionsJeremy Soller
Reference: - TigerLake FSP Change-Id: I666eb710762f6b00d173ee1a473f1f5a612953a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H chipset devicetreeJeremy Soller
Based on the base TGL devicetree, add one specific to TGL-H that adds the additional supported devices. Introduces a new Kconfig for selecting the PCH support. Reference: - Intel doc 615985 Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller
Convert the power limit defines to an enum and add TGL-H entries. Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel: Add TGL-H CPUIDJeremy Soller
Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56942 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"Furquan Shaikh
This reverts commit 68d8357dab55660058ad1ab8dca34fd03e0adbb5. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-24Revert "soc/intel/broadwell/pch: Drop device NVS remainders"Furquan Shaikh
This reverts commit 34bd6ba97917b0bc54bb1f1e106a56b5c03e19ac. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Not reverted: * ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's selection in broadwell is not required. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-20soc/intel/adl: Update power limits for ADL-M SKUSumeet Pawnikar
Update SKU specific power limits for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: I40b9b3a508c549d940e1c2c9e8b4079695b694e6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20soc/intel/adl: Update PCI ID for ADL-M SKUSumeet Pawnikar
Update PCI ID for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: Ia2c5ce270bc421d8a41cc4bc6ce0b51987d2aaec Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20soc/intel/cannonlake: Unbreak some short linesNico Huber
Change-Id: I8c8b49d519b7c6a3d1e4946818b2fc5a1dd1d3e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56663 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19Revert "src/soc/intel/cannonlake: Update C-state latency control limits"Nico Huber
This reverts commit 66dbb0c5d67279722fcbcb547d9c6b61e606d50e. The numbers were meant for Cannon Lake, but the code was also meant to be used for all other platforms using the Cannon Point PCH. Now Cannon Lake support is even dropped, so we can cleanly revert to the recommended values for the other platforms. Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56662 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-19soc/intel/denverton_ns: Sanity check MMCONF_BASE_ADDRESSKyösti Mälkki
According to received feedback, FSP-T enables MMCONF at address 0xe0000000 with 256 busses. Sanity-check that Kconfig matches that. Add MMCONF_BUS_NUMBER such that MCFG in ACPI will be correct. Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-19soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik
This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19soc/intel/alderlake: set default PL4 values for different SKUsSumeet Pawnikar
Set default PL4 values for various Alder Lake CPU SKUs as per bug#191906315 comment#10. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board. Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/common: Add TGL-H PCI IDsJeremy Soller
Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16soc/intel/alderlake: Create eNEM Kconfig for Alder LakeSubrata Banik
Alder Lake SoC specific Kconfig that internally selects all eNEM related Kconfig. CONFIG_ALDERLAKE_CAR_ENHANCED_NEM will get autoselected if platform doesn't have INTEL_CAR_NEM Kconfig selected explicitly. BUG=b:168820083 TEST=Verified CONFIG_INTEL_CAR_NEM is still enable. Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS KconfigSubrata Banik
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enableSubrata Banik
As per TGL EDS doc:575681, two ways will be controlled with one bit of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT for TGL SoC. Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/common: Calculate and configure SF Mask 1Subrata Banik
MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates the maximum number of bits that may be set in any of the SF MASK register. Hence, this patch calculates SF way count using below logic: Calculate SF masks 1: 1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. SFWayCnt = SFWayCnt / 2 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - SF_MASK_2 Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15soc/intel/common: Calculate and configure SF Mask 2Subrata Banik
As per TGL EDS, two ways will be controlled with one bit of SF QoS register hence, this patch introduces SF_MASK_2WAYS_PER_BIT Kconfig to allow SoC users to select SF_MASK_2WAYS_PER_BIT to follow the EDS recommendation. Calculate SF masks 2: 1. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. data_ways = data_ways / 2 Also, program SF Mask#2 using below logic: 2. Set SF_MASK_2 = (1 << data_ways) - 1 Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-13soc/intel/tgl: Hook up ucode for TGL-U and TGL-RTim Crawford
Hook up microcode from 3rdparty repo for: - TGL-U: 06-8c-01 (CPUID signature: 0x806c1) - TGL-R: 06-8c-02 (CPUID signature: 0x806c2) Verified microcode blob was found in CBFS on system76/darp7 (TGL-U). CBFS: Found 'cpu_microcode_blob.bin' @0x103c0 size 0x31c00 in mcache @0x76c2d0ac microcode: sig=0x806c1 pf=0x80 revision=0x88 coreboot reports the correct revision for the microcode. Change-Id: I210c0133dad7ade63b9f7177aaa9a69b019469af Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56862 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/jasperlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/tigerlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/skylake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-clause and adjust comments. This changes behavior since now related options are always set, depending on if coreboot or the FSP should be responsible for the chipset lockdown. This ensures a defined state independent from the default configuration of the FSP. Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/cannonlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause and adjust comments. Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADLV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU specific values from the FSP default value 160. * ADL-P 682(45W) = 137. * ADL-P 482(28W) = 128. * ADL-P 282(15W) = 128. These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56176 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/apollolake: add 4Gb and 6Gb dram densityJamie Chen
This patch adds 4gb and 6gb dram density support to APL and GLK. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: Ic0d5d14f26a30da7a9caf4ef43d7fac88a4d2bf1 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55153 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/apollolake: change LPDDR4 density enum definitionJamie Chen
Originally we use rank_density=0 to mean disable the channel, but actually rank_density=0 means 4Gb density in the FSP. This patch changes the LPDDR4 enum values to the real density number and adds a switch statement to mapping the density define in the FSP. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: I36dba2cef130211e7aea9e2a4f82c5db78f82a83 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56805 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-STim Crawford
Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. TGL also introduces parameters for customizing the default SVID:SSID. These must be set or it will still use the FSP defaults. Tested by checking lspci output on System76 darp7 (TGL-U). References: - b1fa231d76a ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S") - TigerLake FSP Integration Guide - Intel Document #631120-001 Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-11soc/intel/alderlake: Implement report_cache_info() functionSubrata Banik
Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache size = 12 MiB Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-10mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4Tim Wawrzynczak
The code is clearer when ACPI_DEVICE_SLEEP_D3_COLD is used instead of the number 4. Change-Id: I4b0ade1cd0b4b9cdb59f90f8d455269d0b69ed86 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpusMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will always be 0 but as per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can be any processor whose index/APIC ID might not be 0. To handle this situation, init_cpu call is required to modify to handle dynamic detection of APIC ID from BSP instead of hardcoding always through devicetree. Function has been updated to create a new node with actual BSP APIC ID when devicetree doesn't contain APIC ID defined. In case APID ID is defined, function will use a node with the APIC ID defined in devicetree. Changes also requires to remove "lapic 0" hardcoding from devicetree to allow code to fill BSP APIC ID dynamically. Otherwise coreboot will create an extra node for CPU with APIC ID 0 and it'll show as a extra node in kernel. This will cause kernel to report wrong (extra) core count information then actually present. BUG=None BRANCH=None TEST=Boot the JSL system and observe there is no functional impacts. Without this CL kernel core count in `lscpu` = 3 With this CL, kernel core count is corrected to 2. Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05soc/intel/alderlake: Add GFx Device ID 0x46aaBora Guvendik
This CL adds support for new ADL-M graphics Device ID 0x46aa. TEST=boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib24b494b0eedad447f3b2a3d1d80c9941680c25d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04Move post_codes.h to commonlib/console/Ricardo Quesada
Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04soc/intel/cannonlake: Allow to configure maximum package C stateNico Huber
Sometimes it's preferable or even necessary (e.g. stability issues) to limit the maximum package C state. Let's add a devicetree option that keeps the current behavior if it is left unset. Change-Id: I0dc254d34f46de4c65cb85cc92e4b7f26618888d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is givenNico Huber
Change-Id: I4f9b62fd944d8a91d53bc584c88797f23de1e5ca Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-04soc/intel/cannonlake/vr_config: Print configured valuesNico Huber
These values are quite important and our default tables sometimes have holes. We should at least make it visible what the resulting settings are. Change-Id: Ic716d073da1c2638c4b16f2eac01b83a0768d22f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/intel/cannonlake/vr_config: Add TDC values for CFL-H 6+2Nico Huber
Values were taken from PDG (571391), 51.3 IMVP8 Voltage and Current Requirements. Change-Id: Iffa29386cb7da333353dafd0ba3a61ca61a0ccac Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-03soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-02soc/intel/broadwell: Drop early BAR macrosAngel Pons
They are used at most once. Use the actual values and drop the macros. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9c1c3ebbbfa64a5eeea3bd5551c3d0068ac0dab2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55799 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Replace soc/intel/common includeAngel Pons
Broadwell now uses the Lynx Point hda_verb.c and should thus use the corresponding header as well. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9b8ca91bed67be9c6850bd51f4c81e002a0f5aef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55797 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell/pch/pch.c: Drop unused includeAngel Pons
For some reason, this change makes ramstage slightly smaller. Change-Id: I5564e06b797d787f0d1093bd9bd572d1ee7b2d54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55583 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop unused function declarationsAngel Pons
These functions are never defined. Remove the unused declarations. Change-Id: I4204265680d06bf83fc42f061fd7270ff8e3305e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55798 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Rename `ramstage.h`Angel Pons
This file only contains the `broadwell_run_reference_code()` function prototype (either a declaration or an inline stub definition). Rename this file to refcode.h and only include it where necessary. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6513f45b8914a84312b27ef4860870a89fd0aab3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55582 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Rename `SA_DEV_ROOT`Angel Pons
For consistency with Haswell, rename this macro to `HOST_BRIDGE`. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop helper functionsAngel Pons
Done for consistency with Haswell in order to ease unification. Change-Id: I445f086cfcb65a6001ced3326fb9f25a4188b888 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55527 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29soc/intel/elkhartlake: Update UART clock divider paramsLean Sheng Tan
As EHL UART source clock is 120MHz, update the clock divider parameters (M & N) to reflect the right value. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-28util/spd_tools/lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for ADL: 1. H54G46CYRBX267 2. H54G56CYRBX247 3. K4U6E3S4AB-MGCL 4. K4UBE3D4AB-MGCL BUG=b:194686484 b:194765811 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28Revert "soc/intel/common/block/gpio: Add support to program VCCIO selection"Karthikeyan Ramasubramanian
This reverts commit 4c569b52f6053fc39cb07eed4a0753ade567c5b6. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. BUG=None TEST=Build and boot to OS in Storo. Ensure that the regressed peripherals are working back again. Change-Id: Ibfeed1075fe28051b926ddd7ca771693dc19dae8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56613 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28Revert "soc/intel/jasperlake: Enable support to program VCCIO selection"Karthikeyan Ramasubramanian
This reverts commit 16f2c5082c92ceb4defc252819aaeca96d801543. Change-Id: Id0f960fdeca5895afc22809ff3f0236d6dbe82f4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56614 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28soc/intel/jsl: Add disable_external_bypass_vr configSimon Yang
This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake. BUG=b:191691430 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>