diff options
| author | Jeremy Soller <jeremy@system76.com> | 2021-08-12 10:49:58 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-24 14:49:33 +0000 |
| commit | bc071feec18fb7feffbcacde74d101348c65e98e (patch) | |
| tree | 3000fdc6a32fe37f7dc6b01bc9132cf8b3cdcdc9 /src/soc/intel | |
| parent | 83d795c45b602ed1736e80871b2bd5cd2ccf7490 (diff) | |
soc/intel/tigerlake: Add TGL-H PEG ports
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/pcie.asl | 22 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/chip.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pci_devs.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 9 |
4 files changed, 39 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index 8219c653a7..9c98dde129 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -112,6 +112,28 @@ Method (IRQM, 1, Serialized) { } } +Device (PEG0) +{ + Name (_ADR, 0x00060000) +} + +#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) +Device (PEG1) +{ + Name (_ADR, 0x00010000) +} + +Device (PEG2) +{ + Name (_ADR, 0x00010001) +} + +Device (PEG3) +{ + Name (_ADR, 0x00010002) +} +#endif + Device (RP01) { Name (_ADR, 0x001C0000) diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 2fd0f0ee7e..dcdaa1ad93 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -73,6 +73,10 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_CPU_PCIE: return "PEG0"; + case SA_DEVFN_PEG1: return "PEG1"; + case SA_DEVFN_PEG2: return "PEG2"; + case SA_DEVFN_PEG3: return "PEG3"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT1: return "TRP1"; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 5962fa32c2..eee03f980d 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -25,6 +25,11 @@ #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif +#define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 0) +#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 1) +#define SA_DEVFN_PEG3 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index a63386f964..8c8461093e 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -191,7 +191,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ - m_cfg->CpuPcieRpEnableMask = is_devfn_enabled(SA_DEVFN_CPU_PCIE); + m_cfg->CpuPcieRpEnableMask = 0; + const unsigned int cpu_pcie_devs[] = { + SA_DEVFN_CPU_PCIE, SA_DEVFN_PEG1, SA_DEVFN_PEG2, SA_DEVFN_PEG3, + }; + for (i = 0; i < ARRAY_SIZE(cpu_pcie_devs); i++) { + if (is_devfn_enabled(cpu_pcie_devs[i])) + m_cfg->CpuPcieRpEnableMask |= 1 << i; + } /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ m_cfg->TmeEnable = CONFIG(INTEL_TME); |