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2024-01-29device: Add a helper function to add a downstream busArthur Heymans
Adding downstream busses at runtime is a common pattern so add a helper function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26soc/intel/common: Add lunarlake device IDsAppukuttan V K
Added Lunar Lake device IDs the device specific functions Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2024-01-26soc/intel/commonlake: Re-add SATA to soc_api_name() listMatt DeVillier
Now that we've added an ACPI device for SATA, add the name back to the soc_acpi_name() list so the PEPD LPI constraint list generates a valid reference to the SATA device. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80059 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/intel/common/block/sata: Add ACPI stub for SATA deviceMatt DeVillier
Add an ACPI stub containing the SATA device in proper scope, along with the device status, so that there exists a device to be referenced from the PEPD LPI constraint list. Fixes a Windows BSOD INTERNAL_POWER_ERROR on devices with enabled SATA ports. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I951c62d09609ed73079fe97ea9ce49fdee333272 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-26Revert "soc/intel/cannonlake: Add missing min sleep state for thermal device"Matt DeVillier
This reverts commit d64b66ba267a217d0b6716309019c36c8cfdf8c2: "soc/intel/cannonlake: Add missing min sleep state for thermal device." Reverting because commit e00523aae2ea ("soc/intel/cannonlake: Drop entries from soc_acpi_name()") removed the ACPI device name for the PCH thermal device, since there is no ACPI device defined for it. Removing the name without removing the minimum sleep state caused an invalid LPI entry to be created, which caused a Windows BSOD: INTERNAL_POWER_ERROR. TEST=build/boot Win11 on google/puff (wyvern). Change-Id: I2dfe76d5f72cde7742cee338fa24eaafb84c4604 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80057 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24soc/intel: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24soc/intel/xeon_sp/chip_common: Improve the domain IDPatrick Rudolph
Use a union to access the PCI domain ID. This will become handy in the following commits to gather meta-data from the domain ID. Change-Id: I5c371961768410167a571358f6f366847a259eb6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80099 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24soc/intel/cannonlake: Report correct latencies for C statesNico Huber
The C_STATE_LATENCY_FROM_LAT_REG() macro uses values that we also write into the respective MSRs in configure_c_states(). Match the indices to those used there. Change-Id: Ie01a53d6f06bc02a53d95e390e16e9963f4c65ee Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-22soc/intel/xeon_sp: Add IIO resources via SSDTArthur Heymans
There is no need to inject this code in DSDT. Just generating a _CRS Name in SSDT containing a resource template works well and reduces the need to sync up on names being used to return _CRS names in DSDT. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-22soc/intel/xeon_sp: Scan and allocate resources on all stacksArthur Heymans
The code can now deal with stacks that have no resources so just hook them all up. Intel XEON-SP FSP reports all report the state of its stacks, which comprise of PCI root bridges and their respective resources, like PCI busses, IO and MEM resources, via HOB. Parsing all of those into native coreboot structures makes it possible to handle those in a more native fashion like use PCI drivers, native helper functions, ... As opposed parsing those structures again out of the HOB each time. This makes code reuse across the tree more feasible. An additional advantage is that Linux does not need to redo resource allocation since the one done by coreboot will be valid, which potentially decreases boot time. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/78332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-22soc/intel/xeon_sp: Fix devicetree walking upPatrick Rudolph
Connect the PCI domain to the bus to allow walking the devicetree up. This is required to figure out which PCI domain a device belongs to. Change-Id: I8cc50cabf7ad540c52498e1ffe7f9246550ed87b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-01-22soc/intel/cmn/block/pmc: Fix prev_sleep_state string name mappingAnil Kumar
commit d078ef2152052b5ce8686249dcd05ebd50010889 ("soc/intel/cmn/block/pmc: Add previous sleep state strings in log") used SLP_TYP numbers to map ACPI sleep state value. This incorrectly printed wrong string for prev_sleep_state during S5. ex: after a cold reset the previous sleep state printed was [DEBUG] prev_sleep_state 5 (S3) This patch corrects this by using ACPI sleep state numbers for mapping the prev_sleep_state values. TEST=test the logs on google/rex board after cold reset [DEBUG] prev_sleep_state 5 (S5) Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I9bcdacc4d01a8d827a6abdf9af2b9e5d686ed847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80144 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-22soc/intel/meteorlake: Fix system hang by enabling SMI handlingKane Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:306267652 TEST=Cold reboot test on 20 google/screebo by ODM, all passed w/o hang. Change-Id: Ie1f096f8eda4adcf1627e44afa517b02adddad76 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-19device/Kconfig: Move Intel/ACPI/USB4 specific Kconfig optionsArthur Heymans
This options should not be visible on !Intel, !ACPI and !USB4. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia515d52baead9e151533278c33fda9436ee56168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79669 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18soc/intel/braswell: Use {read,write}32p()Elyes Haouas
Change-Id: I00894565efc405a47348236ad7df50071a843487 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77972 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/intel/elkhartlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-16soc/intel/apollolake: Fix PCI memory resource allocReto Buerki
There is a mismatch in how PCI memory resources are allocated on Apollo Lake with the current configuration. While the ACPI code expects resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code allocates them above, leading to the following error messages on Linux: pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref] Tested on up/squared with Linux kernel version 6.1.0. Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS, and by moving the UART base address into the expected range. Thanks to Nico Huber for the help in writing this patch. Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Signed-off-by: Reto Buerki <reet@codelabs.ch> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79957 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-16device: Add support for multiple PCI segment groupsFelix Held
Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new segment_group struct element and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-15soc/intel/xeon_sp: Redesign resource allocationArthur Heymans
The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle IOAT stacks with multiple domains in soc-specific code TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-12soc/intel/xeon_sp: Allocate resources above 4GArthur Heymans
This makes sure that prefetchable mem64 memory gets allocated above 4G which allows non prefetchable resources to be allocated in the tight window below 4G. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79058 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11soc/intel/meteorlake: Enable FSP logo support by defaultSubrata Banik
Enables FSP logo support for Meteor Lake SoC config, covering both Intel Meteor Lake RVP and ChromeOS devices. Applies HAVE_FSP_LOGO_SUPPORT configuration only for platforms with native FSP support. Ensures successful builds and boots for google/rex and intel/mtlrvp. BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex and intel/mtlrvp Change-Id: Ic99bfdc2d33db48bdb015525981c1ef76df8203b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79859 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-09soc/intel/mtl: Override the `SOC_PHYSICAL_ADDRESS_WIDTH` as integerSubrata Banik
This patch enforces consistent override handling for integer `SOC_PHYSICAL_ADDRESS_WIDTH` config Change-Id: Ib5bdfdb8c2689803c9d3c2bfd353609edae91ab3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-02soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verificationJeremy Compostella
Enabling SSE2 accelerated RSA signature verification saves 4.7 ms of boot time. | modpow() function call | original | SSE2 Algorithm 2 | |----------------------------+----------+------------------| | coreboot/verstage - step 1 | 6.644 | 3.042 | | coreboot/verstage - step 2 | 1.891 | 0.757 | |----------------------------+----------+------------------| | Total (ms) | 8.535 | 3.799 | BUG=b:312709384 TEST=modular exponentiation is more than twice faster on rex0 Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79291 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/intel/alderlake: Make C1e configurableSean Rhodes
Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/intel/xeon/spr: Enforce POR frequency settingNaresh Solanki
For RMT build, add kconfig option to enforce Plan Of Record restriction on DDR5 frequency & voltage settings. Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-22soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPDSubrata Banik
This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22soc/intel/cmn/block/pmc: Add previous sleep state strings in logMarx Wang
Previous sleep state showing in serial log is a magic number. In order to let users understand its meanings directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [DEBUG] prev_sleep_state 0 with this change: [DEBUG] prev_sleep_state 0 (S0) Change-Id: Iabe63610d3416b3b6e823746e3ccc5116fabb17d Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-22soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42Jeremy Compostella
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22x86: Separate CPU and SoC physical address sizeJeremy Compostella
The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22Revert "soc/intel/meteorlake: Set build time physical address reserved bits"Jeremy Compostella
This reverts commit 533efb23083afd721d4c268ce0ee8e863e13689a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79664 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20soc/intel/common,mtl: Refactor BERT generation flow for crashlogPratikkumar Prajapati
With earlier flow, a chunk of CBMEM region was allocated for each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM content was copied to dedicated CBMEM region. Later in acpi_bert.c, the BERT table was getting created for each chunk of CBMEM. This flow was not considering creating separate entries for each region of crashlog records. It resulted in only the first entry getting decoded from each SRAM. New flow aims to fix this issue. With new flow, a simple singly linked list is created to store each region of crashlog records from all SRAMs. The crashlog data is not copied to CBMEM. The nodes are allocated dynamically and then copied to ACPI BERT table and then freed. This flow also makes the overall crashlog code much simpler. BUG=b:298234592 TEST=With this change decoding crashlog show comprehensive details, tested on REX. Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDsSubrata Banik
This patch allows to override acoustic noise mitigation FSP UPDs: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:312405633 TEST=Able to override the acoustic noise UPDs. Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79302 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-18soc/intel/mtl: Adaptively disable 3-strike error for QS siliconSubrata Banik
This patch provides a way to mask the 3-strike error on Intel Meteor Lake SoC platform across pre-prod and prod SoC. This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types. Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error. BUG=b:314883362 TEST=Disable the 3-strike on google/screebo with QS silicon. Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15soc/intel/cmn/cpu: Introduce API to disable signaling 3-strike eventSubrata Banik
This patch introduces a new API to disable signaling the 3-strike event on Intel Meteor Lake C0 (QS) stepping and subsequent SoCs. This is necessary because the existing event handling mechanism is incompatible with the new hardware design. Disabling the 3-strike event registration prevents the 3-strike count from increasing, which addresses bug b:314883362. This issue can potentially lead to system instability. BUG=b:314883362 TEST=disabling the 3-strike event on a Google Screebo system with QS silicon. Change-Id: I15bd5a93da34d7f2a127c21c4cd8b5952926bccf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79472 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard pathKulkarni, Srinivas
Move the existing FSP 4301.01 headers for Raptor Lake out of subdirectory called 43101.01 to follow standard process. Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-11soc/intel/meteorlake: Add entries to eventLog on invocation of early SOLSubrata Banik
This patch records early signs of user activity during CSE firmware synchronization or MRC (re)training events in the event log (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:279173035 TEST=Verified on google/rex, event shows in eventlog after CSE sync and/or MRC. Scenario #1: While performing MRC update 1 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2023-11-08 | Memory Cache Update | Normal | Success 3 | 2023-11-08 | System boot | 9 4 | 2023-11-08 | ACPI Wake | S5 Scenario #2: While performing CSE update/downgrade 11 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 12 | 2023-11-08 | System boot | 13 Scenario #2: While performing both MRC and CSE upgrade 16 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 17 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 18 | 2023-11-08 | Memory Cache Update | Normal | Success 19 | 2023-11-08 | System boot | 16 20 | 2023-11-08 | ACPI Wake | S5 Change-Id: Idfa6f216194fd311bb1a57dd7c86fe7446a3597c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78983 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-11soc/intel/mtl: Display Sign-of-Life message using FSP-MJeremy Compostella
Meteor Lake Firmware Support Package (FSP-M) for ChromeOS includes an pre-memory graphics driver which can be leveraged to display a text message thanks to the following FSP-M UPD (Updateable Product Data): - VgaInitControl (bitfield): Bit 0: Turn on graphics, setup VGA text mode and display `VgaMessage' text centered on the screen. Bit 1: Clear text and tear down VGA text mode and graphics before returning from FSP-M. - VbtPtr (address): Pointer to the VBT (Video BIOS Tables) binary. - VbtSize (unsigned int): Size of the VBT binary. - LidStatus (boolean): Due to limited resources at early boot stages, the text message is displayed on a single monitor. The lid status helps decide which display is the most appropriate. 0: Lid is closed: show the text message on the external display if available, do not display anything otherwise. 1: Lid is open: show the message on the internal display if available, use an external display if available otherwise. - VgaMessage (string): Text message to display. If the `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' flag is set, coreboot configures the UPDs above to display a text message during memory training and CSME update. The text message can be configured via the locale text mechanism using the `memory_training_desc' name. The `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' selects the LZ4 compression algorithm for VBT because LZMA decompression is not available in romstage by default and adding LZMA support increases the romstage binary size more than the VBT binary is reduced. BUG=b:279173035 TEST=Text message is displayed during memory training on a rex board Change-Id: I8e7772582b1895fa8e38780932346683be998558 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78244 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11soc/intel/cse: Add API to check if CSE Firmware update is requiredAnil Kumar
This patch adds a function to check if a CSE FW update is required during this boot. The function is expected to be used during use cases like Pre-Memory Sign of Life text display to inform user of a CSE Firmware update. Bug=279173035 TEST=build and boot on google/rex board. Call the function in romstage and confirm it returns True during CSE FW update and False otherwise Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If5fae95786d28d586566881bc4436812754636ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/78243 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-11soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDsKilari Raasi
By default MarginLimitCheck and RMC UPDs are enabled in FSP which enables fast and cold boot retraining causing the boot time increase. So, disabling the same UPDs to fix it. Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-04soc/intel/alderlake: Update LidStatus UPD dynamicallySubrata Banik
This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:313886118 TEST=Able to build and boot google/marasov to redirect the display using external HDMI monitor while LID is closed. Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21soc/intel/mtl: Keep SOC_INTEL_COMMON_BASECODE_RAMTOP for non-ChromeOSSubrata Banik
This patch guarantees that non-ChromeOS platforms continue to enable early caching. ChromeOS devices, on the other hand, control this configuration through the motherboard configuration based on the underlying SoC. BUG=b:306677879 TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex. Change-Id: I412b2b6a807dc0f5f2632f0fbd56bd37689dead3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-14soc/intel/cannonlake: Drop entries from soc_acpi_name()Matt DeVillier
The THRM and SATA PCI devices do not currently have any ACPI devices defined, so drop them from soc_acpi_name() so they do not end up in the LPI constraint list. This eliminates the following errors under Linux: AE_NOT_FOUND: _SB_.PCI0.THRM AE_NOT_FOUND: _SB_.PCI0.SATA TEST= build/boot google/hatch (jinlon) and verify no ACPI errors. Change-Id: I3827b152644e2eaecc1ad288d441d2dad4d76ccb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79013 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-14soc/intel/cmn/block/cse: Support sending EOP from payloadKapil Porwal
Skip sending EOP from coreboot when payload is sending it. BUG=b:279184514 TEST=Verify sending EOP from depthcharge on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fbb9fd0f8522eefad39960ca3167c2ba764f523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74765 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-10soc/intel/alderlake: Allow using FSP repo for all RPL-S platformsMichał Żygowski
The Client FSP for Raptor Lake-S is present on the Intel FSP repository, so there is no need to restrict Raptor Lake-S FSP binary repository to IoT only. TEST=Build and boot MSI PRO Z790-P Change-Id: I77aecd6e2d753732bf6358afe2c7ea0491348387 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-10soc/alderlake: Fix order of defaults in FSP_HEADER_PATHMichał Żygowski
The combination of SOC_INTEL_RAPTORLAKE_PCH_S and FSP_TYPE_IOT is currently broken. By default, e.g. for MSI PRO Z790-P, the FSP_HEADER_PATH does not match the default FSP_FD_PATH. For headers the client FSP is selected, while for the FD file, IoT FSP binary is chosen. The order of default for both headers and FD file must be the same to match the headers and binaries. TEST=Build default MSI PRO Z790-P config and see that FSP_HEADER_PATH matches FSP_FD_PATH FSP variant-wise. Change-Id: I8db5ea10c2986ff8d3fa7d616b3f1617d05f0260 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78410 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-10soc/intel/meteorlake: Set DTT PCI device IRQ to INT_A/PIRQ_AJeremy Compostella
The Dynamic Tuning Technology (DTT) device IRQ is not programmable and is INT_A/PIRQ_A (IRQ 16). Reference: Meteor Lake U/H and U Type4 External Design Specification External Design Document (657165) TEST=Linux driver successfully uses IRQ 16 on rex. Without this patch it was binding IRQ 18 but interrupts were going to IRQ 16. Change-Id: I2cbb9dd41f27c40a29346be325bb9c46d1061afb Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-10device/Kconfig: rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORTFelix Held
Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help text to this Kconfig option to clarify what this option is about. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-09Allow to build romstage sources inside the bootblockArthur Heymans
Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-07Revert "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. Reason for revert: It breaks wakeup from suspend on a bunch of boards. While this approach of eyeballing "correct" values by chipset _should_ be fixed, it should also be accompanied by compile time verification that the memory map works out. Since nobody seems to care enough, let's just revert this, instead of keeping the tree broken for a bunch of configurations. Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-04soc/intel/meteorlake: Consolidate settings for enabling tracehubKane Chen
To get tracehub working, it requires few settings such as SOC_INTEL_METEORLAKE_DEBUG_CONSENT=2 and enable tracehub device in dev tree. This commit binds all tracehub related settings to Kconfig, so that users only need to enable SOC_INTEL_COMMON_BLOCK_TRACEHUB TEST=boot on screebo and test tracehub device exists and working Change-Id: Ie830fe2fd38e3456497bea37fe42ca60d26ca305 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-04soc/intel/alderlake: Add missing min sleep state for DPTF deviceMatt DeVillier
Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:04.0 TEST=build/boot google/brya (banshee), verify warning not present in cbmem log, verify entry for DPTF device in ACPI LPI constraint list. Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78877 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-03soc/intel/braswell/Kconfig: Set HPET_MIN_TICKSMatt DeVillier
Commit 2bc9cee0f70f ("Braswell: Update the ACPI tables") switched the SoC from using its own HPET generation code to the common x86 code, but along the way the min_tick value got lost. Restore the original value prior to the above commit, which is now set via a Kconfig override. TEST=build/boot google/cyan (edgar), verify min_tick value in HPET ACPI table is correct. Change-Id: I2633e7cd0c3d74c1554ae8c1f2bb6387fd6dde2b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78744 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-03soc/intel/braswell: Unify DPTF enablementMatt DeVillier
Currently, there are 3 separate settings for DPTF which are not always in sync: - the enabled/disabled state of the devicetree PCI device - the 'dptf_enable' register, which sets the ACPI device status via GNVS - the 'DptfDisable' register, which sets the FSP UPD of the same name To make things sane, drop the two chip registers, and set the GNVS variable and FSP UPD based on the enabled/disabled status of the DPTF PCI device in the mainboard's devicetree. TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI devices are present/enabled when DPTF is enabled in devicetree, and not present/disabled when disabled in devicetree. Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-03soc/intel/cannonlake: Add missing entry to soc_acpi_name()Matt DeVillier
The device name for the SA thermal/DPTF PCI device was missing from soc_acpi_name(), leading to an invalid PLI device constraint entry being generated in the SSDT (the name field was blank/missing). Add the missing entry, matching the name to the existing ACPI device. TEST=build/boot Win11 on google/puff (wyvern) without a BSOD. Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78869 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-03soc/intel/cannonlake: Add missing min sleep state for thermal deviceMatt DeVillier
Add an entry in the min_pci_sleep_states array for SA_DEVFN_THERMAL, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:12.0 TEST=build/boot google/puff (wyvern), verify warning not present in cbmem log, verify entry for THRM device in ACPI LPI constraint list. Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78868 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-03soc/intel/cmn/gfx: Join MBUS while FSP-S performs GFX initSubrata Banik
This patch calls into the function to join the MBUS if the GFX PEIM module inside the FSP binary is taking care of graphics initialization based on the RUN_FSP_GOP config option. The FW skips joining the MBUS in case of a non-FSP solution and/or SOC_INTEL_GFX_MBUS_JOIN config is not enabled. BUG=b:284799726 TEST=MBUS joining is only applicable for google/rex while using GFX PEIM. Change-Id: I50d719a286722f5aafbad48ab4ca60500c836dd6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-02Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version"Ravi Sarawadi
This reverts commit 2e10a6d6f3ec46bcaf75bd066319d51f001be764. Reason for revert: The FW version check is not supported except for ADL platform. Reverted change broke S0ix functionality; the original CL was added as HW W/A for ADL ONLY. BUG=b:306214725 TEST=S0ix cycles on Rex with TBT Device attached. Change-Id: Ib8eb11d36eac4e1c94a3349386442fa3eeeaef37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02drivers/intel/gma/opregion: Use CBFS cache to load VBTJeremy Compostella
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-02soc/intel/*: Correct ACPI device name for eMMCMatt DeVillier
The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-01soc/intel/cmn/gfx: Fix GFX modeset issue with dual-displaySubrata Banik
This patch fixes the redundent GFX modeset issue when a dual display is attached (e.g. an eDP display and an HDMI display). The issue was caused by the MBUS joining logic not considering the display type. This patch introduces three types of display: internal, external, and dual-display. The MBUS joining logic is then updated to consider the display type and ensure that the correct pipes are joined to the MBUS: For internal-only displays, only PIPE-A is joined to the MBUS. For external displays, no pipes are joined to the MBUS. For dual-displays, all available pipes are joined to the MBUS. BUG=b:284799726 TEST=Able to fix the redundent modeset issue when eDP and HDMI attached to the google/rex. Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78691 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01soc/intel/meteorlake: Adjust Power State Current 2 thresholdJeremy Compostella
VccSA Power State 2 (PS2) current threshold has be adjusted to 10A to improve PS2 residency which reduces Voltage Regular (VR) power loss. BUG=b:308002192 TEST=power and performance analysis shows a positive Load Line result Change-Id: I2da2b05de8a04f91dacaa55062165c4351422865 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-01soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKUCurtis Chen
This commit adds power limit settings for 4+8 28W SOC sku and renames MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W settings. BUG=b:306677879 TEST=boot on rex with 4+8 SOC and power limit settings are correct Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78796 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31soc/intel/cannonlake: Implement SoC sleep state arrayMatt DeVillier
Adapted from Alderlake implementation, modified as needed. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/hatch (akemi). Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-31soc/intel/tigerlake: Implement SoC sleep state arrayMatt DeVillier
Copied from Alderlake implementation, modified as needed for Tigerlake. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/volteer (drobit). Change-Id: I34999891ea0d386328698109b6315d481de7c43a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78521 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-28soc/intel/meteorlake: Expose In-Band ECC UPD config to mainboardMarx Wang
Meteor Lake has a UPD config called In-Band ECC(IBECC) which uses a part of the system DRAM to store the ECC information. There are a few UPD parameters in FSP-M to configure this feature as needed. This patch adds code to expose these parameters to the devicetree so that they can be configured on the mainboard level as needed. Change-Id: Ice1ede430d36dff4175a92941ee85cc933fa56d5 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28soc/intel/meteoerlake: Add power limits for 2+4 15W SOC SKUKane Chen
This commit adds power limit settings for 2+4 15w SOC sku and renames MTL_P_282_CORE to MTL_P_282_242_CORE since they are sharing same 15w settings. BUG=b:306543967 TEST=boot on rex with 2+4 SOC and power limit settings are correct Change-Id: Id738303d1652f964142f8f27110426d6b84609bf Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78495 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27soc/intel/cse: remove cbfs_unverified_area_map() API in cse_liteRizwan Qureshi
With CBFS verification feature (CONFIG_VBOOT_CBFS_INTEGRATION) being enabled, we can now remove cbfs_unverified_area_map() APIs which are potential cause of security issues as they skip verification. These APIs were used earlier to skip verification and hence save boot time. With CBFS verification enabled, the files are verified only when being loaded so we can now use cbfs_cbmem_alloc()/cbfs_map function to load them. BUG=b:284382452 Change-Id: Ie0266e50463926b8d377825142afda7f44754eb7 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78214 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-10-26soc/intel/cannonlake: Add/use chipset devicetreesMatt DeVillier
Change-Id: I8ceae832e60cd3094b4a34ab3a279e5a011f2c80 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26soc/intel/apollolake: Select USE_LEGACY_8254_TIMERSean Rhodes
CB:77409 corrected what the UPD `Timer8254ClkSetting` was set to; this stopped a few boards from booting. Selecting USE_LEGACY_8254_TIMER ensures that the previous behaviour is maintained. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibf898cae6c9fbaf3dc7184eee745278d9b5eade4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78504 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25cbmem.h: Drop cbmem_possible_online in favor of ENV_HAS_CBMEMArthur Heymans
The macro ENV_HAS_CBMEM achieves the same as this inline function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6d65ca51c863abe2106f794398ddd7d7d9ac4b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-10-24soc/intel/meteorlake: Add PsysPmax configurationJakub Czapiga
psys_pmax_watts is configured in SoC node of devicetree. Value represents Watts the PSU provides. Zero means automatic/default configuration (not optimal). BUG=b:289853442 TEST=Build google/rex/ovis4es target board Change-Id: I69afa06110254f6384352c062891c0c9c0b23070 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76796 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23soc/intel/cannonlake: Add ACPI devices for FSPI, SRAM, HEC1Matt DeVillier
Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: I3b85fec3de8f33d338425a417cc8b0f5290a5e4f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78520 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-23soc/intel/tigerlake: Add ACPI devices for FSPI, SRAM, HEC1Matt DeVillier
Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: Ib70dc29f54d28ec1fe7b630ab3fab24bcdd08154 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78519 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23soc/intel/common/acpi: Don't generate LPI constraints for disabled/hidden ↵Matt DeVillier
devices When walking the devicetree to generate the list of devices and minimum sleep states, skip any devices which have the disable or hidden flags set. This prevents adding entries for devices which are not present, which are hidden (and likely to not have a min sleep state entry), or generating duplicate entries in the case of PCIe remapping. Any of these conditions are considered invalid by Windows and will result in a BSOD with an INTERNAL_POWER_ERROR. TEST=tested with rest of patch train Change-Id: I06f64a72c82b9e03dc8af18700d24b3d10b7d3a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-23soc/intel/common/pcie: Disable removed RPs when updating devicetreeMatt DeVillier
If a root port is not present but was enabled in the devicetree, mark it disabled so that no ACPI references will be generated by any function which walks the devicetree (eg, LPI constraints). TEST=tested with rest of patch train Change-Id: I52e23fb1c0148a599ed736fc294e593ebbd27860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78517 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20soc/intel/meteorlake: Set build time physical address reserved bitsJeremy Compostella
Meteor Lake TME bits [42-45] are reserved regardless of if the part supports TME or not. On a device with TME fused off, we noticed some reboot hangs which have been narrowed down to internal IP routing issues when the IA accesses the Input Output Manager (IOM) which is mapped at 0x3fff0aa0000 (0x3ff upper 32 bits). It turns out since TME is fused off, coreboot uses the full physical address size reported by CPUID MAXPHYADDR (46 bits). Therefore, it allocates thunderbolt memory range on 46 bits (0x3fff upper 32 bits). Since 4 of these bits are actually reserved, it seems that this address range is "stripped down" to 42 bits (=> 0x3ff upper 32 bits) resulting in potential conflict with other devices such as IOM. BUG=b:288978352 TEST=No reboot issue on rex with TME fused off Change-Id: I96ba23ab304257003c0413243d3ac8129ce31743 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78452 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20x86: Add pre-memory stages CBFS cache scratchpad supportJeremy Compostella
Having a CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region. This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set the pre-memory stages CBFS cache size. A cache size of zero disables the CBFS cache feature. The default value is 16 KB which seems a reasonable minimal value enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform needs and capabilities. We have set this size to zero for all the platforms without enough space in Cache-As-RAM to accommodate the default size. TEST=Decompression of vbt.bin in romstage on rex using cbfs_map() Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-20soc/intel/cannonlake: Support Comet Lake v1 and v2 in one buildJonathon Hall
Define SOC_INTEL_COMETLAKE_1_2, which creates a build supporting both Comet Lake v1 and v2 by including both sets of FSP binaries and selecting one based on the CPUID. A mainboard can select this instead of SOC_INTEL_COMETLAKE_1 or ..._2 to support all CML-U steppings in one build. Change-Id: Ic8bf444560fd6b57064c47faf038643fabde010e Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78345 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-10-19soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QSRavi Sarawadi
Within TBT PCIe, following register offsets have been updated for production silicon. Update ASL with new offsets. 1. MPC - Miscellaneous Port Configuration Register 2. RPPGEN - Root Port Power Gating Enable 3. SMSCS - SMI/SCI Status Register BUG=306026121 TEST= Check TBT PCIe Tunnel creation and device enumration. Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-19soc/intel: Improve CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ useJeremy Compostella
Commit bd9c562a9e0c6af65f5e798a17ba9a55892ef082 ("acpi: Configure slp-s0 residency counter frequency in LPIT table") led to jenkins reporting the following error: !!!!! Error: defined(CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ) used at src/include/acpi/acpi.h:457. Symbols of type 'hex' are always defined. Since hex Kconfig are always defined there is no need to test it being defined but also no need to handle zero or non-zero values. In addition: 1. This config was defined in Meteor Lake specific Kconfig file while it should actually be define closer to where it is being used (here soc/intel/common/block/acpi/Kconfig) and only set by the SoC Kconfig. 2. Once moved and under control of `SOC_INTEL_COMMON_BLOCK_ACPI_LPIT' gating (lpit.c), the Kconfig name needed to be adjusted to better fit its use. 3. Make Meteor Lake Kconfig sets the config but does not define it anymore. TEST=LPIT ACPI table Counter Frequency field is set to 0x2005 on rex Change-Id: I2083c9209e61be6180cca2c9f74097e2f4b4ce9a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78458 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-19soc/intel/alderlake: Fix incorrect microcode commentsMichał Żygowski
The microcode for RPL-S C0 and H0 is actually available, however, the name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos in the comments. Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256 sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256 sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag microcode-20230808: 5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9 Update the comments to correctly indicate supported CPU steppings. Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-19vc/intel/raptorlake: Use FSP v4301.01 headers for GoogleNick Vaccaro
Remove the existing FSP 4221.00 headers subdirectory called 4221.00_google, and have Google vendor devices use FSP 4301.01. BUG=b:306181828 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: Ic64b3aec62f0d6302278393bf06d090f43c0d592 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <srinivas.kulkarni@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-18soc/intel/mtl: Set slp-s0 counter frequencySukumar Ghorai
System sleep time (SLP_S0 signal asserted) is measured in ticks, for Meteor Lake soc in 122us (i.e. ~8197Hz) granularity/ticks. Change-Id: I1e95cd69e941d4d72d5c36a07660ca07ee2499ba Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-18soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUSSubrata Banik
This patch ensures that the IGD joins the MBUS when the firmware splash screen feature is enabled (aka BMP_LOGO config is enabled). For ChromeOS platform, it prevents the i915 driver from reinitializing the display, which can save up to 75ms-80ms of boot time and eliminate a brief period of blank screen between the firmware splash screen and the OS login prompt. BUG=b:284799726 TEST=Able to build and boot google/rex. Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-18soc/intel/cmn/graphics: Implement API for IGD to join the MBUSSubrata Banik
This patch implements `.final` hooks for the IGD device to perform the required operations before handing the control to the payload or OS. The MBUS (Memory Bus) is a high-speed interface that connects the graphics controller to the system memory. It provides a dedicated data path for graphics data, which helps to improve graphics performance. The MBUS is a key technology that helps to make the Intel i915 driver powerful and versatile graphics drivers available. It provides the high-speed data transfer capabilities that are essential for smooth and responsive graphics performance. Enable this config to ensure that the Intel GFX controller joins the MBUS before the i915 driver is loaded. This is necessary to prevent the i915 driver from re-initializing the display if the firmware has already initialized it. Without this config, the i915 driver will initialize the display to bring up the login screen although the firmware has initialized the display using the GFX MMIO registers and framebuffer. Kernel graphics driver can avoid redundant display init by firmware, which can optimize boot time by ~15ms-30ms. Ensures hashing mode is 1x4 to enable a single pipe between Pipe A or B. Typically, internal display is on Pipe-A, so 1x4 restricts MBUS joining to internal display alone. BUG=b:284799726 TEST=Able to build and boot google/rex Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78385 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-16soc/intel/alderlake: Add config for Client RPL FSP supportBora Guvendik
For Raptor Lake, select Raptor Lake's .fd file and header. TEST=Boot to OS on Google Brya board with RPL silicon. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-16soc/intel/cmn/gfx: Detect dual display (eDP + HDMI)Subrata Banik
This patch adds support for detecting dual displays (eDP and HDMI) on Intel platforms. This information is useful for setting the `lb_framebuffer.has_external_display` variable, which is used to determine whether depthchage should avoid shutting down when an extended display is present. TEST= Able to build and boot google/rex, where depthchage now successfully avoids shutting down when both eDP and HDMI displays are attached. w/o this patch: with eDP and HDMI attached: .has_external_display=0 with eDP attached: .has_external_display=0 with HDMI attached: .has_external_display=1 w/ this patch: with eDP and HDMI attached: .has_external_display = 1 with eDP attached: .has_external_display=0 with HDMI attached: .has_external_display=1 Change-Id: Ie39d48da75a21e3508a1fbcf09da31caedaa1c0a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78383 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-16soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BARMichał Żygowski
Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. There is no telling what could happen if the reservation is not made in ACPI. TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4 Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77445 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-13soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetreeNaresh Solanki
The board has three SATA controllers, so add the remaining two on PCI device 18.0 and 19.0. TEST=Verify in lspci the sata controllers. Change-Id: Ia654c4ef895b52338554d89c25f61b262fbbcbbb Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77892 Reviewed-by: Annie Chen <chen.annieet@inventec.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-10-13soc/intel/cse: Remove unused header fileKrishna Prasad Bhat
Systemagent related functions are not used in this file. Remove the unused the header file. Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78312 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-11Kconfig: Bring HEAP_SIZE to a common, large valuePatrick Georgi
We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-09soc/intel/meteorlake: Reserve IOE P2SB MMIO correctlyKane Chen
The original code only reserves IOM mmio, but there is other asl code that requires to program ioe p2sb mmio such as IOE PCIE clk request control. See \_SB.ECLK.CLKD in src/soc/intel/common/acpi/pcie_clk.asl TEST=as before: suspend_stress_test 50 cycle pass, type-c display OK on screebo Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78252 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-07mb/google/{rex,ovis}: Disable package C-state auto demotionSukumar Ghorai
Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. BUG=b:303546334 TEST=Local build successfully & Boot to OS successfully - Also check platform enter PC8 state in local video playback - before this change: # iotools rdmsr 0 0xE2 -> 0x0000000060008008 - After # iotools rdmsr 0 0xE2 -> 0x0000000000008008 Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78250 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-05soc/intel: separate slp-s0 residency counter frequency in LPIT tableSukumar Ghorai
Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Whereas slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created after kernel boot cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cmn/gfx: Add API to report presence of external displaySubrata Banik
This patch implements an API to report the presence of an external display on Intel silicon. The API uses information from the transcoder and framebuffer to determine if an external display is connected. For example, if the transcoder is attached to any DDI ports other than DDI-A (eDP), and the framebuffer is initialized, then it is likely that an external display is present. This information can be used by payloads to determine whether or not to power on the display, even if eDP is not initialized. BUG=b:299137940 TEST=Build and boot google/rex Scenarios: Booting with eDP alone: has_external_display value is 0 Booting with eDP + HDMI: has_external_display value is 0 Booting with HDMI alone: has_external_display value is 1 Booting with USB-C display alone: has_external_display value is 1 Change-Id: I77436940978c7fa9368d79394b46a5e794c32e42 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78080 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defsSubrata Banik
Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed since Tiger Lake. This register is used to map ports and pipes to display controllers, so reflecting the correct status is important for detecting physical display end point devices. This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to properly reflect the updated port and pipe register definitions. BUG=b:299137940 TEST=Build and boot google/rex successfully. Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04soc/intel/jasperlake: Enable wake from USBReka Norman
Use the common UWES ACPI method to enable wake from USB. The only difference to other SoCs is that JSL only has 8 USB2 ports, so the USB3 PORTSC register offset is different. BUG=b:300844110 TEST=When enabled on taranza, all USB2 and USB3 ports can wake from suspend Change-Id: Ibc90246965d5d809123e954847543d28d78498a5 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78086 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2023-10-04soc/intel: Move USB wake methods to a common ASL fileReka Norman
The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 05:45:04 +0000