diff options
| author | Kilari Raasi <kilari.raasi@intel.com> | 2023-11-07 14:05:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-12-11 05:06:18 +0000 |
| commit | ebb28c523ef154beee3e9afdc6262df7ce28e03c (patch) | |
| tree | 24117bbce13331ada1476d3b5251df7973dab9a9 /src/soc/intel | |
| parent | b21bc9d9dffd84886081462cd0555f201e023f4b (diff) | |
soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDs
By default MarginLimitCheck and RMC UPDs are enabled in FSP
which enables fast and cold boot retraining causing the
boot time increase. So, disabling the same UPDs to fix it.
Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 9534fc19ef..81ad9dd6a4 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -156,6 +156,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, } m_cfg->RMT = config->rmt; + m_cfg->RMC = 0; + m_cfg->MarginLimitCheck = 0; /* Enable MRC Fast Boot */ m_cfg->MrcFastBoot = 1; m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; |